JPS6066454A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6066454A JPS6066454A JP58174801A JP17480183A JPS6066454A JP S6066454 A JPS6066454 A JP S6066454A JP 58174801 A JP58174801 A JP 58174801A JP 17480183 A JP17480183 A JP 17480183A JP S6066454 A JPS6066454 A JP S6066454A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- holes
- lead frame
- package
- inner leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、プラスチックパッケージを有する半導体装置
に係り、特にリードフレームの半導体素子載置部に連接
する吊りピンおよび半導体素子の外部ピンとして接続さ
れるインナーリードの構造に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device having a plastic package, and particularly to a hanging pin connected to a semiconductor element mounting portion of a lead frame and an external pin of the semiconductor element. Regarding the structure of the inner lead.
第１図（ａ）は従来のフラットパッケージ型の半導体装
＆１を示すもので、その内部は第１図（ｂ）、（Ｃ）に
示すように構成されていた。即ち、２は半導体素子ペレ
ット、３はリードフレームの素子載置部であって、その
上に前記ペレット２が接着剤４により固着されている。FIG. 1(a) shows a conventional flat package type semiconductor device &1, the interior of which was constructed as shown in FIGS. 1(b) and 1(C). That is, 2 is a semiconductor element pellet, 3 is an element mounting part of a lead frame, and the pellet 2 is fixed thereon by an adhesive 4.
５は上記素子載置部３に連通する吊りピンであって、半
導体装置の製造段階ではリードフｌ／一ノ・の外枠部に
も連通しているが、最終的にはモールド樹脂６外へ突出
しないように切断ｇｈている。７は前記ペレット２に金
線８を介］２て接続さわるインナーリードであって、半
導体装１りの製造段階ではリードフレームに連接して支
持さねているが、最終的にはモールド樹脂６から所定長
さだけ突出した部分で切断されている。なお、リードフ
レームはニッケル合金もしくは銅合金からなり、そのう
ち前記素子載置部３、吊りピン５、インナーリード７の
モールド樹脂内端部付近はそれぞれ銀メッキあるいは金
メッキが施さ力ており、このメッキ部を図中斜線にて示
している。また、前記モールド樹脂６は、素子載置部３
およびその上に固着されたペレット２ならびに吊りビン
５、インナーリード７、金線８を一体的に固定して内蔵
するパッケージとなっている。Reference numeral 5 denotes a hanging pin that communicates with the element mounting section 3, and at the manufacturing stage of the semiconductor device, it also communicates with the outer frame of the lead flask, but ultimately the pin 5 is connected to the outside of the mold resin 6. It is cut so that it does not protrude. Reference numeral 7 denotes an inner lead which is connected to the pellet 2 via a gold wire 8. Although it is connected to and supported by a lead frame at the manufacturing stage of the semiconductor device 1, it is ultimately connected to the mold resin 6. It is cut at a portion that protrudes a predetermined length from the base. The lead frame is made of nickel alloy or copper alloy, and the inner ends of the molded resin of the element mounting portion 3, hanging pins 5, and inner leads 7 are each plated with silver or gold. is indicated by diagonal lines in the figure. Further, the mold resin 6 is attached to the element mounting portion 3
The pellet 2 fixed thereon, the hanging bottle 5, the inner lead 7, and the gold wire 8 are integrally fixed and built into the package.
ところで、上述したようなプラスチックパッケージ型の
半導体装置は、製品段階での半田ジャブ漬け（浸漬半田
付け）に際して、そのときのヒートショックによりパッ
ケージ内の各材料の界面に熱応力が生じる。これは、各
材料の熱膨張係数が違うために起こるもので、この応力
は特にモールド樹脂６とペレット２との間、モールド樹
脂６とリードフレーム部との間で太きい。そして、この
ように生じた応力に対して、モールド樹脂６の耐弾性が
弱い場合にはパッケージの外形変形が起きる欠点があっ
た。また、前記応力により、モールド樹脂６とインナー
リード７との間およびモールド樹脂６と吊りビン５との
間で密着性が悪くなって隙間が生じる。By the way, when the above-mentioned plastic package type semiconductor device is subjected to solder jab dipping (immersion soldering) at the product stage, thermal stress is generated at the interface between each material in the package due to the heat shock at that time. This occurs because the coefficients of thermal expansion of each material are different, and this stress is particularly large between the mold resin 6 and the pellet 2 and between the mold resin 6 and the lead frame portion. If the mold resin 6 has weak elasticity against the stress generated in this way, there is a drawback that the outer shape of the package may be deformed. Further, due to the stress, the adhesion between the mold resin 6 and the inner lead 7 and between the mold resin 6 and the hanging bottle 5 deteriorates, and gaps are created.
このため、半田ジャブ漬は後の４湿性試験時に、パッケ
ージ外から上記隙間を通って水分とが水分と同時に汚染
物がパッケージ内に浸入し易くなり、これによって製品
不良が多く発生する原因となっている。また、前記半田
ジャブ漬けに際して、パンケージ内に水分を含んでいた
場合には内部で発生する熱応力は増長する部面があるの
で、パッケージ内への水分の浸入を防ぐ対策が特に必要
である。For this reason, solder jab dipping makes it easier for contaminants to infiltrate into the package from outside the package through the above-mentioned gap during the subsequent 4 humidity tests, and this causes many product defects. ing. Further, when the solder jab is soaked, if the pan cage contains moisture, the thermal stress generated inside the pan cage will increase, so it is especially necessary to take measures to prevent moisture from penetrating into the package.
本発明は上記の事情に鑑みてなさｈたもので、プラスチ
ックバラゲージ内に外部から水分が浸入し難く、パッケ
ージ外形の渡形が生じ維く、モールド樹脂と吊りビンお
よびインナーリードとの密着性が良くて隙間が生じ絆＜
、１酬湿性の良い半導体装置を提供するものである。The present invention has been developed in view of the above circumstances, and has the following features: it is difficult for moisture to enter the plastic baggage from the outside, it maintains the shape of the package, and it has good adhesion between the mold resin, the hanging bottle, and the inner lead. It is good and a gap is created and the bond <
One advantage is to provide a semiconductor device with good moisture resistance.
即ち、本発明は、リードフレームの素子載置部に半導体
素子が固着され２１’態でモールド樹脂によりパッケー
ジングされてなる半導体装置において、前記リードフレ
ームの吊りビンおよびインナーリードにそれぞれ穴が形
成されていることを特徴とするものであり、この穴にモ
ールド樹脂が入り込んで固化することによってモールド
樹脂とリードフレームとの密着性が向上（７、外部から
パッケージ内へ水分が浸入し難くなっている。That is, the present invention provides a semiconductor device in which a semiconductor element is fixed to an element mounting portion of a lead frame and packaged in a 21' state with a molded resin, in which holes are formed in each of a hanging bottle and an inner lead of the lead frame. The mold resin enters these holes and solidifies, improving the adhesion between the mold resin and the lead frame. .
以下、図面を参照して本発明の一実施例を詳細に説明す
る。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第２図（ロ）） 、 （ｂ） 、 （ｃ）に示す半導体
装置２ｏは、第１図（ａ） ｅ （ｂ） 、（ｃ）を参
照【１．て前述した従来の半導体装ｕ１に比べて、吊り
ビン２ノに１個以上（本例では２１β１）のパンチ穴２
２が形成されてイル点、各インナーリード２３のストッ
パ部２３′にそれぞれパンチ穴２４が形成されている点
、吊りビン２ノが蛇行状に湾曲形成されている点が異な
り、その他は同じであるので第１図中と同一部分には同
一符号を付してその説明を省略する。The semiconductor device 2o shown in FIGS. 2(b), (b), and (c) is shown in FIGS. 1(a), (b), and (c) [1. Compared to the conventional semiconductor device u1 described above, one or more punch holes 2 (21β1 in this example) are provided in the hanging bottle 2.
2 is formed, a punch hole 24 is formed in the stopper part 23' of each inner lead 23, and the hanging bottle 2 is curved in a serpentine shape, but the other points are the same. Therefore, the same parts as in FIG. 1 are denoted by the same reference numerals, and the explanation thereof will be omitted.
上記構成の半導体装置によれば、吊りビン２１およびイ
ンナーリード２３にそれぞれパンチ穴２２．２４？ｉ−
設けているので、第２図（ｄ） 、 （ｅ）に示すよう
にモールド樹脂６は上記パンチ穴２２．２４に入り込ん
だ状態で固化（−ている。【７たがって、モールド樹脂
６と吊りビン２．１との間およびモールド樹脂６とイン
ナーリード２３との間は、密着性が良く保たれて隙１１
１１がケじ離〈なり、外部から上記隙間を通ってパッケ
ージ内に水分が浸入することは殆んと生じない。According to the semiconductor device having the above configuration, the hanging bottle 21 and the inner lead 23 have punch holes 22 and 24, respectively. i-
As shown in FIGS. 2(d) and 2(e), the mold resin 6 is solidified (-) in the punched hole 22.24. Good adhesion is maintained between the bottle 2.1 and between the molded resin 6 and the inner lead 23, leaving a gap 11.
11 is separated, and moisture hardly enters into the package from the outside through the gap.
また、吊りビン２）は蛇行しており、パッケージ内の吊
りビン２１の寸法が長くなっているので、吊りビン２ノ
に沿って外部からパッケージ内の夾深くまで水分が浸入
することはんんど生じない。なお、インナーリード２３
もその内光端部が一般に蛇行しているので、やはりそｒ
ｌぞれに沿って水分が浸入することは殆んど生じない。In addition, since the hanging bottle 2) has a meandering shape, and the length of the hanging bottle 21 inside the package is long, moisture cannot penetrate from the outside along the hanging bottle 2) to deep inside the package. It won't happen. In addition, inner lead 23
Also, since the inner light end is generally meandering,
There is almost no intrusion of moisture along each line.
次に、上記構成による半導体装ｊｄ ２ ｏの半田ジャ
ブ漬は後における外観該層、耐湿性試験の結果を下表（
５）、■）に示す。なお、対比のために従来の半導体装
置１の同様の試駁結朱も示している。ここで、半田ジャ
ブ漬けの条件は３６０℃、１０秒間であり、本発明装置
は試験サンプル数２４個のうちパッケージの外ノド変化
としてふくワ、破裂、クラックが生じた不良数は皆無で
あり、全品とも正常であった。また、耐湿性試かの条件
は１２７°Ｃ１湿度１００％、圧力２．５ａｔｍであり
、本発明装置は試験サンプル数２４イ１〜のうち試駄町
間が２０時曲、４０時間、６０時間、８０時ＩＭＪの後
で生じた不良１ｉＪ、は皆無であり、全品とも正猟であ
った。Next, after soldering the semiconductor device JD2O with the above configuration, the appearance of the layer and the results of the moisture resistance test are shown in the table below (
5) and ■). For comparison, a similar test result of the conventional semiconductor device 1 is also shown in red. Here, the solder jab dipping conditions were 360°C and 10 seconds, and the device of the present invention had no defects in which bubbles, ruptures, or cracks occurred as a result of changes in the outer edges of the package out of 24 test samples. All items were normal. In addition, the conditions for the moisture resistance test were 127°C, 100% humidity, and 2.5 atm, and the device of the present invention was tested for 20 hours, 40 hours, and 60 hours. There were no defective 1iJs that occurred after 80:00 IMJ, and all products were in good condition.
表（Ａ）外紐試鹸結呆（サンプル数２４ （１，！ｉｔ
）表（Ｂ）耐湿性試験（サンプル数２４個）（半田ジ
ャブ漬は条件＝２６０’０．１０秒間）（ブレラシャフ
ラカーテスト条件：
１２７°Ｃ１漫度１００％、２５気圧）なお、前記吊り
ビン２ノの蛇行形状は、上記力ゝ
実施例のようなくの字状にμＦ１らず、Ｓ字状とがジグ
ザグ状であってもよい。また、本発明は上記実施例の７
ラツトタイプ以外にもデュアルインラインタイプなどの
パッケージを有する半導体装置にも適用可能である〇
また、本発明による前述し７た効果は、少なくとも吊り
ビンおよびインナーリードにパンチ穴を設けておくこと
によって得られるものであり、さらに前述したように吊
りビンを蛇行状に形成しておくことによって一層効果的
である。Table (A) Outer string test saponification (number of samples 24 (1,!it
) Table (B) Moisture resistance test (24 samples) (Solder jab soaking conditions = 260' for 0.10 seconds) (Brella Shafracar test conditions: 127°C 100%, 25 atm) In addition, the above The meandering shape of the hanging bottle 2 may not be in the dogleg shape μF1 as in the above embodiment, but may be in a zigzag shape with the S shape. In addition, the present invention is based on the seventh embodiment described above.
In addition to the rat type, it is also applicable to semiconductor devices having packages such as a dual in-line type. Also, the above-mentioned seven effects of the present invention can be obtained by providing punch holes in at least the hanging bottle and the inner lead. This is even more effective if the hanging bottle is formed in a meandering shape as described above.
」：述したように木兄り）１の半（体装汎によれば、プ
ラスチックパッケージ内にｌＡ部から水分が浸入しＫｌ
： ＜ 、パッケージ例形の変形が住じ虹く、モールド
樹脂と吊りビンお・よひインナーリードとの密着性がル
くて淑！間が生じ虹＜、ｉｌｌ＋＋湿性がｐいなどの効
果が荀られる。”: As mentioned above, according to Kisouhan, moisture entered the plastic package from the 1A area and the 1/2
： < , The shape of the package is very flexible, and the adhesion between the mold resin and the inner lead of the hanging bottle is very good! There is a pause, and effects such as rainbow<, ill++ and wetness are observed.
第１図は従沫の半塔体装誦を示すもので、同図（Ｂ）は
上面図、同図（ｂ）はｆｉｉＪ図（ａ）のＢ −Ｂ’ｌ
ｊに沿う断面の拡大図、同図（ｃ）はリードフト−ム部
を月シリ出してその一部を省略して示す平面図、第２図
は本発明に係る半導体装置の一実施シ１１を示すもので
、同図（ａ） ｆ町上平面、同図（ｂ）は同図（ａ）の
Ｈ−Ｂ／塾に沿う断面の拡大図、同図（ｅ）はリードフ
１／−ム％５を取り出してその−に１＜を省略して示す
平面図、同図（ｄ）、、 、（ｅ）はそ刊、ぞハ、同図
（ｅ）のパンチ穴Ｉ／３にモールド樹脂が入り込んで密
着している様子を拡大して示す平面図である。
２・・・半導体ぺ１／ツト、３・・・素子載置部、２゜
吊りビン、２２．２４・・・パンチ穴、２３・・・イン
ナーリード。Figure 1 shows the half-tower structure of the Congregation, where (B) is a top view, and (b) is B-B'l of fiiJ diagram (a).
FIG. 2 is an enlarged view of the cross section along the direction j, FIG. The figure (a) is a plan view of f-cho, the figure (b) is an enlarged view of the cross section along H-B/Juku in figure (a), and the figure (e) is the lead f 1/-m%. 5 is taken out and 1< is omitted from its -, the same figure (d), , , (e) is the same publication. FIG. 7 is a plan view showing an enlarged view of the state in which the parts are inserted and in close contact with each other. 2...Semiconductor plate 1/tsut, 3...Element mounting portion, 2° hanging bottle, 22.24...Punched hole, 23...Inner lead.
Claims (2)
された状態でモールド樹脂によりパッケージングされて
なる半導体装置において、前記リードフレームの吊りピ
ンおよびインナーリードにそれぞれ穴が形成されている
ことを特徴とする半導体装置。(1) In a semiconductor device that is packaged with molded resin with an outer conductor element fixed to the element mounting portion of a lead frame, holes are formed in each of the suspension pins and inner leads of the lead frame. A semiconductor device characterized by:
徴とする特許 載の半導体装置。(2) The semiconductor device described in the patent is characterized in that the hanging pin is formed in a meandering shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58174801A JPS6066454A (en) | 1983-09-21 | 1983-09-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58174801A JPS6066454A (en) | 1983-09-21 | 1983-09-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6066454A true JPS6066454A (en) | 1985-04-16 |
Family
ID=15984898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58174801A Pending JPS6066454A (en) | 1983-09-21 | 1983-09-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6066454A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003019677A3 (en) * | 2001-08-21 | 2004-04-29 | Osram Opto Semiconductors Gmbh | Conductor frame and housing for a radiation-emitting component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5614053B2 (en) * | 1974-07-19 | 1981-04-02 |
-
1983
- 1983-09-21 JP JP58174801A patent/JPS6066454A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5614053B2 (en) * | 1974-07-19 | 1981-04-02 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003019677A3 (en) * | 2001-08-21 | 2004-04-29 | Osram Opto Semiconductors Gmbh | Conductor frame and housing for a radiation-emitting component |
| US7193299B2 (en) | 2001-08-21 | 2007-03-20 | Osram Opto Semiconductors Gmbh | Conductor frame and housing for a radiation-emitting component, radiation-emitting component and display and/or illumination system using radiation-emitting components |
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