JP2000252404A - Semiconductor package and its manufacture - Google Patents
Semiconductor package and its manufactureInfo
- Publication number
- JP2000252404A JP2000252404A JP4886099A JP4886099A JP2000252404A JP 2000252404 A JP2000252404 A JP 2000252404A JP 4886099 A JP4886099 A JP 4886099A JP 4886099 A JP4886099 A JP 4886099A JP 2000252404 A JP2000252404 A JP 2000252404A
- Authority
- JP
- Japan
- Prior art keywords
- silicon die
- lead frame
- resin film
- semiconductor package
- insulating resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＱＦＰ（Ｑｕａｄ
Ｆｌａｔ Ｐａｃｋａｇｅ）等の半導体パッケージ及
びその製造方法に関する。The present invention relates to a QFP (Quad).
The present invention relates to a semiconductor package such as a flat package and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、この種の分野の技術に関しては、
例えば図４に示すようなものがあった。2. Description of the Related Art Conventionally, with regard to technologies in this kind of field,
For example, there was one as shown in FIG.
【０００３】図４は、従来のＱＰＦタイプの半導体パッ
ケージの構造を示す断面図である。この半導体パッケー
ジは、四方向全ての側面から外部端子が導出された表面
実装型パッケージであり、Ｃｕ（銅）等のダイパッド１
０１上にシリコンダイ１０２が接着剤１０３によりダイ
ボンディングされている。さらに、シリコンダイ１０２
の各Ａｌ（アルミニューム）電極が、外部端子となるリ
ードフレーム群１０４にＡｕ（金）線１０５によってそ
れぞれワイヤボンディングされている。FIG. 4 is a sectional view showing a structure of a conventional QPF type semiconductor package. This semiconductor package is a surface mount type package in which external terminals are led out from all side surfaces in four directions, and has a die pad 1 made of Cu (copper) or the like.
A silicon die 102 is die-bonded on the substrate 01 with an adhesive 103. Further, the silicon die 102
Each of the Al (aluminum) electrodes is wire-bonded to a lead frame group 104 serving as an external terminal by an Au (gold) wire 105.
【０００４】そして、上記のダイパッド１０１上のシリ
コンダイ１０２、及びＡｕ線１０５を介して接続された
リードフレーム群１０４がエポキシ等のモールドレジン
１０６によって封止されている。Then, the silicon die 102 on the die pad 101 and the lead frame group 104 connected via the Au wire 105 are sealed with a mold resin 106 such as epoxy.
【０００５】このような半導体パッケージは、良品・不
良品の各種試験を行った上で、出荷されるようになって
おり、この試験の一つに耐リフロー試験と呼ばれている
ものがある。この耐リフロー試験は、被試験品である半
導体パッケージを湿度７０％且つ温度３０℃の雰囲気中
に２００時間程度さらすことにより、当該半導体パッケ
ージの破損や亀裂等の不具合の有無を調べるものであ
る。[0005] Such a semiconductor package is shipped after being subjected to various tests of good and defective products, and one of these tests is called a reflow resistance test. In this reflow resistance test, the semiconductor package to be tested is exposed to an atmosphere at a humidity of 70% and a temperature of 30 ° C. for about 200 hours to check whether or not the semiconductor package has a defect such as breakage or crack.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体パッケージでは、ダイパッド１０１の材料と
してＣｕ等の酸化する材質を使用している場合は、当該
ダイパッド１０１とモールドレジン１０６との密着性が
良くないため、上記耐リフロー試験時に、モールドレジ
ン１０６とダイパッド１０１との剥離が発生し、その結
果、破損等が生じて不良品となることが多かった。However, in the above-mentioned conventional semiconductor package, when a material that oxidizes such as Cu is used as the material of the die pad 101, the adhesion between the die pad 101 and the mold resin 106 is good. Therefore, during the reflow resistance test, the mold resin 106 and the die pad 101 peeled off, and as a result, damage and the like often occurred, resulting in a defective product.
【０００７】本発明は、上述の如き従来の問題点を解決
するためになされたもので、その目的は、剥離等の不具
合がなく耐リフロー試験において良好な試験結果を得る
ことができ、製品の生産性を向上させることができる半
導体パッケージを提供することである。また、その他の
目的は、前記半導体パッケージを容易且つ的確に製造す
ることができる半導体パッケージの製造方法を提供する
ことである。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. An object of the present invention is to obtain a good test result in a reflow resistance test without defects such as peeling, and An object of the present invention is to provide a semiconductor package capable of improving productivity. Another object of the present invention is to provide a method of manufacturing a semiconductor package that can easily and accurately manufacture the semiconductor package.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、請求項１記載の発明である半導体パッケージの特徴
は、複数の貫通穴を有する絶縁樹脂フィルムと、前記絶
縁樹脂フィルムの主面上に固定されたシリコンダイと、
前記絶縁樹脂フィルムの端部に固定された外部端子用の
リードフレームと、前記シリコンダイの電極と前記リー
ドフレームを電気的に接続するためのボンディングワイ
ヤと、前記絶縁樹脂フィルム、前記シリコンダイ、及び
前記ボンディングワイヤの全体を封止するモールドレジ
ンとを備えたことにある。In order to achieve the above object, a semiconductor package according to the present invention is characterized in that an insulating resin film having a plurality of through holes and a main surface of the insulating resin film are provided. A silicon die fixed to the
A lead frame for external terminals fixed to an end of the insulating resin film, a bonding wire for electrically connecting an electrode of the silicon die to the lead frame, the insulating resin film, the silicon die, and And a mold resin for sealing the entirety of the bonding wire.
【０００９】この請求項１記載の発明によれば、絶縁樹
脂フィルムとモールドレジンとの接着面積が増大し、絶
縁樹脂フィルムとモールドレジンの密着性が良好となる
ため、耐リフロー試験時に両部材において剥離が発生す
るのを防止する。According to the first aspect of the present invention, the adhesion area between the insulating resin film and the mold resin is increased, and the adhesion between the insulating resin film and the mold resin is improved. Prevents peeling.
【００１０】請求項２記載の発明である半導体パッケー
ジの特徴は、請求項１記載の発明である半導体パッケー
ジにおいて、前記貫通穴が、前記絶縁樹脂フィルムにお
ける前記シリコンダイを搭載する領域と前記リードフレ
ームが固定される領域との間の領域に形成されたことに
ある。The semiconductor package according to the second aspect of the present invention is characterized in that, in the semiconductor package according to the first aspect of the present invention, the through hole has a region in which the silicon die is mounted in the insulating resin film and the lead frame. Is formed in a region between the region to be fixed.
【００１１】この請求項２記載の発明によれば、絶縁樹
脂フィルムとモールドレジンとの接着面積が一層増大
し、絶縁樹脂フィルムとモールドレジンの密着性がより
良好となるため、耐リフロー試験時に両部材において剥
離が発生するのを確実に防止する。According to the second aspect of the present invention, the adhesion area between the insulating resin film and the mold resin is further increased, and the adhesion between the insulating resin film and the mold resin is further improved. It is possible to reliably prevent separation from occurring in the member.
【００１２】請求項３の発明である半導体パッケージの
製造方法の特徴は、複数の貫通穴を有する絶縁樹脂フィ
ルムの端部にリードフレームを固定した部材を用意し、
前記絶縁樹脂フィルムの主面上にシリコンダイを固定し
て、該シリコンダイの電極と前記リードフレームとをボ
ンディングワイヤで接合し、前記絶縁樹脂フィルム、前
記シリコンダイ、及び前記ボンディングワイヤの全体を
モールドレジンで封止し、前記モールドレジンから外部
へ導出された前記リードフレームの端部を外部端子用に
加工したことにある。A feature of the method for manufacturing a semiconductor package according to the third aspect of the present invention is that a member in which a lead frame is fixed to an end of an insulating resin film having a plurality of through holes is prepared.
A silicon die is fixed on the main surface of the insulating resin film, and the electrode of the silicon die and the lead frame are joined with a bonding wire, and the entire insulating resin film, the silicon die, and the bonding wire are molded. The present invention is characterized in that the lead frame is sealed with a resin, and the end of the lead frame led out from the mold resin is processed for an external terminal.
【００１３】この請求項３記載の発明によれば、請求項
１記載の半導体パッケージが容易且つ的確に製造され
る。すなわち、モールド時に貫通穴にもモールドレジン
が侵入するため、絶縁樹脂フィルムとモールドレジンと
の接着面積が増大し、絶縁樹脂フィルムとモールドレジ
ンの密着性が良好となるため、耐リフロー試験時に両部
材において剥離が発生するのを確実に防止する。According to the third aspect of the present invention, the semiconductor package according to the first aspect is easily and accurately manufactured. That is, since the mold resin also enters the through holes during molding, the adhesion area between the insulating resin film and the mold resin increases, and the adhesion between the insulating resin film and the mold resin becomes good. , The occurrence of peeling is surely prevented.
【００１４】[0014]
【発明の実施の形態】以下、本発明に係わる半導体パッ
ケージ及びその製造方法の実施形態について説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor package and a method of manufacturing the same according to the present invention will be described.
【００１５】図１は、本発明の実施形態に係る半導体パ
ッケージの断面構造図であり、図２は、その要部の平面
構造図である。FIG. 1 is a sectional structural view of a semiconductor package according to an embodiment of the present invention, and FIG. 2 is a plan structural view of a main part thereof.
【００１６】この半導体パッケージは、四方向全ての側
面から外部端子が導出された表面実装型パッケージであ
り、従来装置のダイパッドに代用されるポリイミドテー
プ１１が設けられている。This semiconductor package is a surface-mount type package in which external terminals are led out from all side surfaces in all four directions, and is provided with a polyimide tape 11 which can be used as a die pad of a conventional device.
【００１７】ポリイミドテープ１１は、例えば□２０ｍ
ｍのサイズで、中央部にシリコンダイ搭載用領域が設け
られ、さらに四方の端部にはそれぞれ外部端子用のリー
ドフレーム群１４が接着剤１５によって固定されてい
る。The polyimide tape 11 is, for example, □ 20 m
A silicon die mounting area is provided at the center in a size of m, and lead frame groups 14 for external terminals are fixed to the four end parts by an adhesive 15, respectively.
【００１８】そして、ポリイミドテープ１１におけるシ
リコンダイ搭載用領域とリードフレーム群１４との間の
領域には、当該ポリイミドテープ１１とモールドレジン
１７との密着を良好にするために複数の貫通穴１１ａ，
１１ｂ，１１ｃが開孔されている。この貫通穴１１ａ，
１１ｂ，１１ｃは、例えば直径が３ｍｍの円形であり、
図２に示すように一定のピッチ（例えば４ｍｍ）で、シ
リコンダイ搭載領域を例えば三重に囲むような形で配さ
れている。In the area between the silicon die mounting area and the lead frame group 14 in the polyimide tape 11, a plurality of through holes 11 a,
11b and 11c are opened. This through hole 11a,
11b and 11c are circular with a diameter of 3 mm, for example,
As shown in FIG. 2, they are arranged at a constant pitch (for example, 4 mm) so as to surround the silicon die mounting area, for example, three times.
【００１９】かかる構造のポリイミドテープ１１のシリ
コンダイ搭載用領域には、例えば□１０ｍｍのサイズの
シリコンダイ１２がＡｇ（銀）ペースト等の接着剤１３
によりダイボンディングされ、さらにシリコンダイ１２
の各Ａｌ（アルミニューム）電極が、リードフレーム群
１４にＡｕ（金）線１６によってそれぞれワイヤボンデ
ィングされている。On the silicon die mounting area of the polyimide tape 11 having such a structure, for example, a silicon die 12 having a size of 10 mm is bonded with an adhesive 13 such as an Ag (silver) paste.
Die bonding, and furthermore, the silicon die 12
Are respectively wire-bonded to the lead frame group 14 by Au (gold) wires 16.
【００２０】そして、上記ポリイミドテープ１１、シリ
コンダイ１２、及びＡｕ線１６を含む接続構成部全体が
エポキシ等のモールドレジン１７によって封止され、該
モールドレジン１７から外部へ導出された前記リードフ
レーム群１４の端部が折り曲げられて外部端子を成形し
ている。The entire connection structure including the polyimide tape 11, the silicon die 12, and the Au wire 16 is sealed with a mold resin 17 such as epoxy, and the lead frame group led out from the mold resin 17 to the outside. The end of 14 is bent to form an external terminal.
【００２１】次に、図１に示した構造の半導体パッケー
ジの製造工程を図３（ａ）〜（ｄ）の工程図を参照して
説明する。Next, a manufacturing process of the semiconductor package having the structure shown in FIG. 1 will be described with reference to FIGS. 3 (a) to 3 (d).
【００２２】まず、図３（ａ）に示すように、パンチン
グ等で上記貫通穴１１ａ，１１ｂ，１１ｃが開孔された
ポリイミドテープ１１の端部に、リードフレーム群１４
ａを接着剤１５で固定した部材を用意する。First, as shown in FIG. 3A, a lead frame group 14 is attached to the end of the polyimide tape 11 in which the through holes 11a, 11b, 11c are opened by punching or the like.
A member having a fixed with an adhesive 15 is prepared.
【００２３】次の工程では、図３（ｂ）に示すように、
前記ポリイミドテープ１１のシリコンダイ搭載用領域上
にシリコンダイ１２を接着剤１３を介してダイボンディ
ングし、該シリコンダイ１２の各Ａｌ電極とリードフレ
ーム群１４ａとを、それぞれボンディングワイヤ１６を
用いてネイルヘッドボンディング法で接合する。In the next step, as shown in FIG.
A silicon die 12 is die-bonded on the silicon die mounting area of the polyimide tape 11 via an adhesive 13, and each Al electrode of the silicon die 12 and a lead frame group 14 a are respectively nailed using bonding wires 16. Joining by head bonding method.
【００２４】続く工程では、図３（ｃ）に示すように、
ポリイミドテープ１１、シリコンダイ１２、及びＡｕ線
１６を含む接続構成部全体を、エポキシ等のモールドレ
ジン１７を用いてトランスファーモールド法によって封
止する。すなわち、熱硬化性樹脂であるモールドレジン
を予め加熱室内で可塑化させておくと共に、専用成形機
に取り付けられた金型キャビティに、前工程でリードフ
レーム群１４ａがワイヤボンディングされたシリコンダ
イ１２を装填し、型締めを行う。そして、既に成形温度
（１７０℃）に加熱された前記金型キャビティに、可塑
化されたモールドレジンを圧入してモールドレジン１７
として硬化させる。このとき、前記ポリイミドテープ１
１の貫通穴１１ａ，１１ｂ，１１ｃにもモールドレジン
１７が侵入するため、ポリイミドテープ１１とモールド
レジン１７との接着面積が増大し、両部材の密着性が従
来よりも一段と向上する。In the subsequent step, as shown in FIG.
The entire connection structure including the polyimide tape 11, the silicon die 12, and the Au wire 16 is sealed by a transfer molding method using a mold resin 17 such as epoxy. That is, the mold resin, which is a thermosetting resin, is plasticized in a heating chamber in advance, and the silicon die 12 to which the lead frame group 14a has been wire-bonded in the previous process is placed in the mold cavity attached to the special molding machine. Load and close the mold. Then, the plasticized mold resin is press-fitted into the mold cavity already heated to the molding temperature (170 ° C.) and the mold resin 17 is pressed.
To be cured. At this time, the polyimide tape 1
Since the mold resin 17 also enters the one through hole 11a, 11b, 11c, the adhesion area between the polyimide tape 11 and the mold resin 17 is increased, and the adhesion between the two members is further improved as compared with the related art.
【００２５】そして、その後の工程では、モールドレジ
ン１７から外部へ導出された前記リードフレーム群１４
ａにメッキ処理を施した後、図３（ｄ）に示すようにリ
ードカット及びベンド処理を行えば、図１に示した構造
の半導体パッケージが完成する。In a subsequent step, the lead frame group 14 led out of the mold resin 17 to the outside is used.
After performing a plating process on a, if lead cutting and bending processes are performed as shown in FIG. 3D, the semiconductor package having the structure shown in FIG. 1 is completed.
【００２６】このようにして製造された図１の構造の半
導体パッケージは、貫通穴１１ａ，１１ｂ，１１ｃによ
って、ポリイミドテープ１１とモールドレジン１７の密
着性が従来よりも一段と向上するため、耐リフロー試験
時に両部材において剥離が発生するのを防止することが
できる。これにより、耐リフロー試験において良好な試
験結果を得ることでき、製品の生産性が向上する。In the semiconductor package having the structure shown in FIG. 1 manufactured as described above, the adhesion between the polyimide tape 11 and the mold resin 17 is further improved by the through holes 11a, 11b and 11c as compared with the conventional semiconductor package. Occasionally, peeling of both members can be prevented. Thereby, good test results can be obtained in the reflow resistance test, and the productivity of the product is improved.
【００２７】なお、本発明は図示の実施形態に限定され
ず、種々の変形が可能である。その変形例として、例え
ば、上記実施形態ではポリイミドテープ１１に開孔する
貫通穴１１ａ，１１ｂ，１１ｃを円形としたが、これに
限定されるものでなく本発明の趣旨に沿ったものである
ならば正方形、三角形等如何なる形状であっても良い。
また、貫通穴の数及びピッチも、ポリイミドテープ１１
の強度及びモールドレジン１７との密着性等を考慮し
て、適切なものにするのが望ましい。The present invention is not limited to the illustrated embodiment, and various modifications are possible. As a modified example, for example, in the above-described embodiment, the through holes 11a, 11b, and 11c formed in the polyimide tape 11 are circular. However, the present invention is not limited to this, and is in accordance with the spirit of the present invention. Any shape such as a square or a triangle may be used.
In addition, the number and pitch of the through holes are also different from those of the polyimide tape 11.
In consideration of the strength of the resin and the adhesiveness to the mold resin 17, it is desirable to make it appropriate.
【００２８】[0028]
【発明の効果】以上詳細に説明したように、請求項１記
載の発明である半導体パッケージによれば、複数の貫通
穴を有する絶縁樹脂フィルムを設け、この絶縁樹脂フィ
ルムの主面上にシリコンダイを固定すると共に、絶縁樹
脂フィルムの端部に外部端子用のリードフレームを固定
し、前記絶縁樹脂フィルム、前記シリコンダイ、及びボ
ンディングワイヤの全体をモールドレジンで封止したの
で、貫通穴によって、絶縁樹脂フィルムとモールドレジ
ンの密着性が良好となり、耐リフロー試験時に両部材に
おいて剥離が発生するのを防止することができる。これ
により、耐リフロー試験において良好な試験結果を得る
ことでき、製品の生産性を向上させることが可能にな
る。As described above in detail, according to the semiconductor package of the first aspect, an insulating resin film having a plurality of through holes is provided, and a silicon die is provided on a main surface of the insulating resin film. And the lead frame for external terminals was fixed to the end of the insulating resin film, and the entire insulating resin film, the silicon die, and the bonding wires were sealed with a mold resin. Adhesion between the resin film and the mold resin is improved, and peeling can be prevented from occurring in both members during a reflow resistance test. Thereby, good test results can be obtained in the reflow resistance test, and the productivity of the product can be improved.
【００２９】請求項２記載の発明である半導体パッケー
ジによれば、請求項１記載の発明である半導体パッケー
ジにおいて、前記貫通穴が、前記絶縁樹脂フィルムにお
ける前記シリコンダイを搭載する領域と前記リードフレ
ームが固定される領域との間の領域に形成されたので、
絶縁樹脂フィルムとモールドレジンの密着性がより一層
良好となり、耐リフロー試験時に両部材において剥離が
発生するのを確実に防止することができる。According to the semiconductor package according to the second aspect of the present invention, in the semiconductor package according to the first aspect of the present invention, the through-hole is formed in a region of the insulating resin film on which the silicon die is mounted and the lead frame. Is formed in the area between the fixed area and
Adhesion between the insulating resin film and the mold resin is further improved, and peeling can be reliably prevented from occurring in both members during a reflow resistance test.
【００３０】請求項３の発明である半導体パッケージの
製造方法によれば、例えば請求項１記載の半導体パッケ
ージを簡易且つ的確に製造することができる。すなわ
ち、この製造方法で製造された半導体パッケージは、貫
通穴によって、絶縁樹脂フィルムとモールドレジンの密
着性が良好となるので、耐リフロー試験時に両部材にお
いて剥離が発生するのを防止することができる。これに
より、耐リフロー試験において良好な試験結果を得るこ
とでき、製品の生産性を向上させることが可能になる。According to the method for manufacturing a semiconductor package according to the third aspect of the present invention, for example, the semiconductor package according to the first aspect can be manufactured simply and accurately. That is, the semiconductor package manufactured by this manufacturing method has good adhesion between the insulating resin film and the mold resin due to the through-holes, so that it is possible to prevent separation from occurring in both members during the reflow resistance test. . Thereby, good test results can be obtained in the reflow resistance test, and the productivity of the product can be improved.
【図１】本発明の実施形態に係る半導体パッケージの断
面構造図である。FIG. 1 is a sectional structural view of a semiconductor package according to an embodiment of the present invention.
【図２】図１に示した半導体パッケージの要部の平面構
造図である。FIG. 2 is a plan structural view of a main part of the semiconductor package shown in FIG. 1;
【図３】図１に示した構造の半導体パッケージの製造工
程を示す工程図である。FIG. 3 is a process chart showing a manufacturing process of the semiconductor package having the structure shown in FIG. 1;
【図４】従来のＱＰＦタイプの半導体パッケージの構造
を示す断面図である。FIG. 4 is a cross-sectional view showing the structure of a conventional QPF type semiconductor package.
１１ ポリイミドテープ １１ａ，１１ｂ，１１ｃ 貫通穴 １２ シリコンダイ １３ 接着剤 １４ リードフレーム １５ 接着剤 １６ Ａｕ（金）線 １７ モールドレジン DESCRIPTION OF SYMBOLS 11 Polyimide tape 11a, 11b, 11c Through-hole 12 Silicon die 13 Adhesive 14 Lead frame 15 Adhesive 16 Au (gold) wire 17 Mold resin
Claims (3)
と、 前記絶縁樹脂フィルムの主面上に固定されたシリコンダ
イと、 前記絶縁樹脂フィルムの端部に固定された外部端子用の
リードフレームと、 前記シリコンダイの電極と前記リードフレームを電気的
に接続するためのボンディングワイヤと、 前記絶縁樹脂フィルム、前記シリコンダイ、及び前記ボ
ンディングワイヤの全体を封止するモールドレジンとを
備えた事を特徴とする半導体パッケージ。1. An insulating resin film having a plurality of through holes, a silicon die fixed on a main surface of the insulating resin film, and a lead frame for an external terminal fixed to an end of the insulating resin film. A bonding wire for electrically connecting an electrode of the silicon die to the lead frame; and a mold resin for sealing the entirety of the insulating resin film, the silicon die, and the bonding wire. Semiconductor package.
おける前記シリコンダイを搭載する領域と前記リードフ
レームが固定される領域との間の領域に形成されたこと
を特徴とする請求項１記載の半導体パッケージ。2. The insulating resin film according to claim 1, wherein the through hole is formed in a region between the region where the silicon die is mounted and a region where the lead frame is fixed in the insulating resin film. Semiconductor package.
の端部にリードフレームを固定した部材を用意し、 前記絶縁樹脂フィルムの主面上にシリコンダイを固定し
て、該シリコンダイの電極と前記リードフレームとをボ
ンディングワイヤで接合し、 前記絶縁樹脂フィルム、前記シリコンダイ、及び前記ボ
ンディングワイヤの全体をモールドレジンで封止し、 前記モールドレジンから外部へ導出された前記リードフ
レームの端部を外部端子用に加工したことを特徴とする
半導体パッケージの製造方法。3. A member in which a lead frame is fixed to an end portion of an insulating resin film having a plurality of through holes, a silicon die is fixed on a main surface of the insulating resin film, and an electrode of the silicon die is formed. Bonding the lead frame with a bonding wire, sealing the whole of the insulating resin film, the silicon die, and the bonding wire with a mold resin, and removing an end of the lead frame led out from the mold resin to the outside. A method for manufacturing a semiconductor package, wherein the semiconductor package is processed for an external terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4886099A JP2000252404A (en) | 1999-02-25 | 1999-02-25 | Semiconductor package and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4886099A JP2000252404A (en) | 1999-02-25 | 1999-02-25 | Semiconductor package and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000252404A true JP2000252404A (en) | 2000-09-14 |
Family
ID=12815040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4886099A Withdrawn JP2000252404A (en) | 1999-02-25 | 1999-02-25 | Semiconductor package and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000252404A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661081B2 (en) | 2000-10-20 | 2003-12-09 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| KR100426330B1 (en) * | 2001-07-16 | 2004-04-08 | 삼성전자주식회사 | Ultra-Thin Semiconductor Package Device Using a Support Tape |
| CN107994005A (en) * | 2017-12-27 | 2018-05-04 | 天水华天科技股份有限公司 | A kind of high reliability array locking-type lead frame and its application in an enclosure |
-
1999
- 1999-02-25 JP JP4886099A patent/JP2000252404A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6661081B2 (en) | 2000-10-20 | 2003-12-09 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| US6962836B2 (en) | 2000-10-20 | 2005-11-08 | Renesas Technology Corp. | Method of manufacturing a semiconductor device having leads stabilized during die mounting |
| KR100426330B1 (en) * | 2001-07-16 | 2004-04-08 | 삼성전자주식회사 | Ultra-Thin Semiconductor Package Device Using a Support Tape |
| CN107994005A (en) * | 2017-12-27 | 2018-05-04 | 天水华天科技股份有限公司 | A kind of high reliability array locking-type lead frame and its application in an enclosure |
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| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
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