JPS6066451A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPS6066451A JPS6066451A JP17501083A JP17501083A JPS6066451A JP S6066451 A JPS6066451 A JP S6066451A JP 17501083 A JP17501083 A JP 17501083A JP 17501083 A JP17501083 A JP 17501083A JP S6066451 A JPS6066451 A JP S6066451A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- semiconductor package
- package
- electrode hole
- pin holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
本発明は、半導体パッケージであるＰ工Ｐに関する。最
近、工０の多機能化に対応し、多ピンのパッケージが必
要とされてきている。特に、コンビ瓢−夕に代表される
高信頼性を要求される分野には、セラミックパッケージ
によるハーメチック実装は不可欠であり、高密度実装か
らの要求からＰ工Ｐが、この分野で主流になりつつある
。第１図に、Ｐ工Ｐの外観を示す。セラミックペース１
０１内に、多層配線工程により内部配線され、片方をキ
ャビティ内１０２に設けたポンディングパッドと接続さ
れ、又、一方をリード１０５と接続されている。さて、
工０の多機能化に代表されるものとしてマイクロプロセ
ッサ−があるが、機能アップにつれ、８ビツト→１６ビ
ツト→５２ビツトと進み、近い将来、大型コンピュータ
並のマイクロプロセッサ−が開発されることも、充分考
えられている。ところが、マイクロプロセッサ−では、
周辺の工０がパスライン上に接続されるため、従来例で
は実装基板上に、多数のパスラインを設けていた。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a P-product which is a semiconductor package. Recently, a multi-pin package has been required to accommodate the increasing number of functions with zero manufacturing costs. In particular, hermetic mounting using ceramic packages is indispensable in fields that require high reliability, such as combination gourds, and P-type packaging is becoming mainstream in this field due to the demand for high-density packaging. be. Figure 1 shows the external appearance of P-work P. ceramic pace 1
01 is internally wired by a multilayer wiring process, one side is connected to a bonding pad provided in the cavity 102, and the other side is connected to a lead 105. Now,
The microprocessor is a typical example of multi-functionalization of the microprocessor, but as the functionality increases, the number of processors will go from 8 bits to 16 bits to 52 bits, and in the near future, microprocessors comparable to large computers may be developed. , is well thought out. However, in a microprocessor,
Since the peripheral workpieces 0 are connected to the pass lines, in the conventional example, a large number of pass lines were provided on the mounting board.
本発明は、従来のＰｌＰ上に、ビン穴を設けたピギーバ
ックＰＩＰ構造である。第２図が、本発明の外観図であ
る。セラミックベース２０１に設けた、キャビティ２０
２及び、リード２０３に対し、パッケージ上面に、上記
リード２０３と一対一に、対応するピン穴２０４を設け
た。尚ピン穴２０４と対応するリード２０３は、電気的
に接続されている。第３図が、本発明のＰＩＰ上に、他
のＰ工Ｐを、実装した例である３０１が本発明の改良Ｐ
工Ｐ、３０２が、その上に挿着されたＰ工Ｐである。The present invention is a piggyback PIP structure in which a bottle hole is provided on a conventional PIP. FIG. 2 is an external view of the present invention. Cavity 20 provided in ceramic base 201
2 and the leads 203, pin holes 204 corresponding to the leads 203 were provided on the upper surface of the package in one-to-one correspondence with the leads 203. Note that the leads 203 corresponding to the pin holes 204 are electrically connected. FIG. 3 shows an example in which another P is implemented on the PIP of the present invention. 301 is an improved P of the present invention.
The work P, 302 is the work P inserted thereon.
第１図が従来のＰ工Ｐ１第２図が本発明の改良Ｐ工Ｐ、
ｌＡ３［Ｗがその実装例である。
１０５．２０３・・・・・・リード
２０４・・・・・・新たに設けたビン穴以上
出願人 株式会社輝訪精工舎
代理人 弁理士 鰻重 務
第２図 第３ビｌFig. 1 shows the conventional P-work P; Fig. 2 shows the improved P-work P of the present invention;
lA3[W is an example of its implementation. 105.203...Lead 204...Newly created bottle hole Applicant Kiwa Seikosha Co., Ltd. Agent Patent attorney Unagi Shige Figure 2 Building 3
Claims (1)
導体パッケージに於いて、該セラミックペース上に、電
極穴が設けられていること、および、この電極穴に、他
の半導体素子が搭載出来ること、該セラミックベースの
下部に、リードが形成されているＰｌｕｇ−工ｎ−Ｐａ
ｃｋａｇｅ（Ｐ工ｐ）であることを特徴とする半導体パ
ッケージ。In a semiconductor package formed by laminated multilayer wiring on a ceramic paste, an electrode hole is provided on the ceramic paste, and another semiconductor element can be mounted in the electrode hole. Plug-engine n-Pa with leads formed at the bottom of the base
A semiconductor package characterized in that it is a ckage (P-product).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17501083A JPS6066451A (en) | 1983-09-21 | 1983-09-21 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17501083A JPS6066451A (en) | 1983-09-21 | 1983-09-21 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6066451A true JPS6066451A (en) | 1985-04-16 |
Family
ID=15988634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17501083A Pending JPS6066451A (en) | 1983-09-21 | 1983-09-21 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6066451A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7744447B2 (en) | 2005-03-16 | 2010-06-29 | Goei, Co., Ltd. | Abrasive disc |
-
1983
- 1983-09-21 JP JP17501083A patent/JPS6066451A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7744447B2 (en) | 2005-03-16 | 2010-06-29 | Goei, Co., Ltd. | Abrasive disc |
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