JPH0193157A - Plug-in type package - Google Patents

Plug-in type package

Info

Publication number
JPH0193157A
JPH0193157A JP25050487A JP25050487A JPH0193157A JP H0193157 A JPH0193157 A JP H0193157A JP 25050487 A JP25050487 A JP 25050487A JP 25050487 A JP25050487 A JP 25050487A JP H0193157 A JPH0193157 A JP H0193157A
Authority
JP
Japan
Prior art keywords
package
plug
view
cavity
external connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25050487A
Other languages
Japanese (ja)
Inventor
Yoshimi Marui
丸井 義美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25050487A priority Critical patent/JPH0193157A/en
Publication of JPH0193157A publication Critical patent/JPH0193157A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make possible a highly integrated packaging without needing a reduction in the pitch between the wirings of a printed-wiring board and the formation in a multilayer structure of a wiring layer by a method wherein external connecting pins are provided on the surface and rear of a plug-in type ceramic package. CONSTITUTION:External connecting pins 4' are provided on the surface side of a package as well in addition to external connecting pins 4 on the rear side of a conventional package. These pins 4 and 4' are connected to bonding pads 3 in a cavity 5 by wiring patterns in the interior of a ceramic substrate 1. The size of the plug-in type package is the same size as that of the conventional package, but this plug in type package can being capable of housing a semiconductor circuit chip having terminals of a number more than the number of the terminals of a semiconductor circuit chip to be housed in the conventional package.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路のパッケージに関し、特に半
導体集積回路の製造工程においてつ工−ハ処理後にスク
ライブした半導体チップを収容しプリント配線基板に実
装する半導体集積回路のプラグイン型パッケージに関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor integrated circuit, and in particular to a package for accommodating a scribed semiconductor chip after die processing in the manufacturing process of a semiconductor integrated circuit, and for mounting it on a printed wiring board. This invention relates to plug-in packages for semiconductor integrated circuits to be mounted.

〔従来の技術〕[Conventional technology]

従来のプラグインタイブのセラミックパッケージのほと
んどは第3図に示す形状のものである。
Most of the conventional plug-in type ceramic packages have the shape shown in FIG.

、第3図(a)、(b)及び(c)はそれぞれ従来のプ
ラグイン型パッケージの一例を示す上面図、側面図及び
裏面図である。このパッケージはセラミックケース1.
ボンディングパッド3.シールリング2.キャビティ5
.外部接続リードピン4等で構成されている。
, FIGS. 3(a), 3(b), and 3(c) are a top view, a side view, and a back view, respectively, showing an example of a conventional plug-in type package. This package includes ceramic case 1.
Bonding pad 3. Seal ring 2. Cavity 5
.. It is composed of external connection lead pins 4 and the like.

この従来のパッケージのプリント配線基板への実装例の
断面模式図を第4図に示す。
FIG. 4 shows a schematic cross-sectional view of an example of mounting this conventional package on a printed wiring board.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体集積回路装置のパッケージは、回
路機能を複数の半導体集積回路チップに分割して1つの
多ビン用プラグインタイブのセラミックパッケージとし
て構成すると外部接続リードピンの増加によりその形状
がさらに大きくなるので、これをプリント配線基板に実
装するには従来以上にプリント配線基板の配線ピッチの
縮小や、配線層の多層化が必要になること、さらにセラ
ミックパッケージとしてもこれを従来の大きさに留める
には外部接続リードピンのピン径やピンピッチの縮小を
しなければならないと云う欠点がある。
In the conventional semiconductor integrated circuit device package described above, when the circuit function is divided into multiple semiconductor integrated circuit chips and configured as a single multi-bin plug-in type ceramic package, the size becomes even larger due to the increase in the number of external connection lead pins. Therefore, in order to mount this on a printed wiring board, it is necessary to reduce the wiring pitch of the printed wiring board and increase the number of wiring layers more than before, and furthermore, it is necessary to keep this to the conventional size as a ceramic package. The disadvantage of this method is that the pin diameter and pin pitch of external connection lead pins must be reduced.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のプラグイン型パッケージは、半導体チップを搭
載するキャビティと、前記キャビティの周囲に設けられ
た複数のボンディングパッドと、前記ボンディングパッ
ドの周囲に設けられたシールリングとを備えた多層セラ
ミック基板内の両面に、前記ボンディングパッドと各々
前記多層セラミック基板内の配線パターンで接続された
外部接続用リードピンが設けられてなるというものであ
る。
The plug-in package of the present invention includes a multilayer ceramic substrate including a cavity for mounting a semiconductor chip, a plurality of bonding pads provided around the cavity, and a seal ring provided around the bonding pads. External connection lead pins are provided on both surfaces of the multilayer ceramic substrate, each of which is connected to the bonding pad through a wiring pattern within the multilayer ceramic substrate.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)、(b)及び(c)はそれぞれ本発明の第
1の実施例を示す上面図、側面図及び裏面図である。
FIGS. 1(a), (b), and (c) are a top view, a side view, and a back view, respectively, showing a first embodiment of the present invention.

第3図に示した従来例のパラゲージ裏面側の外部接続リ
ードピン4に加えパッケージの表面側にも外部接続リー
ドピン4′が設けてあり、これらの外部接続リードピン
4.4′はセラミック基板1の内部の配線パターン(図
示せず)でキャビティ内のボンディングパッド3に接続
しており、従来のパッケージと同一の大きさでありなが
らより多くの端子数を有する半導体集積回路チップを収
容することができる構造−となっている。
In addition to the external connection lead pins 4 on the back side of the package in the conventional example shown in FIG. 3, external connection lead pins 4' are also provided on the front side of the package. The wiring pattern (not shown) is connected to the bonding pad 3 in the cavity, and the structure is capable of accommodating a semiconductor integrated circuit chip having the same size as a conventional package but having a larger number of terminals. -.

本実施例を用いた半導体装置のプリント配線基板への実
装例の断面模式図を第5図に示す。
FIG. 5 shows a schematic cross-sectional view of an example of mounting a semiconductor device on a printed wiring board using this embodiment.

第2図(a)、(b)及び(c)はそれぞれ本発明の第
2の実施例の上面図、側面図及び裏面図である。
FIGS. 2(a), (b), and (c) are a top view, a side view, and a back view, respectively, of a second embodiment of the present invention.

外部接続リードビンをキャビティのある表面側に引出し
たものを2個裏面で貼合せた形状を有し、半導体チップ
を2個実装できる特色がある。
It has a shape in which two external connection lead bins are drawn out on the front side with a cavity and are bonded together on the back side, and has the feature of being able to mount two semiconductor chips.

パッケージ表面側の外部接続リードビン4′、裏面側の
外部接続リードピン4″が設けてあり、これらの外部接
続リードピン4′、4″はセラミック基板1′の内部配
線パターンでキャビティ内のボンディングパッド3.3
′にそれぞれ接続しておりさらにセラミック基板の内部
配線パターンで半導体チップ間の相互接続を行うように
してもよい。従来のパッケージと同一の大きさでありな
がらより多くの端子数を有する半導体集積回路チップを
収容することができる構造を実現できる。
An external connection lead pin 4' on the front side of the package and an external connection lead pin 4'' on the back side are provided, and these external connection lead pins 4', 4'' are connected to bonding pads 3. 3
', and the semiconductor chips may be interconnected by an internal wiring pattern of the ceramic substrate. It is possible to realize a structure that can accommodate a semiconductor integrated circuit chip having a larger number of terminals while having the same size as a conventional package.

本実施例を用いた半導体装置のプリント配線基板への実
装例の断面模式図を第6図に示す。
FIG. 6 shows a schematic cross-sectional view of an example of mounting a semiconductor device on a printed wiring board using this embodiment.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、プラグイン型のセラミッ
クパッケージの表面及び裏面の両面に外部接続リードビ
ンを設けることにより、パッケージ形状が同じでも、従
来以上の多端子を有する半導体チップを搭載でき、半導
体装置をプリント配線基板へ実装するに際してもプリン
ト配線基板の配線ピッチの縮小、配線層の多層化を必要
とせず高密度実装ができる効果がある。
As explained above, by providing external connection lead bins on both the front and back surfaces of a plug-in type ceramic package, the present invention makes it possible to mount a semiconductor chip with a larger number of terminals than before even though the package shape is the same. When mounting the device on a printed wiring board, there is an effect that high-density mounting can be achieved without reducing the wiring pitch of the printed wiring board or increasing the number of wiring layers.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)及び(C)はそれぞれ本発明の第
1の実施例を示す平面図、側面図及び裏面図、第2図(
a)、(b)及び(C)はそれぞれ第2の実施例を示す
平面図、側面図及び裏面図、第3図(a)、(b)及び
(c)はそれぞれ従来例の平面図、側面図及び裏面図、
第4図、第5図、第6図はそれぞれ従来例、第1の実施
例、第2の実施例を用いた半導体装置のプリント配線基
板への実装例の断面模式図である。 1.1′・・・セラミック基板、2・・・シールリング
、3・・・ボンディングパッド、4.4’ 、4″・・
・外部接続リードビン、5.キャビティ、11゜11′
・・・プリント配線基板。
Figures 1 (a), (b) and (C) are a plan view, side view and back view showing the first embodiment of the present invention, respectively, and Figure 2 (
a), (b), and (C) are respectively a plan view, a side view, and a back view showing the second embodiment; FIGS. 3(a), (b), and (c) are plan views of the conventional example, respectively; side view and back view,
FIG. 4, FIG. 5, and FIG. 6 are schematic cross-sectional views of examples of mounting a semiconductor device on a printed wiring board using the conventional example, the first embodiment, and the second embodiment, respectively. 1.1'... Ceramic substrate, 2... Seal ring, 3... Bonding pad, 4.4', 4''...
・External connection lead bin, 5. Cavity, 11°11'
...Printed wiring board.

Claims (1)

【特許請求の範囲】[Claims]  半導体チップを搭載するキャビティと、前記キャビテ
ィの周囲に設けられた複数のボンディングパッドと、前
記ボンディングパッドの周囲に設けられたシールリング
とを備えた多層セラミック基板内の両面に、前記ボンデ
ィングパッドと各々前記多層セラミック基板内の配線パ
ターンで接続された外部接続用リードピンが設けられて
なることを特徴とするプラグイン型パッケージ。
The bonding pads are placed on both sides of a multilayer ceramic substrate that includes a cavity for mounting a semiconductor chip, a plurality of bonding pads provided around the cavity, and a seal ring provided around the bonding pads. A plug-in type package characterized in that a lead pin for external connection is provided which is connected to a wiring pattern within the multilayer ceramic substrate.
JP25050487A 1987-10-02 1987-10-02 Plug-in type package Pending JPH0193157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25050487A JPH0193157A (en) 1987-10-02 1987-10-02 Plug-in type package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25050487A JPH0193157A (en) 1987-10-02 1987-10-02 Plug-in type package

Publications (1)

Publication Number Publication Date
JPH0193157A true JPH0193157A (en) 1989-04-12

Family

ID=17208867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25050487A Pending JPH0193157A (en) 1987-10-02 1987-10-02 Plug-in type package

Country Status (1)

Country Link
JP (1) JPH0193157A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567984A (en) * 1994-12-08 1996-10-22 International Business Machines Corporation Process for fabricating an electronic circuit package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567984A (en) * 1994-12-08 1996-10-22 International Business Machines Corporation Process for fabricating an electronic circuit package

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