JPS6063943U - Mount frame for semiconductor wafers - Google Patents

Mount frame for semiconductor wafers

Info

Publication number
JPS6063943U
JPS6063943U JP15658483U JP15658483U JPS6063943U JP S6063943 U JPS6063943 U JP S6063943U JP 15658483 U JP15658483 U JP 15658483U JP 15658483 U JP15658483 U JP 15658483U JP S6063943 U JPS6063943 U JP S6063943U
Authority
JP
Japan
Prior art keywords
opening
semiconductor wafer
mount frame
adhered
adhesive tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15658483U
Other languages
Japanese (ja)
Other versions
JPS6322676Y2 (en
Inventor
小野 喬利
Original Assignee
株式会社デイスコ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デイスコ filed Critical 株式会社デイスコ
Priority to JP15658483U priority Critical patent/JPS6063943U/en
Publication of JPS6063943U publication Critical patent/JPS6063943U/en
Application granted granted Critical
Publication of JPS6322676Y2 publication Critical patent/JPS6322676Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例を示すマウントフレーム
と半導体ウェハの平面図、第2図は本考案の第2の実施
例を示すマウントフレームの縦断面図、第3図は本考案
の第3の実施例を示すマウントフレームの縦断面図、第
4図は本考案の第4の実施例を示すマウントフレームの
縦断面図、第5図は本考案の第5の実施例を示すマウン
トフレームの縦断面図、第6図は本考案の第6の実施例
を示すマウントフレームの縦断面図である。 なお図面に用いた符号において、1・・・・・・マウン
トフレーム、2・・・・・・半導体ウェハ、3・・・・
・・開口、6・・・・・・接着テープ、14,19,2
5,30,35・・・・・・被接着面である。
Fig. 1 is a plan view of a mount frame and a semiconductor wafer showing a first embodiment of the present invention, Fig. 2 is a vertical cross-sectional view of the mount frame showing a second embodiment of the present invention, and Fig. 3 is a plan view of a mount frame and a semiconductor wafer showing a first embodiment of the present invention. FIG. 4 is a vertical cross-sectional view of the mount frame showing the third embodiment of the present invention, FIG. 5 is a longitudinal cross-sectional view of the mount frame showing the fourth embodiment of the present invention, and FIG. 5 shows the fifth embodiment of the present invention. FIG. 6 is a vertical cross-sectional view of a mount frame showing a sixth embodiment of the present invention. In addition, in the symbols used in the drawings, 1...Mount frame, 2...Semiconductor wafer, 3...
...Opening, 6...Adhesive tape, 14, 19, 2
5, 30, 35... are surfaces to be adhered.

Claims (1)

【実用新案登録請求の範囲】 1 半導体ウェハを収容するための開口をはり中央部に
有する板状部材からなり、この板状部材の一方の面であ
る被接着面に上記開口をは\゛覆うようにして接着され
た接着テープにより上記半導体ウェハを上部開口内で位
置決め保持するように構成された半導体ウェハ用マウン
トフレームにおいて、上記開口の周囲部分がこの周囲部
分以外の部分よりも上記接着テープに対して接着され易
いように上記マウントフレームの上記被接着面を構成し
たことを特徴とする半導体ウェハ用マウントフレーム、 2 上記被接着面において、上記開口の上記周囲部分以
外の部分を粗面に構成したことを特徴とする実用新案登
録請求の範囲第1項に記載の半導体ウェハ用マントフレ
ーム。 3 上記被接着面において、上記開口の上記周囲部分を
上記接着テープが接着し易い材料で構成し、この周囲部
分以外の部分を上記接着テープが接着し難い材料で構成
したことを特徴とする実用新案登録請求の範囲第1項に
記載の半導体ウェハ用マントフレーム。 4 上記被接着面において、上記開口の上記周囲部分以
外の部分に上記接着テープが接着し難い表面層を形成し
たことを特徴とする実用新案登録請求の範囲第3項に記
載の半導体ウェハ用マウントフレーム。 5 上記被接着面において、上記開口の上記周囲部分が
他の部分よりも相対的に高くなるように構成したことを
特徴とする実用新案登録請求の範囲第1項に記載の半導
体ウェハ用マウントフレーム。
[Claims for Utility Model Registration] 1. Consisting of a plate-shaped member having an opening in the center for accommodating a semiconductor wafer, and covering the opening on one surface of the plate-shaped member to be bonded. In the semiconductor wafer mount frame configured to position and hold the semiconductor wafer within the upper opening by the adhesive tape adhered in this manner, the area around the opening is more closely attached to the adhesive tape than the area other than the area around the opening. A mount frame for a semiconductor wafer, characterized in that the surface to be adhered of the mount frame is configured to be easily bonded to the mount frame, 2. A portion of the surface to be bonded other than the peripheral portion of the opening is configured to have a rough surface. A mantle frame for semiconductor wafers according to claim 1 of the utility model registration claim. 3. On the surface to be adhered, the peripheral part of the opening is made of a material to which the adhesive tape easily adheres, and the part other than the peripheral part is made of a material to which the adhesive tape is difficult to adhere. A mantle frame for a semiconductor wafer according to claim 1 of the patent registration claim. 4. The mount for a semiconductor wafer according to claim 3, wherein a surface layer to which the adhesive tape is difficult to adhere is formed on the surface to be adhered other than the peripheral portion of the opening. flame. 5. The semiconductor wafer mount frame according to claim 1, wherein the peripheral portion of the opening is relatively higher than other portions of the surface to be adhered. .
JP15658483U 1983-10-07 1983-10-07 Mount frame for semiconductor wafers Granted JPS6063943U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15658483U JPS6063943U (en) 1983-10-07 1983-10-07 Mount frame for semiconductor wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15658483U JPS6063943U (en) 1983-10-07 1983-10-07 Mount frame for semiconductor wafers

Publications (2)

Publication Number Publication Date
JPS6063943U true JPS6063943U (en) 1985-05-07
JPS6322676Y2 JPS6322676Y2 (en) 1988-06-22

Family

ID=30345467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15658483U Granted JPS6063943U (en) 1983-10-07 1983-10-07 Mount frame for semiconductor wafers

Country Status (1)

Country Link
JP (1) JPS6063943U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053162A (en) * 2005-08-16 2007-03-01 Shin Etsu Polymer Co Ltd Frame for dicing semiconductor wafer
JP2007335706A (en) * 2006-06-16 2007-12-27 Shin Etsu Polymer Co Ltd Carrier tool
JP2012109338A (en) * 2010-11-16 2012-06-07 Disco Abrasive Syst Ltd Processing method of work and dicing tape

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053162A (en) * 2005-08-16 2007-03-01 Shin Etsu Polymer Co Ltd Frame for dicing semiconductor wafer
JP4693545B2 (en) * 2005-08-16 2011-06-01 信越ポリマー株式会社 Semiconductor wafer dicing frame
JP2007335706A (en) * 2006-06-16 2007-12-27 Shin Etsu Polymer Co Ltd Carrier tool
JP2012109338A (en) * 2010-11-16 2012-06-07 Disco Abrasive Syst Ltd Processing method of work and dicing tape

Also Published As

Publication number Publication date
JPS6322676Y2 (en) 1988-06-22

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