JPS6059775B2 - Analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter, and in particular, an object of the present invention is to improve conversion accuracy defects caused by leakage of clock pulse noise from analog circuits in analog-to-digital converters integrated on the same semiconductor substrate. It is something to do.

The configuration of FIG. 1 shows a typical successive approximation type analog-to-digital converter. Comparator 1 compares the reference voltage applied to terminal 6 with the signal applied to terminal 9, and Output 11 is transmitted to memory 3.

The memories 3 are arranged in the number of conversion bits, and correspondingly, the shift counter 2 and the current switch 4 for selectively switching the binary weighted current to the addition line 10 are respectively connected in a one-to-one manner. In this case, memory 3 and shift counter 2
form a control circuit that controls the current switch 4. Conventionally, analog-to-digital converters with such a configuration have adopted a module type or a hybrid type in order to satisfy the specification conditions of conversion accuracy and conversion speed. In recent years, monolithic analog-to-digital J conversion has been introduced due to advances in the improvement of the high-frequency characteristics of integrated transistors, suppression of fluctuations in transistor device parameters during the manufacturing process, and strong demand for low-cost analog-to-digital converters. The device is being developed. However, if a digital circuit and an analog circuit are constructed on the same integrated semiconductor substrate, spike noise caused by a pulse signal in the digital circuit inevitably leaks to the analog circuit.

Therefore, a monolithic analog-to-digital converter has the disadvantage that conversion accuracy cannot be improved due to the influence of the noise. In particular, the shift counter 2 shown in FIG.
When a gate L is used in a control circuit such as the memory 3, the logic amplitude is as high as about 4 V, and the transistor operates in saturation, so that the pulse signal leaks to the semiconductor substrate as spike noise. Even if ECL is used in the control circuit for non-saturation operation with low logic amplitude, the logic level must be converted from ECL to TT'L when taking out the digital output. Therefore, spike noise occurs in the TTL portion. In addition, ECL has poor integration density, increases IC chip size, and wastes a lot of power. In view of the above points, the present invention uses an integrated injection logic circuit (IIL) that can improve integration density with low logic amplitude in the control circuit, and takes out the digital output from the current switch section, thereby creating a monolithic analog circuit.
The purpose is to improve accuracy defects caused by spike noise in digital converters.

The present invention will be described below with reference to the drawings and embodiments. FIG. 2 is a block diagram showing an embodiment of the present invention, in which a portion 201 surrounded by dotted lines shows a control circuit based on IIL,
A flip-flop is constructed.

The outputs 202 and 203 are out of phase with each other. I
The common emitter potential of IL2Ol is set lower than the current addition line 211 and higher than the common negative power supply line 209. The outputs 202 and 203 are in opposite phase to each other, and the differential input of the transistors 204 and 205 becomes approximately 0.7V due to the action of clamp circuits 213 and 214 provided at the IIL output section.
Clamp circuits 213 and 214 provide current balance 5 in the connection between IIL and transistors 204 and 205.
This is a current source added to maintain stable logic operation. Therefore, the threshold voltage of the paired switch of transistors 204 and 205 is approximately 0.1V, which is sufficient for switching. A current source 206 is connected between the common emitter electrodes of the three binary-weighted paired transistor switches and a common negative power supply line 209 . pair transistor 20
4 and 205 selectively switch the reference voltage 10 to the current addition line 211 and the common positive power supply line 212 by the IIL outputs 202 and 203. The digital output is taken out from the emitter electrode of the transistor 208 via the resistor 2074. As described above, by combining the integrated injection logic circuit and the current selection switch, the level exchange interface circuit that was conventionally required is not required, and
Since the digital output section does not require an interface circuit, it also has low logic amplitude characteristics and is free from spikes.
Not only can pulse leakage be reduced, but the number of circuit components can be reduced compared to conventional designs, making it possible to design for higher density and lower power consumption.

FIG. 3 is a diagram showing the configuration of a successive approximation type analog-to-digital converter according to the present invention.

Control circuit 307 configured by integrated injection logic circuit
The current changeover switches 304 and 305 are driven by the two phases Q and O from the current. The current source connected to the common emitter of the paired transistors 304 and 305 has the same current value for each bit.
Binary weighting is performed by a ladder resistor network 303 provided on the current summing line 316. Current switch 304 is turned on, weighted current flows through current addition line 316, and input 3
The sample and hold signals applied to the signal line 12 are compared by a comparator 301 via a span resistor 302. sample·
If the hold signal is large, the comparator output outputs a ``H'' level, and the control circuit 307 stores the ``H'' level as it is, and the switch 304 continues to be in the on state.At this time, the digital output is compared. When matched with the phase of the output of the transistor, the digital output becomes ``H'' level, but the emitter output from transistor 309 also becomes ``H'' level.The collector electrodes of resistor 308 and transistor 309 are connected to a common positive It is connected to a power supply line 310.The emitter electrode of the transistor 309 outputs a digital output.This output terminal is connected to an external system component, but usually a MOS logic IC or a TTL logic IC. In the case of MOS logic IC,
Transistor 309 operates as an emitter follower circuit and drives the gate electrode of the MOS transistor with low output impedance. In addition, in TTL logic IC,
Since the transistor 309 cannot absorb current, it can operate by connecting a resistor between the ground potential. In addition,
In FIG. 3, 313 is a common negative power supply line, and 314 and 315 are clock pulse inputs and reset pulse inputs to the control circuit. In this way, according to this embodiment, when the digital output is taken out from one collector electrode of the current switch, the current value flowing through it is the same for all bit outputs, so connection with an external system is possible. Become.

The method of making the reference current the same for all bits and providing a ladder-type resistor network on one side of the current switch, as in this embodiment, solves the above-described uneven output voltage. As explained above, according to the present invention, by using the integrated injection logic circuit with a current switch, a level conversion interface circuit is not required, and leakage of spike noise can be prevented due to the structure of the integrated injection logic circuit. , high density and low power consumption ratio can be achieved.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a successive approximation type analog-to-digital converter, Fig. 2 is a block diagram of a current switch according to the present invention, and Fig. 3 is a block diagram of a current switch according to the present invention.
The figure is a block diagram showing one embodiment of the analog-to-digital converter of the present invention. 301...Comparator, 302...Span resistance, 303...Ladder type resistance network, 304,3
05... vs. transistor, 306...
Current source, 307...Logic control circuit, 308...Resistor, 309...Transistor.

Claims (1)

[Claims] 1. A plurality of current switch circuits that output binary-weighted currents, a comparator that compares an input signal with an output current obtained by adding up the currents of the plurality of current switch circuits, and the comparator. and a control circuit that controls the addition of currents of the plurality of current switch circuits based on the output of the plurality of current switch circuits and a clock signal, wherein the control circuit is composed of an integrated injection logic circuit, and The current switch circuit includes a plurality of pairs of transistor switches that selectively switch the binary weighted current to the comparator and the power supply line via the resistor, and the current switch circuit includes a plurality of pairs of transistor switches that selectively switch the binary weighted current to the comparator and the power supply line via the resistor, and the current switch circuit is configured to control the voltage change occurring in the resistor. An analog-to-digital converter characterized by outputting as a digital output. 2. An analog-to-digital converter as claimed in claim 1, characterized in that the binary weighted current is obtained by a ladder resistor network connected to a plurality of current switch circuits. 3. The analog-to-digital converter according to claim 1, wherein the digital output is obtained by extracting a voltage change occurring in the resistor via a buffer transistor.