JPS6059769A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to readily alter a protecting withstand voltage by forming two or more reverse conductive type wells at the prescribed interval on one conductive type semiconductor substrate, connecting the one well to the substrate to set to the same potential and forming a diode of the other well and the substrate. CONSTITUTION:When a voltage is applied to an input terminal A, a depletion layer expands from a boundary between a P type silicon substrate 1 and a well region, and when N type well regions 3a, 3b are formed at a suitable distance, the regions 3a, 3b are connected via the depletion layer at a voltage lower than a breakdown voltage between the substrate 1 and the N type wells to flow a current. Accordingly, a voltage at a B point is clamped by the potential divided by a resistor R, but the voltage at the B point can be set to a voltage lower than the breakdown voltage between the substrate and the N type wells from lateral N-P-N type bipolar transistor characteristics having negative resistance. Consequently, when the regions 3a, 3b are formed at a suitable distance, the protecting voltage can be altered freely to a low voltage without increasing the density of the N type wells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a winter complementary MO8 semiconductor device equipped with an input protection device.

[Prior art]

A well-known input protection device for a complementary MO8 semiconductor device is one that uses a semiconductor substrate of one conductivity type and an impurity diffusion layer of an opposite conductivity type such as a source/drain or a well, and uses a down voltage as a protection voltage. There is.

However, in this structure, the protection voltage cannot be determined by the impurity concentration of each conductivity type, and in order to obtain a lower protection voltage, it is necessary to increase the impurity concentration. To achieve this, the number of steps required to form the dense layer must be increased, or if the source, drain, or well is used, the density can be increased, which increases the appearance of peripheral transistors and increases speed. It had the disadvantage of being blocked.

FIGS. 1 and 2 are cross-sectional views of a conventional input protection device for a complementary MO8 semiconductor device. In the input protection device shown in FIG. 1, an n+ diffusion layer 2 is provided on a p-type silicon substrate 1 when forming the source and drain of an n-channel transistor, and its breakdown voltage is utilized. The device utilizes the breakdown voltage with the n-well layer when an n-well 3 is formed on a p-type silicon substrate l. The protection voltage of these input protection devices is p
Since it is determined by each layer Jσ of the type silicon substrate, n+ diffusion layer, and n well layer, should the protection voltage be lower than this? If the impurity layers j9- are different from each other, it is necessary to make one of the impurity layers j9- This has the disadvantage that it requires the use of a different memory, which increases the capacity and impedes speed-up.

[Purpose of the invention]

The object of the present invention is to eliminate the following two drawbacks and to provide a semiconductor device equipped with an input protection device that can easily change the protection pressure without changing the impurity concentration or increasing the total number of steps. 11. There is something to do.

[Structure of the invention]

In the semiconductor device of the present invention, two or more wells of a conductivity type opposite to that of the semiconductor substrate are provided on a -conductivity type semi-DH substrate, separated by a predetermined distance, and one well is all connected to the semiconductor substrate to have the same potential. , the other well and the semiconductor substrate form a diode.

[Explanation of Examples]

Next, regarding the embodiments of the present invention,
+! tj l.

I will explain.

FIG. 3 is a sectional view of one embodiment of the present invention.

In FIG. 3, ``■'' is a 9m7+) silicon substrate, and an n-well 3a formed of the opposite conductivity type is formed on this silicon substrate.

3b.
The well 3b is connected to the silicon substrate through the n''-diffusion layer by the Kamasaka medium 10, and is made to have the same potential as the silicon substrate. Note that 8 is the p-diffusion layer formed on the surface of the silicon substrate. Possible other well 3a Id, p
A mold silicon substrate 1 and a diode are formed. Here, 2 is an n+ diffusion layer. Note that 4 is a silicon oxide film, 7 is a field oxide film, 9 is an interlayer insulating film, A is an input terminal, B is an internal circuit input potential point, and R is a resistor.

When a voltage is applied to the input terminal A of the input protection device having the configuration shown in FIG. If the n-well regions 3a and 3b are formed at a lower voltage than the constant voltage of the breakdown 71T between the p-type silicon substrate l and the n-well, the depletion layer will connect the n-well regions 3a and 3b, and a current will flow.

Therefore, the voltage at point B is clamped at the divided potential with resistor R, but due to the characteristics of a lateral npn bipolar transistor with negative resistance, the voltage at point B is lower than the breakdown voltage between the p-type silicon substrate and the n-well. It becomes possible to lower the voltage below that. Therefore, by forming n-well regions 3a and 3b at an appropriate distance, the n-well concentration can be reduced to t.
It is possible to freely change the protection voltage to a low value by design, such as the distance between the n-wells, without increasing the voltage.

FIGS. 4A to 4E are cross-sectional views shown in order of steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 4(a), a p-type silicon substrate l
A silicon oxide film 4 is formed thereon, and then the portions other than those where the n-well region is to be formed are covered with photoresist 5.

Next, as shown in FIG. 4 (bJ), as a photoresist lf mask, for example, ion implantation of phosphorus is performed, the photoresist lc is removed, and high temperature heat treatment is performed to form the n wells 3a, 3.
b Complete formation.

Next, as shown in FIG. 4 (C1), after forming an oxidation-resistant material, for example, a silicon nitride film 6, the silicon nitride film outside the element formation region is selectively etched.

Next, as shown in FIG. 4(d), a field oxide film 7 is formed by oxidation, and then the silicon nitride film 6 is removed.

Next, as shown in FIG. 4, a normal complementary MO8
In accordance with a semiconductor device manufacturing method, the n-diffusion layer 2 is formed by, for example, phosphorus ion implantation, the p-diffusion layer 8 is formed by boron ion implantation, the interlayer insulating film 9 is formed, and the layers are formed on the n-well and on the p-type silicon substrate. A contact hole is formed in , and the p-type silicon substrate and n-well 3b are electrically connected by metal wiring 10 to obtain a semiconductor device having a structure similar to that shown in FIG.

FIGS. 5 and 6 are plan views of modified examples of n-wells formed at a distance, in which collapse is also a component of the embodiment of the present invention. Of course, the number and shape of n-wells formed at this distance are not limited to those in the above example.

In the above detailed explanation of the present invention, p-type silicon No. 1 is used.
(Although a plate is used as an example, it is not necessary to explain that the same can be applied to an n-type silicon substrate.

〔Effect of the invention〕

As explained above, according to the present invention, a semiconductor device equipped with a 7′ζλ force protection device having a target protection voltage can be easily installed without changing the impurity concentration or adding a new process. ;J can do it.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a conventional input protection device of a complementary MO8 semiconductor device, FIG. 3 is a cross-sectional view of an embodiment of the present invention, and FIGS. 4(a) to (eJ are Cross-sectional views shown in the order of steps for explaining the manufacturing method of one embodiment, FIGS. 5 and 6
Each figure is a plan view of a modified example of an N-well in which the components of the embodiment of the present invention are formed at a distance. 1...p-type silicon substrate, 2...n
Diffusion layer, 3a, 3b...N-well, 4...
・/Recon oxidation [;q15...Photoresist,
6...Silicon oxide film, 7...Field oxide film, 8...P+ diffusion layer, 9...
Interlayer insulating film, 10... Metal interconnection MJ, A...
...Input terminal, B...Internal circuit input potential point, ■ also...Resistance. Agent: Patent Attorney Uchihara 1. d2 gokado sword

Claims (1)

[Claims] Two or more wells of a conductivity type opposite to one semiconductor substrate are provided in a semiconductor substrate of one conductivity type, separated by a certain distance, one well is connected to the semiconductor substrate to have the same potential, and the other well and the semiconductor substrate are connected to each other at the same potential. A semiconductor device characterized in that a diode is formed by and.