JPH0319276A - Cmos semiconductor device - Google Patents
Cmos semiconductor deviceInfo
- Publication number
- JPH0319276A JPH0319276A JP1153435A JP15343589A JPH0319276A JP H0319276 A JPH0319276 A JP H0319276A JP 1153435 A JP1153435 A JP 1153435A JP 15343589 A JP15343589 A JP 15343589A JP H0319276 A JPH0319276 A JP H0319276A
- Authority
- JP
- Japan
- Prior art keywords
- element isolation
- well
- type
- region
- isolation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000010410 layer Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 239000010408 film Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 229910021332 silicide Inorganic materials 0.000 abstract description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000000452 restraining effect Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はラッチアップ耐性の優れた構造を有するＣＭＯ
Ｓ型半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a CMO having a structure with excellent latch-up resistance.
The present invention relates to an S-type semiconductor device.
従来の技術
近年半導体装置は低消費電力の要求からＣＭＯＳ型半導
体装置の開発が主流となってきている。しかしＣＭＯＳ
型半導体装置では寄生サイリスタ構造を有するため外部
からのトリガー電流によってラッチアップを生じる可能
性がある。そしてラッチアップが生じると過大電流が流
れ動作不良となるばかうでなく素子破壊に到ることもあ
る。2. Description of the Related Art In recent years, the development of CMOS type semiconductor devices has become mainstream due to the demand for low power consumption. However, CMOS
Since a type semiconductor device has a parasitic thyristor structure, latch-up may occur due to an external trigger current. When latch-up occurs, an excessive current flows, resulting in not only malfunction but also element destruction.
このラッチアップ現象は外部トリガーにより基板内１た
はウェル内に流れ込んだ電流によって基板電位１たはウ
ェル電位が所望の電位から変動するために生じるので基
板１たはウェルの電位変動を抑えることによってラッチ
アップ耐性を向上させることが可能となる。This latch-up phenomenon occurs because the substrate potential 1 or well potential fluctuates from the desired potential due to the current flowing into the substrate 1 or well due to an external trigger. Therefore, by suppressing the potential fluctuation of the substrate 1 or well, It becomes possible to improve latch-up resistance.
以下にラッチアップ耐性を向上させるための従来の技術
について第２図の断面図を用いて説明する。A conventional technique for improving latch-up resistance will be described below with reference to the cross-sectional view of FIG. 2.
図中１はＰ型シリコン基板、２はＮウェル領域、３は素
子分離領域である。そしてＮウェル領域２内にはゲート
酸化膜８１、ゲート電極９１かよびＰ型拡散層１０によ
ってＰチャンネルトランジスタが形成されておシ、同様
にゲート酸化膜８２、ゲート電極９２かよびＮ型拡散層
１１によってＮチャンネルトランジスタが形成されてい
る。In the figure, 1 is a P-type silicon substrate, 2 is an N-well region, and 3 is an element isolation region. A P channel transistor is formed in the N well region 2 by a gate oxide film 81, a gate electrode 91, and a P type diffusion layer 10, and a P channel transistor is formed by a gate oxide film 82, a gate electrode 92, and an N type diffusion layer. 11 forms an N-channel transistor.
１２はＮウェル領域内のＮ型拡散層であう，通常このＮ
型拡散層１２を介してＮウェル領域２に所望の電圧、例
えば電源電圧を与える構造になっている。12 is an N type diffusion layer in the N well region.
The structure is such that a desired voltage, for example, a power supply voltage, is applied to the N-well region 2 via the type diffusion layer 12.
そしてラッチアップ耐性を向上させるためには、このＮ
ウェル内Ｎ型拡散層１２をＮウエ〃領域２の周囲を囲む
ように形成することが望ましい。すなわち、Ｎウェル内
Ｎ型拡散層を介してのＮウェル領域２への電圧供給を充
分に行うことによって、外部トリガーによってもＮウエ
μ内の電位変動を少なく抑えることができ、ラフチアッ
プ耐性の向上が図れる。In order to improve latch-up resistance, this N
It is desirable to form the in-well N-type diffusion layer 12 so as to surround the N-well region 2 . In other words, by sufficiently supplying voltage to the N-well region 2 through the N-type diffusion layer in the N-well, potential fluctuations in the N-well μ can be suppressed to a small level even by an external trigger, improving resistance to rough-up. can be achieved.
発明が解決しようとする課題
しかし上述の従来例では、Ｎウエμ内のＮ型拡散層に所
定の電位を与える構造であシ、このＮ型拡散層領域は全
プロセスの初期の段階のいわゆる素子分離領域形戒工程
で確・定するため、試作品評価結果を基にラッチアップ
耐性を強化しようとしても、素子分離領域形戒用マスク
を変更する必要があ９、マスク対策の効果が確認できる
１でに長時間を要してし１い、プロセス釦よびデバイス
の開発期間を短縮することが困難であった。Problems to be Solved by the Invention However, in the above-mentioned conventional example, the structure is such that a predetermined potential is applied to the N-type diffusion layer in the N-wafer μ, and this N-type diffusion layer region is used in the so-called element at the initial stage of the entire process. Even if we try to strengthen the latch-up resistance based on the prototype evaluation results, it is necessary to change the element isolation region shape mask because it is confirmed in the isolation region shape control process9, so the effectiveness of the mask countermeasure can be confirmed. However, it is difficult to shorten the development period for process buttons and devices.
本発明は上記従来の問題点を解決するもので、Ｎ型拡散
層がなくてもＮウェルに所定の電位を与えることのでき
る自由度の高い、ラッチアップ耐性の優れたＣＭＯＳ型
半導体装置を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and provides a CMOS semiconductor device with a high degree of freedom in which a predetermined potential can be applied to an N-well without an N-type diffusion layer and with excellent latch-up resistance. The purpose is to
課題を解決するための手段
この目的を達或するために本発明の半導体装置は、電極
配線層を形成するＮ型導電性薄膜がＰ型シリコン基板上
のＮウェル領域内の素子分離領域の一部に設けられた開
口部および前記素子分離領域の上部に形戒された層間絶
縁膜に設けられた開口部を介して前記素子分離領域の下
部のＮウェル領域の表面と接し、前記Ｎウェル領域の表
面領域に前記Ｎ型導電性薄膜からの熱拡散により形成さ
れたＮ型拡散層を有する。Means for Solving the Problems In order to achieve this object, the semiconductor device of the present invention has a semiconductor device in which an N-type conductive thin film forming an electrode wiring layer is formed in a part of an element isolation region in an N-well region on a P-type silicon substrate. The surface of the N-well region under the element isolation region is in contact with the surface of the N-well region under the element isolation region through an opening provided in the upper part of the element isolation region and an opening provided in an interlayer insulating film formed above the element isolation region. has an N-type diffusion layer formed by thermal diffusion from the N-type conductive thin film in the surface region.
作 用
本発明のＣＭＯＳ型半導体装置によれば、Ｎ型導電性薄
膜に簡単な製造工程によシ所定の電位を与えることによ
って素子分離領域上から直接Ｎウェル領域へ所定の電位
を与えることができるため、Ｎウェル内のＮ型拡散層を
必要とせず、従来よう高い自由度でＮウエρへ所定の電
位を与えることができ、ラッチアップ耐性の優れたＣＭ
ＯＳ型半導体装置を得ることができる。According to the CMOS type semiconductor device of the present invention, by applying a predetermined potential to the N-type conductive thin film through a simple manufacturing process, it is possible to directly apply a predetermined potential to the N-well region from above the element isolation region. As a result, a predetermined potential can be applied to the N-well ρ with a high degree of freedom unlike conventional methods without requiring an N-type diffusion layer in the N-well, making it possible to create a CM with excellent latch-up resistance.
An OS type semiconductor device can be obtained.
実施例
以下本発明の一実施例について図面を参照しながら説明
する。第１図は本発明の半導体装置の実施例の断面図を
示すものである。第１図において、１はＰ型シリコン基
板、２はＮウェル領域、３は素子分離領域、４は層間絶
縁膜、６は４０層間絶縁膜および３の素子分離領域に設
けられたコンタクト用窓、６はＮ型ボリシリコン層、７
は６のポリシリコン層と共にポリサイド配線を形成する
シリサイド層、８は６０Ｎ型ポリシリコン層からの熱拡
散によって形威されたＮ型拡散層である。その他は第２
図の説明と同様である。図からも明らかなように、ポリ
サイド配線層６，７に所定の電位を与えるとＮ型拡散層
８を介して素子分離用酸化膜の下のＮウエ〃領域に所定
の電位を与えることが可能となる。EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional view of an embodiment of the semiconductor device of the present invention. In FIG. 1, 1 is a P-type silicon substrate, 2 is an N-well region, 3 is an element isolation region, 4 is an interlayer insulating film, 6 is a 40 interlayer insulating film, and 3 is a contact window provided in the element isolation region. 6 is an N-type polysilicon layer, 7
A silicide layer forms a polycide wiring together with the polysilicon layer 6, and an N-type diffusion layer 8 is formed by thermal diffusion from the 60N-type polysilicon layer. Others are second
It is the same as the explanation of the figure. As is clear from the figure, when a predetermined potential is applied to the polycide wiring layers 6 and 7, it is possible to apply a predetermined potential to the N-wafer region under the element isolation oxide film via the N-type diffusion layer 8. becomes.
発明の効果
以上のような構造を有するＣＭＯＳ型半導体装置を用い
れば、外部トリガーによるＮウェルの電位変動を抑える
ための所定電位供給を従来よシ高い自由度で実施するこ
とができ、ラッチアップ耐性の優れた信頼性の高いＣＭ
ＯＳ型半導体装置を実現できる。さらに本発明の構造は
溝掘シ型キャパシター構造を有するＤＲＡＭプロセスに
全く変更を加えずに導入することが可能であり、さらに
開発段階でラッチアップ耐性を強化する場合コンタクト
窓用マスク以降の変更にて対処できるため開発効率を上
げることが可能となる。Effects of the Invention By using a CMOS type semiconductor device having a structure as described above, it is possible to supply a predetermined potential to suppress N-well potential fluctuations caused by an external trigger with a higher degree of freedom than before, and the latch-up resistance is improved. Excellent and reliable commercials
An OS type semiconductor device can be realized. Furthermore, the structure of the present invention can be introduced into a DRAM process having a grooved capacitor structure without making any changes, and furthermore, if latch-up resistance is to be strengthened at the development stage, changes after the contact window mask can be implemented. This makes it possible to improve development efficiency.
第１図は本発明実施例のＣＭＯＳ型半導体装置の断面図
、第２図は従来例を説明するための断面図である。
１・・・・・・Ｐ型シリコン基板、２・・・・・・Ｎウ
エ〃領域、３・・・・・・素子分離領域、４・・・・・
・層間絶縁膜、６・・・・・・コンタクト用窓、ｅ・・
・・・・Ｎ型ポリシリコＸ薄膜、７・・・・・・シリサ
イド薄膜、８１ ，８２・・・・・・ゲート酸化膜、９
１，９２・・・・・・ゲート電極、１０・・・・・・Ｐ
型拡散層、１１・・・・・・Ｎ型拡散層、１２・・・・
・・Ｎウェル内Ｎ型拡散層、１３・・・・・・Ｎ型ポリ
シリコン薄膜からの熱拡散によυ形成されたＮ型拡散層
。FIG. 1 is a sectional view of a CMOS type semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view for explaining a conventional example. 1...P type silicon substrate, 2...N wafer region, 3...element isolation region, 4...
・Interlayer insulating film, 6... Contact window, e...
...N-type polysilico X thin film, 7... Silicide thin film, 81, 82... Gate oxide film, 9
1,92...gate electrode, 10...P
Type diffusion layer, 11...N type diffusion layer, 12...
...N-type diffusion layer in N-well, 13...N-type diffusion layer formed by thermal diffusion from the N-type polysilicon thin film.
Claims (1)
半導体装置において電極配線層を形成するＮ型導電性を
有する導電性薄膜が前記Ｎウェル領域内の素子分離領域
の一部に設けられた開口部および前記素子分離領域の上
部に形成された層間絶縁膜に設けられた開口部を介して
前記素子分離領域の下部のＮウェル領域の表面と接し、
前記Ｎウェル領域の表面領域に前記Ｎ型導電性を有する
導電性薄膜からの熱拡散により形成されたＮ型拡散層を
有することを特徴とするＣＭＯＳ型半導体装置。In a CMOS semiconductor device having an N-well region on a P-type silicon substrate, a conductive thin film having N-type conductivity forming an electrode wiring layer is provided in a part of an element isolation region in the N-well region. and in contact with the surface of the N-well region under the element isolation region through an opening provided in an interlayer insulating film formed on the upper part of the element isolation region,
A CMOS type semiconductor device comprising an N-type diffusion layer formed by thermal diffusion from the conductive thin film having N-type conductivity in a surface region of the N-well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1153435A JPH0319276A (en) | 1989-06-15 | 1989-06-15 | Cmos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1153435A JPH0319276A (en) | 1989-06-15 | 1989-06-15 | Cmos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0319276A true JPH0319276A (en) | 1991-01-28 |
Family
ID=15562461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1153435A Pending JPH0319276A (en) | 1989-06-15 | 1989-06-15 | Cmos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0319276A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846058A (en) * | 1994-08-01 | 1996-02-16 | Nec Corp | Manufacture of mos semiconductor device |
| EP0721217A3 (en) * | 1995-01-05 | 1999-06-16 | Texas Instruments Inc. | CMOS integrated circuits |
-
1989
- 1989-06-15 JP JP1153435A patent/JPH0319276A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846058A (en) * | 1994-08-01 | 1996-02-16 | Nec Corp | Manufacture of mos semiconductor device |
| EP0721217A3 (en) * | 1995-01-05 | 1999-06-16 | Texas Instruments Inc. | CMOS integrated circuits |
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