JP2002009277A - Offset gate type fet and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress channel generation and improve breakdown voltage without extension of offset region or the like. SOLUTION: A second gate electrode 17 between a source region 12 and a gate region 14 and another second gate electrode 17 between a drain region 13 and the gate region 14 cover offset regions 16. The second electrodes 17 are electrically connected to back-gate regions 15 and are held at back-gate voltage. Therefore, when a FET, comprising the source region 12 the drain region 13 and the gate region 14, is turned off, the offset regions 16 under the second gate electrodes 17 are turned off, and channel generation is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage utilizing an offset region (a region provided between active regions of a transistor requiring a withstand voltage and having a low impurity concentration and a thick insulating film where a channel is unlikely to be generated) And a semiconductor device having a plurality of FETs.

[0002]

2. Description of the Related Art FIGS. 2A and 2B are structural views showing an example of a conventional offset gate type FET.
2 is a plan view, and FIG. 2B is a cross-sectional view taken along line AA of FIG.

[0003] The drain offset gate type FET is a high voltage transistor using the offset region, the N-type silicon substrate 1, consisting of a source region 2 and the P ⁺ impurity layer composed of P ⁺ impurity layer is the active region The region 3 is formed to face at a predetermined distance.
A gate region 4 is formed between the source region 2 and the drain region 3. Gate region 4 has a gate oxide film 4a formed on the surface of silicon substrate 1 between source region 2 and drain region 3, and gate electrode 4b is formed on gate oxide film 4a.

In a silicon substrate 1, a back gate region 5 made of an N ⁺ impurity layer, which is an active region, is surrounded by a source region 2, a drain region 3 and a gate region 4.
Are formed. The back gate region 5 has a function of a channel stopper. An offset region 6 is formed in the silicon substrate 1 between the source region 2, the drain region 3, and the gate region 4 and the back gate region 5. The offset region 6 has a P-type offset layer 6a which is an offset impurity layer having a lower concentration than the source region 2 and the drain region 3, and an offset oxide film 6b thicker than the gate oxide film 4a is formed on the offset layer 6a. Is formed.

An insulating film 7 covering the entire surface is formed on the source region 2, drain region 3, gate region 4, back gate region 5, and offset region 6, and a plurality of contact holes are formed in predetermined portions of the insulating film 7. 8 is open.
A metal wiring 9 is formed on each contact hole 8,
The metal wiring 9 is electrically connected to the source region 2, the drain region 3, the gate region 4, and the back gate region 5 via the contact hole 8. The metal wiring 9 is covered with a passivation film 10.

In such an offset gate type FET, the drain region is located between the drain region 3 and the source region 2.
When the source-to-source voltage Vds is applied, the drain current Id flows in the following path: drain region 3 → offset layer 6a → below gate region 4 → offset layer 6a → source region 2.
When a reverse voltage is applied to the PN junction between the gate region 4 and the source region 2, the depletion layer of the PN junction expands due to the reverse voltage, the path (channel) of the drain current Id becomes narrow, and the current hardly flows. . For this reason, the magnitude of the drain current Id can be changed by the gate-source voltage Vgs. When the FET is in the off state, it is necessary to suppress the generation of a channel to cut off the drain current Id. In view of this, the offset region 6 is provided to suppress the generation of a channel, thereby achieving a high breakdown voltage.

[0007]

However, conventional offset gate type FETs and semiconductor devices using the same have the following problems (A) and (B). (A) In an offset gate type FET as shown in FIG.
As the target breakdown voltage increases, the width of the offset region 6 has been increased in order to suppress the generation of a channel below the offset region 6 between the source region 2 and the drain region 3 as active regions.

However, when the offset region 6 is expanded to increase the breakdown voltage, the transistor size increases,
For example, when a large number of transistors are manufactured using one wafer, the number of transistors obtained is reduced, and the productivity of products using the transistors is reduced. Further, the enlargement of the offset region 6 between the source region 2 and the gate region 4 and between the drain region 3 and the gate region 4
The ds-Id characteristic curve increases and the sensitivity decreases, and FE
This causes the electrical characteristics of T to deteriorate.

In order to improve the breakdown voltage of the FET without increasing the size of the offset region 6,
It is necessary to suppress the generation of channels in the offset region 6. However, in order to realize this, it is necessary to change the impurity concentration of the offset layer 6a in the offset region 6 and the thickness of the oxide film 6b, and it is necessary to change or add a wafer process.

(B) In a semiconductor device, for example, a first transistor group consisting of a plurality of FETs and a second transistor group consisting of a plurality of FETs of the same conductivity type are separated by a predetermined distance in a semiconductor substrate. In some cases, a channel stopper region is provided between the first and second transistor groups to suppress the generation of a channel, cut off a leak current, and increase a breakdown voltage. Even in such a case, similarly to the problem (A), it is difficult to suppress generation of a channel and increase the breakdown voltage of a semiconductor device without expanding a channel stopper region.

The present invention solves the problems of the prior art, and has an offset gate type FET capable of suppressing the generation of a channel and improving the breakdown voltage without expanding an offset region and the like, and a plurality of FETs. It is an object to provide a semiconductor device.

[0012]

According to a first aspect of the present invention, there is provided an offset gate type FET having an impurity layer formed in a semiconductor substrate and opposed to a semiconductor substrate at a predetermined distance. A gate insulating film formed on a surface of the semiconductor substrate between the source region and the drain region; and a first insulating film formed on the gate insulating film. A gate region having a gate electrode; a back gate region formed of an impurity layer formed in a ring shape in the semiconductor substrate so as to surround the source region, the drain region and the gate region; and the source region and the drain region. And an offset impurity layer formed in the semiconductor substrate between the gate region and the back gate region and having a lower concentration than the source region and the drain region. An offset region formed on the offset impurity layer and having an offset insulating film thicker than the gate insulating film, between the source region and the gate region, and between the drain region and the gate region. A second gate electrode formed so as to cover all or a part of the offset region and electrically connected to the back gate region.

Thus, when a voltage is applied between the drain region and the source region, a channel is formed and a drain current flows, and the magnitude of the drain current is changed by the gate-source voltage. In the off state of the FET, the offset region below this is turned off by the second gate electrode held at the back gate potential, and the generation of a channel in this offset region is suppressed.

A second invention is an offset gate type FET
A source region, a drain region, a gate region, a back gate region, and an offset region of the first invention, and all or a part of the offset region around the source region and the drain region. A second gate electrode electrically connected to the back gate region.

Thus, when the FET is off, the second gate electrode held at the back gate potential allows
The source region and the gate region are turned off, and the drain region and the gate region are turned off, so that the generation of a channel in the offset region below the second gate electrode is suppressed. Further, the second gate electrode held at the back gate potential turns off the source region and the back gate region, and turns off the drain region and the back gate region. Is suppressed.

A third invention is an offset gate type FET
The source region, the drain region, the gate region, the back gate region, and the offset region of the first invention, between the source region and the back gate region, and between the drain region and the back gate region. A second gate electrode formed so as to cover all or a part of the offset region, and electrically connected to the back gate region.

Thus, the second gate electrode held at the back gate potential turns off the source region and the back gate region and turns off the drain region and the back gate region. , Channel generation is suppressed.

According to a fourth aspect of the present invention, in the semiconductor device, a first transistor group including a plurality of first conductivity type FETs formed in a semiconductor substrate and a predetermined distance from the first transistor group in the semiconductor substrate. A second transistor group consisting of a plurality of first conductivity type FETs formed at a distance from each other; and an impurity formed in the semiconductor substrate near the first and second transistor groups and held at a predetermined substrate potential. An active region composed of a layer, a gate electrode formed on the semiconductor substrate so as to cut off between the first transistor group and the second transistor group, and electrically connected to the active region; It has.

As a result, the gate electrode kept at a predetermined substrate potential turns off the first transistor group and the second transistor group, thereby suppressing generation of a channel and cutting off a leak current. .

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG.
1B is a configuration diagram of an offset gate type FET showing a first embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a BB line of FIG. It is sectional drawing.

In this offset gate type FET, a source region 12 made of a P ⁺ impurity layer and a drain region 13 made of a P ⁺ impurity layer, which are active regions, are formed in a semiconductor substrate (eg, an N-type silicon substrate) 11. They are formed facing each other at a predetermined distance. A gate region 14 is formed between the source region 12 and the drain region 13 which are active regions. The gate region 14 is formed on the silicon substrate 11 between the source region 12 and the drain region 13.
Has a gate insulating film (for example, a gate oxide film) 14a formed on the surface thereof, and a first gate electrode 14b of polysilicon or the like is formed on the gate oxide film 14a. An annular back gate region 15 is formed in the silicon substrate 11 so as to surround the source region 12, the drain region 13 and the gate region 14. Back gate area 1
Reference numeral 5 is made of an N ⁺ impurity layer and has a function as a channel stopper.

An offset region 16 is formed in the silicon substrate 11 between the source region 12, the drain region 13, and the gate region 14 and the back gate region 15. An offset impurity layer (for example, a P-type offset layer) 16 a having a lower concentration than the source region 12 and the drain region 13 is formed in the offset region 16, and an offset insulating layer thicker than the gate oxide film 14 a is formed on the offset layer 16 a. A film (for example, an oxide film) 16b is formed. An offset region 16 between the source region 12 and the gate region 14 and between the drain region 13 and the gate region 14
Above, a second gate electrode 17 of polysilicon or the like is formed so as to cover all or a part of these offset regions 16.

An insulating film 18 of phosphor silica or the like is formed on the entire surface of the source region 12, the drain region 13, the gate region 14, the back gate region 15, and the like. Insulating film 18
In FIG. 1, a contact hole 19 is formed on the source region 12, the drain region 13, the gate region 14, the back gate region 15, and the second gate electrode 17.
A metal wiring 20 of aluminum or the like is formed on the contact hole 19, and the metal wiring 20 is connected to the source region 12 and the drain region 1 through the contact hole 19.
3, the gate region 14, the back gate region 15, and the second gate electrode 17 are electrically connected. Further, both ends of the gate electrode 17 are electrically connected to the back gate region 15 via a contact hole 19 and a metal wiring 20. A passivation film 21 such as a nitride film is formed on the entire surface of the metal wiring 20.

Such an offset gate type FET is
For example, it is manufactured as follows. Silicon substrate 11
P-type impurity ions are implanted at predetermined locations by using photolithography technology to form a plurality of offset layers 16a. On each offset layer 16a, a thick oxide film 16b is formed by thermal oxidation or the like. Each oxide film 1
A gate oxide film 14a is formed between 6b. A first gate electrode 14b of polysilicon or the like is formed on the gate oxide film 14a by a photolithography technique, and a polysilicon is formed on the oxide film 16b between the gate region 14 and the source region 12 and the drain region 13. The second gate electrode 17 is formed.

P ⁺ impurity ions are implanted between the offset regions 16 to form the source region 12 and the drain region 13, and N ⁺ impurity ions are implanted to form the back gate region 15. An insulating film 18 is formed on the entire surface, and the source region 12, the drain region 13, and the gate electrode 1 are formed.
A contact hole 19 is opened on 4b, 17 and the back gate region 15. A metal wiring 20 is formed on each contact hole 19 by photolithography. Thereafter, if the passivation film 21 is formed on the entire surface, the manufacture of the offset gate type FET of FIG. 1 is completed.

In the offset gate type FET manufactured as described above, when a voltage is applied between the drain region 13 and the source region 12 by the metal wiring 20, the drain region 13 → the offset layer 16a → the gate oxide film 14a
A drain current Id flows through a path of lower → offset layer 16a → source region 12, and a gate-source voltage Vg
The magnitude of the drain current Id can be changed depending on s. The gate electrode 17 between the source region 12 and the gate region 14 and the gate electrode 17 between the drain region 13 and the gate region 14 are connected to the back gate region 15 by the metal wiring 20 and are held at the back gate potential. . Therefore, in the off state between the source region 12 and the drain region 13 in the FET, the source region 12
The channel between the gate region 14 and the drain region 13 is turned off to suppress channel generation, and the channel between the drain region 13 and the gate region 14 is turned off to suppress channel generation.

In the first embodiment, the following (1):
This has the effect (2). (1) In the off state between the source region 12 and the drain region 13 in the FET, the gate electrode 17 between the source region 12 and the gate region 14 and the drain region 13
The gate electrode 17 between the gate electrode 14 and the gate region 14 is turned off by operating as an FET, and the generation of a channel below these gate electrodes 17 is suppressed. Therefore, the breakdown voltage between the source region 12 and the gate region 14 and between the drain region 13 and the gate region 14 are improved. Conversely, the breakdown voltage is suppressed to a constant value, the length of the offset region 16 between the source region 12 and the gate region 14 and the length of the offset region 16 between the drain region 13 and the gate region 14 are reduced, and the transistor size is reduced. It is also possible. In addition, the gate electrode 17 is
Since it is formed simultaneously using the same material as 4b, there is no need to change or add a wafer process.

(2) Since the potential of the gate electrode 17 is connected to the back gate region 15 and is maintained at the back gate potential, the potential is constant regardless of the on / off state of the FET. Also less.

(Second Embodiment) FIGS. 3A and 3B show an offset gate type FE showing a second embodiment of the present invention.
FIG. 2A is a configuration diagram, FIG. 2A is a plan view, and FIG.
FIG. 3 is a cross-sectional view taken along line CC of FIG. In this FIG.
Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

In this offset gate type FET, FIG.
In place of the second gate electrode 17, a second gate electrode 17A having a different planar shape is provided. The second gate electrode 17A is formed on substantially the entire surface of the offset region 16, and between the source region 12 and the gate region 14, between the drain region 13 and the gate region 14, between the source region 12 and the back gate region 15, Further, the drain region 13
And the back gate region 15.
The second gate electrode 17A is formed at the same time using, for example, a material such as polysilicon similar to the first gate electrode 14b. The periphery of gate electrode 17A is electrically connected to back gate region 15 via contact hole 19 and metal wiring 20. Other configurations are the same as those of the first embodiment. This offset gate type F
The ET has almost the same operation and effect as the first embodiment.

Further, in the offset gate type FET according to the second embodiment, the source region 12 and the gate region 14
Offset region 16 between the source region 12 and the back gate region 15 and between the drain region 13 and the back gate region 15 as well as between the drain region 13 and the gate region 14.
Is the second gate electrode 1 held at the back gate potential
7A. Therefore, in the off state between the source region 12 and the drain region 13 in the FET,
Between source region 12 and gate region 14, drain region 13
-Between the gate regions 14, between the source region 12 and the back gate region 15, and between the drain region 13 and the back gate region 1.
Each of the five operates as an FET and is turned off,
Channel generation under these gate electrodes 17A is suppressed.

Therefore, the source region 12 and the gate region 14
The breakdown voltage between the drain region 13 and the gate region 14 is improved, and the source region 12 and the back gate region 1 are improved.
5 and between the drain region 13 and the back gate region 15 are also improved, and the withstand voltage of the FET is further improved as compared with the first embodiment.

(Third Embodiment) FIGS. 4A and 4B show an offset gate type FE according to a third embodiment of the present invention.
3A is a configuration diagram of T, FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line DD of FIG. This figure 4
In the figure, the same reference numerals are given to the same components as those in the first embodiment shown in FIG.

In this offset gate type FET, FIG.
In place of the second gate electrode 17, a second gate electrode 17B having a different planar shape is provided. The second gate electrode 17B includes the source region 12 and the back gate region 15
And the offset region 16 between the drain region 13 and the back gate region 14. The second gate electrode 17B is formed at the same time using, for example, a material such as polysilicon similar to the first gate electrode 14b. The periphery of the gate electrode 17B is electrically connected to the back gate region 15 via the contact hole 19 and the metal wiring 20. Other configurations are the same as those of the first embodiment.

In the third embodiment, in the off state between the source region 12 and the drain region 13 in the FET, the FET is formed between the source region 12 and the back gate region 15 and between the drain region 13 and the back gate region 15. The gate electrode 17B operates to be turned off, thereby suppressing generation of a channel below these gate electrodes 17B. Therefore, the breakdown voltage between the source region 12 and the back gate region 15 and between the drain region 13 and the back gate region 15 are improved.
Other than that, it has substantially the same operation and effect as the first embodiment.

(Fourth Embodiment) FIG. 5 shows a fourth embodiment of the present invention.
FIG. 3 is a schematic plan view of a semiconductor device according to the first embodiment. This semiconductor device has a semiconductor substrate (for example, a P-type silicon substrate) 31 in which an N-type active region 32 with a large area and a P-type with a small area constituting a first transistor group are formed. Active area 33,3
4 are formed. The N-type active region 32 is maintained at the potential V1, and a plurality of first conductivity type FETs (for example, N-type FETs) are formed therein. In the vicinity of the N-type active region 32, P-type active regions 33 and 34 held at the ground potential GND are formed. A second transistor group is formed in the silicon substrate 31 at a predetermined distance from the first transistor group. The second transistor group includes an N-type active region 35 having a large area held at the potential V2, and a P-type active region 3 having a small area held at the ground potential GND.
6. In the N-type active region 35, a plurality of first conductivity type FETs (for example, N-type FETs) are formed.

In the silicon substrate 31 near the first and second transistor groups, a P-type active region 37 made of a P-type impurity layer maintained at a predetermined substrate potential (for example, ground potential GND) is formed. ing. Silicon substrate 31
A gate electrode 3 made of polysilicon or the like is provided on the upper side so as to cut off between the first transistor group and the second transistor group.
8 are formed. An insulating film such as phosphor silica (not shown) is formed on the entire surface of the gate electrode 38. A plurality of contact holes 39 are opened in the insulating film on the active region 37 and the like.
A metal wiring 40 of aluminum or the like is formed thereon. One end of the gate electrode 38 is electrically connected to the active region 37 via the metal wiring 40 and the contact hole 39. A passivation film (not shown) such as a nitride film is formed on the entire surface of the metal wiring 40.

In such a semiconductor device, a plurality of FETs formed in the active region 32 and a plurality of FETs formed in the active region 35 perform predetermined operations. At this time, the active region 32 is held at the potential V1, the active region 35 is held at the potential V2,
If there is a potential difference between the potentials V1 and V2, a channel may be formed between the active regions 32 and 35, and a leak current may flow. Therefore, in the fourth embodiment, the gate electrode 38 held at the ground potential GND is provided between the active regions 32 and 35.

For this reason, an FET is formed by the gate electrode 38 and the silicon substrate 31 on both sides of the gate electrode 38. The FET is turned off to suppress the generation of a channel, and a leakage current flowing between the active regions 32 and 35 is reduced. Will be shut off.
Therefore, the breakdown voltage between the active regions 32 and 35 is improved. Conversely, the breakdown voltage can be suppressed to a certain value, the distance between the first transistor group and the second transistor group can be reduced, and the size of the semiconductor device can be reduced. further,
Since the potential of the gate electrode 38 is connected to the active region 38 and held at the ground potential GND, the potential is constant regardless of the operating state of the first and second transistor groups, and as a result, the change in the breakdown voltage is small. This has the effect.

(Fifth Embodiment) FIG. 6 shows a fifth embodiment of the present invention.
FIG. 3 is a schematic plan view of a semiconductor device according to the first embodiment. This semiconductor device has a semiconductor substrate (for example, a P-type silicon substrate) 51, and an N-well 52 made of an N-type impurity layer is formed in the silicon substrate 51. In the N-well 52, a large-area P-type active region 53 constituting the first transistor group, and small-area N-type active regions 54 and 55 arranged near this are formed. The P-type active region 53 is maintained at the potential V1, and a plurality of first conductivity type FETs (for example, P-type FETs) are formed therein. This P-type active area 5
N-type active regions 54 and 55 arranged near 3
Are held at the power supply potential VDD. In the N well 52, a second transistor group is formed at a predetermined distance from the first transistor group. The second transistor group includes a plurality of first conductivity type FETs (for example, P-type FETs).
Are formed, a P-type active region 56 having a large area held at the potential V2 and a power supply potential V
N-type active region 5 with small area held in DD
7, 58.

In the vicinity of the first and second transistor groups in the N-well 52, an N-type active region 59 made of an N-type impurity layer held at a predetermined substrate potential (for example, power supply potential VDD) is formed. ing. On the N-well 52,
A gate electrode 60 made of polysilicon or the like is formed so as to cut off between the first transistor group and the second transistor group. An insulating film such as phosphor silica (not shown) is formed on the entire surface of the gate electrode 60. A plurality of contact holes 61 are formed in the insulating film on the active region 59 and the like, and a metal wiring 62 such as aluminum is formed on these contact holes 61. One end of the gate electrode 60 is electrically connected to the active region 59 via the metal wiring 62 and the contact hole 61.

In such a semiconductor device, a plurality of FETs formed in the active region 53 and a plurality of FETs formed in the active region 56 perform predetermined operations. At this time, if there is a potential difference between the potential V1 of the active region 53 and the potential V2 of the active region 56, a channel may be formed between these active regions 53 and 56, and a leak current may flow. Therefore, this fifth
In the embodiment, the gate electrode 60 held at the power supply potential VDD is provided between the active regions 53 and 56.

The gate electrode 60 and the N wells 52 on both sides of the gate electrode 60
Thus, an FET is formed, and this FET is turned off.
Therefore, the generation of a channel between the active regions 53 and 56 is suppressed, and the leakage current is cut off. Therefore, substantially the same effects as in the fourth embodiment can be obtained.

The present invention is not limited to the above embodiment, and the shape, structure, forming material, and manufacturing method of the FET and the semiconductor device can be changed to various types other than those shown.

[0045]

As described above in detail, according to the first aspect, all or a part of the offset region between the source region and the gate region and between the drain region and the gate region is removed.
Since the semiconductor device is covered with the second gate electrode held at the back gate potential, when the source region and the drain region are turned off, the second gate electrode held at the back gate potential causes an offset thereunder. The region is turned off, and channel generation can be suppressed. Therefore, the breakdown voltage between the source region and the gate region and between the drain region and the gate region is improved. Conversely, it is also possible to reduce the transistor size by reducing the breakdown voltage to a certain value, reducing the length of the offset region between the source region and the gate region, and the length of the offset region between the drain region and the gate region. . In addition, if the second gate electrode is formed simultaneously using, for example, the same material as the first gate electrode, there is no need to change or add a wafer process. Further, since the potential of the second gate electrode is connected to the back gate region and held at the back gate potential, the potential is constant regardless of the on / off state of the FET, and as a result, there is little change in the breakdown voltage.

According to the second aspect, all or a part of the offset region around the source region and the drain region is
Since the second gate electrode held at the back gate potential covers the semiconductor device, substantially the same effects as those of the first invention can be obtained. Further, since the offset region between the source region and the back region and between the drain region and the back gate region is covered by the second gate electrode, generation of a channel between the regions can be suppressed, and the withstand voltage can be further improved.

According to the third aspect, all or a part of the offset region between the source region and the back gate region and between the drain region and the back gate region is formed by the second gate electrode held at the back gate potential. Since the semiconductor device is covered, generation of a channel in the offset region between the source region and the back gate region and between the drain region and the back gate region can be suppressed, and the withstand voltage during this period can be improved. Further, substantially the same effects as those of the first invention can be obtained.

According to the fourth aspect, the gate electrode held at the substrate potential is formed on the semiconductor substrate between the first transistor group and the second transistor group. Channel generation between the second transistor group and the second transistor group can be suppressed, and leakage current can be cut off. Thereby, the breakdown voltage between the first and second transistor groups can be improved. Conversely, the breakdown voltage can be suppressed to a constant value, the length between the first and second transistor groups can be reduced, and the size of the semiconductor device can be reduced. Further, since the potential of the gate electrode is connected to the back gate region and held at the substrate potential, the potential is constant irrespective of the operation state of the first and second transistor groups, and as a result, the change in the breakdown voltage is small. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an offset gate type FET showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional offset gate type FET.

FIG. 3 is a configuration diagram of an offset gate type FET showing a second embodiment of the present invention.

FIG. 4 is a configuration diagram of an offset gate type FET showing a third embodiment of the present invention.

FIG. 5 is a schematic plan view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a schematic plan view of a semiconductor device according to a fifth embodiment of the present invention.

[Explanation of symbols]

 11, 31 N-type silicon substrate 12 Source region 13 Drain region 14 Gate region 14a Gate oxide film 14b First gate electrode 15 Back gate region 16 Offset region 16a P-type offset layer 16b Offset oxide film 17, 17A, 17B Second Gate electrode 19, 39, 61 Contact hole 20, 40, 62 Metal wiring 32, 35, 59 N-type active region 37, 53, 56 P-type active region 38, 60 Gate electrode 51 P-type silicon substrate 52 N-well

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 301L 301R F-term (Reference) 5F032 AC01 AC04 BA01 BA05 BA08 CA03 CA07 CA17 CA24 5F040 DA19 DC01 EB02 EB20 EC07 EC16 EC22 EC26 ED09 EF02 EH08 EJ08 EK02 EK07 EL06 FB02 5F048 AA01 AA05 AA07 AA09 AC01 AC03 BA01 BB05 BB16 BC03 BC05 BD00 BD04 BE03 BE09 BF03 BF15 BG12 BH07 BH09

Claims (4)

[Claims] A source region and a drain region formed of an impurity layer opposed to each other at a predetermined distance in a semiconductor substrate; and a source region and a drain region formed on a surface of the semiconductor substrate between the source region and the drain region. A gate insulating film, a gate region having a first gate electrode formed on the gate insulating film, and a ring in the semiconductor substrate surrounding the source region, the drain region and the gate region. A back gate region formed of an impurity layer formed in the semiconductor substrate between the source region, the drain region, the gate region, and the back gate region; An offset region having a low-concentration offset impurity layer and an offset insulating film formed on the offset impurity layer and having a thickness greater than that of the gate insulating film. And an area between the source area and the gate area, and between the drain area and the gate area so as to cover all or a part of the offset area, and is electrically connected to the back gate area. An offset gate type field effect transistor comprising: a second gate electrode formed by: 2. A source region, a drain region, a gate region, a back gate region, and an offset region according to claim 1, and all or a part of the offset region around the source region and the drain region. And a second gate electrode formed and electrically connected to the back gate region. 3. A source region, a drain region, a gate region, a back gate region, and an offset region according to claim 1, between the source region and the back gate region, and between the drain region and the back gate region. And a second gate electrode formed so as to cover all or a part of the offset region between them, and electrically connected to the back gate region. . 4. A first transistor group comprising a plurality of first conductivity type field effect transistors formed in a semiconductor substrate, and a plurality of transistors formed in the semiconductor substrate at a predetermined distance from the first transistor group. A second transistor group comprising a first conductivity type field effect transistor; and an active layer comprising an impurity layer formed in the semiconductor substrate near the first and second transistor groups and maintained at a predetermined substrate potential. A region, formed on the semiconductor substrate so as to cut off between the first transistor group and the second transistor group;
And a gate electrode electrically connected to the active region.