JP2001196475A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the deterioration of a gate oxide film due to threshold ion implantation damage in a semiconductor device incorporating a mask ROM that is composed by two kinds MOS transistors with high and low thresholds. SOLUTION: This semiconductor device contains a source and a drain that are formed on a semiconductor substrate, and a gate electrode that is formed via a gate insulation film on the semiconductor substrate, the end part of the gate electrode is separated from that of the drain, and the end part of the drain is not located under the gate electrode in a memory cell by a MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, particularly to a ROM (Read Only Memory) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices have become smaller and smaller.
Along with the sophistication, the storage capacity of a built-in ROM has increased, and it has become one of the important issues to reduce the area of a memory cell as a storage element.

Generally, a mask R using a contact hole
In the case of OM, the memory cell is M
Since an OS transistor, one contact hole on a diffusion layer provided in a semiconductor substrate or a diffusion layer region in which a contact hole is accommodated, and an isolation region for isolating the diffusion layer from other memory cells are required. In addition, there is a characteristic that the area of the memory cell is increased.

On the other hand, in a mask ROM using two kinds of high and low threshold values (for example, a low threshold value is about 0.6 V, and a high threshold value is 5 V or more), a predetermined threshold value using a word line as a gate is determined. Since a basic memory cell can be constituted only by a MOS transistor having the MOS transistor and a half of a contact hole shared with an adjacent memory cell, the area of the memory cell can be made smaller than that of a mask ROM using a contact hole. Has become mainstream.

[0005] In the following, high and low 2 which are conventionally used well are described.
LDD (Lig)
A method of manufacturing a semiconductor device having a built-in mask ROM constituted by an N-type MOS transistor having an (htly doped drain) structure will be described with reference to FIGS. FIG.
11 to 11 are cross-sectional views in the order of steps in a conventional method of manufacturing a semiconductor device, showing a transistor portion having two types of thresholds.

[0006] First, as shown in FIG.
An isolation oxide film 12 is formed thereon by a known LOCOS method or the like. Next, a P-type well 13 and a P-type channel region 14 for controlling a low threshold value are formed on the silicon substrate 11 by ion implantation using an ion implantation resist mask covering other portions of the semiconductor device.

Then, after forming a gate oxide film 15 by thermal oxidation and further forming a polysilicon film 16 by a CVD (Chemical Vapor deposition) method, the gate oxide film 15 and the polysilicon film 16 are formed by lithography and etching techniques as desired. It is formed in a gate electrode pattern.

Next, as shown in FIG. 7, by ion implantation using an ion implantation resist mask covering other portions of the semiconductor device, in each of the source / drain regions of the two transistors, a portion below the gate electrode is formed. An N-type low-concentration impurity layer 17 is formed so as to partially enter the semiconductor substrate region.

Next, as shown in FIG. 8, after a film for forming the sidewall oxide film 18 is formed on the entire surface so as to cover the polysilicon film 16 of the gate electrode by the CVD method, the polysilicon is formed by the etch back method. The sidewall oxide film 18 is left only on the side wall of the film 16. Then, as shown in FIG. 9, an N-type high-concentration impurity layer 19 is formed in the source / drain regions using an ion implantation resist mask covering other portions of the semiconductor device.

Next, as shown in FIG. 10, a pattern of a resist 20 is formed by a well-known lithography technique to open a portion having a polysilicon film 16 which is a gate electrode of a MOS transistor having a high threshold value.

Finally, as shown in FIG.
The P-type channel region 21 for controlling a high threshold is selected by implanting, for example, boron ions or the like into the P-type well surface region of the semiconductor substrate through the polysilicon film 16 and the gate oxide film 15 using the pattern of 0 as a mask. It is formed. Since the P-type channel region 21 has a higher P-type impurity concentration than the channel regions of other N-channel transistors, the P-type channel region 21 becomes a MOS transistor having a high threshold value. Through the above steps, two types of high and low threshold MOS
Transistors are formed and completed as a mask ROM.

Here, the size of the memory cell N-channel transistor of the completed mask ROM is, for example, about 7.2 μm in channel width and about 0.4 μm in gate length. FIG. 12 shows VG (gate voltage) -ID (drain current) characteristics of the low threshold MOS transistor, and FIG.
FIG. 13 shows the ID characteristics.

[0013] The VG when the drain current 10- ⁷ A to the threshold, lower threshold than 12 is 0.6V, the higher threshold than 13 has a 8.0V I understand.

[0014]

However, in the above-described conventional mask ROM manufacturing method, ions are implanted through a gate oxide film in order to control a high threshold value. Problems such as damage to the gate oxide film and a decrease in the intrinsic lifetime with respect to the breakdown voltage of the gate oxide film and an increase in the stoppage rate of accidental failures. was there.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can suppress the deterioration of the reliability of a gate oxide film even in a MOS transistor having a high threshold value in order to solve the above problems. I do.

[0016]

In order to achieve the above object, a semiconductor device according to the present invention comprises a source and a drain formed on a semiconductor substrate and a gate electrode formed on the semiconductor substrate via a gate insulating film. Wherein the memory cell is constituted by a MOS transistor in which the end of the gate electrode and the end of the drain are spaced apart from each other, and the end of the drain is not located below the gate electrode. .

[0017] With this configuration, since a structure in which the end of the gate electrode and the end of the drain are arranged apart from each other is used, a high threshold value can be realized, and in the manufacturing process, Since a process in which ion implantation through the gate oxide film is not performed can be performed, damage to the gate oxide film is eliminated, and deterioration in reliability of the gate oxide film can be suppressed.

The semiconductor device according to the present invention preferably further includes a sidewall formed on a side wall of the gate electrode, and an end of the drain is preferably located below the sidewall. This is because the source / drain can be arranged at the offset position by the sidewall.

Further, in the semiconductor device according to the present invention, the memory cell has a MOS transistor having a high threshold value and a second transistor having a low threshold value in which the source and drain ends are located below the gate electrode. And the MOS transistor of This is because the memory cell area can be made relatively small.

Next, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of: Forming an electrode;
Forming a sidewall on a side wall facing a semiconductor substrate region to be a drain of a gate electrode, and using a lower portion of the sidewall and a lower portion of the gate electrode as a channel region; and forming a channel on the semiconductor substrate using the gate electrode and the sidewall as a mask. Introduce impurities of the opposite conductivity type to the region,
Forming a source / drain.

With this configuration, a high threshold value can be realized without performing ion implantation through the gate oxide film, so that damage to the gate oxide film is eliminated and deterioration in reliability of the gate oxide film can be suppressed. Become.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
1 to 5 are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device having a built-in mask ROM constituted by N-type MOS transistors having two kinds of high and low threshold values according to the embodiment of the present invention.

Although the cross section of the actual mask ROM is a little more complicated, FIGS. 1 to 5 show two types of N-type MOS transistors having high and low threshold values, and a MOS transistor having one of high and low threshold values is used. Since the manufacturing process will be described with a focus on the memory cell portion including the N-type MOS transistors having two types of thresholds, they are displayed side by side for convenience of description.

First, as shown in FIG.
An isolation oxide film 2 for electrically isolating the elements is formed on the substrate by the well-known LOCOS method. Next, a P-type MO is formed on the silicon substrate 1.
An ion implantation mask, which is a resist pattern that covers an unnecessary portion such as an S transistor region and covers an unnecessary portion of the memory cell, is formed and ion implantation of, for example, boron or BF ₂ is performed using the mask as a different energy amount and dose. And the P-type well 3 and the P controlling the low threshold
Both of the mold channel regions 4 are formed independently. Then, a gate oxide film 5 is formed by thermal oxidation, a silicon film 6 is formed by a known CVD method, and then the gate oxide film 5 and the polysilicon film 6 are formed by lithography and etching techniques.
Is formed in a desired gate electrode pattern.

Next, as shown in FIG. 2, a resist 7 is formed by a well-known lithography technique so as to cover the left polysilicon film 6 serving as a gate electrode of a MOS transistor having a high threshold value.

Then, as shown in FIG. 3, an N-type low-concentration impurity layer 8 is formed by ion implantation of phosphorus or the like in a region to be a source / drain of the transistor by ion implantation. Here, in the MOS transistor having a low threshold value (right side), the N-type low-concentration impurity layer 8 is formed using the polysilicon film 6 serving as a gate electrode as a mask. Also, a part of the N-type low concentration impurity layer 8 enters. On the other hand, in a MOS transistor having a high threshold value, a resist serves as a mask, and an end portion of the polysilicon film 6 serving as a gate electrode and an end portion of the N-type low concentration impurity layer 8 have an offset structure.

Next, as shown in FIG. 4, after an oxide film is formed on the entire surface covering the gate electrode by a known CVD method,
By the etch back method, a sidewall oxide film 9 having a width of about 150 nm is left only on the side wall of the polysilicon film 6.

Finally, as shown in FIG. 5, the resist pattern covering a predetermined portion other than the memory cell is
By implanting ions such as s, an N-type high concentration impurity layer 10 is formed in the source / drain regions of both transistors with a junction depth of about 150 nm. As described above, a MOS transistor having two kinds of thresholds, high and low, is formed, and a mask ROM is completed.

As is clear from the transistor structure in the completed state, the transistor having a low threshold voltage has a source / drain arrangement composed of a normal N-type impurity layer. On the other hand, in the transistor having a high threshold value, the source / drain composed of the N-type high-concentration impurity layer 10 enters under the sidewall oxide film 9, but from the end of the gate electrode polysilicon 6. Is characterized in that the end of the N-type high-concentration impurity layer 10 is located at a position separated by a certain distance, that is, an offset arrangement. In the present embodiment, this offset length is about 80 nm.

With the arrangement of the source / drain regions having such an offset, when a positive voltage is applied to the gate electrode, the semiconductor substrate immediately below the gate electrode is inverted and a channel is formed. Since it is not connected to the source / drain N-type high-concentration impurity layer 10, no drain current flows. However, when the voltage is increased to some extent, the channel expands in the horizontal direction, so that a channel is formed from the end of the gate electrode to the source / drain N-type high-concentration impurity layer 10, and both are electrically connected. Current begins to flow. By forming the source / drain in the offset arrangement in this manner, a transistor having a high threshold value can be formed.

FIG. 14 shows an example of VG-ID characteristics of a high threshold transistor having the structure shown in this embodiment. In FIG 14, V at a drain current 10- ⁷ A
Assuming that G is the threshold value, the threshold value is as high as 10 V or more. As described above, according to the present embodiment, a transistor having a high threshold value can be realized without ion implantation into gate oxide film 5 by adopting the offset structure. There is no possibility of damaging the oxide film 5, and it is possible to prevent the reliability such as withstand voltage from deteriorating.

In this embodiment, the source /
The threshold value can be determined by forming the drains in an offset arrangement and selecting the formation conditions. Specifically, an arbitrary threshold value can be set by adjusting the offset distance between the end of the gate electrode and the end of the source / drain.

The offset distance can be determined by setting the thickness of the sidewall oxide film 9 and the lateral spread of the N-type high-concentration impurity layer 10. That is, the lateral spread of the N-type high-concentration impurity layer 10 depends on the heat treatment temperature and the impurity concentration of the P-type channel region 4 for controlling the low threshold value.

However, it is sufficient that the high threshold can be distinguished from the low threshold to identify the memory state, and there is no particular upper limit at that point if the value is higher than the power supply voltage used for the semiconductor device. Therefore, if the value is high to some extent, the threshold value control does not require much strictness.

In the present embodiment, the pattern end of the resist 7 is located on the source / drain region in the step of FIG. 2, but the resist 7 is extended to the isolation insulating film to extend the source / drain. The area may be covered. This is because the source / drain can be secured in the subsequent step of forming the N-type high concentration impurity layer 10.

As a semiconductor device on which a mask ROM is mounted, not only such a memory cell array, but also N-type MOS transistors constituting its peripheral circuits and a logic portion exist. In order to make the threshold value of the transistor having the low threshold voltage of the cell common to the threshold value of the transistor, the step of forming the P-type channel region 4 for controlling the low threshold value in the step shown in FIG. It is desirable to apply it simultaneously with the memory cell array in order to reduce the number of processes and to manufacture at low cost.

[0037]

As described above, according to the semiconductor device of the present invention, a high threshold value can be realized by forming the source / drain into an offset structure without performing ion implantation through the gate oxide film. And the high threshold M
OS transistor gate oxide film damage is eliminated,
This has the effect of suppressing the deterioration of the reliability of the gate oxide film.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps.

FIG. 2 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 3 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps.

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps.

FIG. 6 is a sectional view in the order of steps in a conventional method for manufacturing a semiconductor device.

FIG. 7 is a sectional view in the order of steps in a conventional method for manufacturing a semiconductor device.

FIG. 8 is a sectional view in the order of steps in a conventional method for manufacturing a semiconductor device.

FIG. 9 is a sectional view in the order of steps in a conventional method for manufacturing a semiconductor device.

FIG. 10 is a sectional view in the order of steps in a conventional method for manufacturing a semiconductor device.

FIG. 11 is a sectional view in the order of steps in a conventional method for manufacturing a semiconductor device.

FIG. 12 is a VG-ID characteristic diagram of a conventional transistor having a low threshold value.

FIG. 13 is a VG-ID characteristic diagram of a conventional transistor having a high threshold value.

FIG. 14 illustrates a VG-ID of a transistor having a high threshold value in a semiconductor device according to an embodiment of the present invention.
Illustration of characteristics

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 Silicon substrate 2, 12 Isolation oxide film 3, 13 P-type well 4, 14, 21 P-type channel region 5, 15 Gate oxide film 6, 16 Polysilicon film 7, 20 Resist 8, 17 N-type low concentration impurity Layer 9, 18 Side wall oxide film 10, 19 N-type high concentration impurity layer

Claims (4)

[Claims] 1. A semiconductor device comprising: a source and a drain formed on a semiconductor substrate; and a gate electrode formed on the semiconductor substrate via a gate insulating film, wherein an end of the gate electrode and an end of the drain are formed. A semiconductor device, wherein a memory cell is formed by MOS transistors that are spaced apart from each other, and an end of the drain is not located below the gate electrode. 2. The semiconductor device according to claim 1, further comprising a sidewall formed on a side wall of said gate electrode, wherein an end of said drain is located below said sidewall. 3. The MOS transistor in which the memory cell has a high threshold value, and a second MOS transistor in which an end of the source and the drain is located below the gate electrode and has a low threshold value. 2. The semiconductor device according to claim 1, comprising: 4. A step of forming a gate electrode made of a conductive film via a gate insulating film in a region where a memory cell of a ROM is to be formed on a semiconductor substrate, and the semiconductor substrate region to be a drain of the gate electrode Forming a sidewall on a side wall facing the semiconductor device, and using the lower portion of the sidewall and the lower portion of the gate electrode as a channel region; and using the gate electrode and the sidewall as a mask, opposing the channel region on the semiconductor substrate. Forming a source / drain by introducing a conductivity type impurity.