JPS6058739A - Phase converting system - Google Patents

Abstract

PURPOSE:To omit trouble of phase adjustment by allowing two signals to be converted automatically in the completely same phase when there is a phase difference up to maximum + or -0.5 bit in the two signals of the same phase transmitted by a digital data transmission system. CONSTITUTION:A write clock is frequency-divided to 1/2 by a frequency divider circuit 7, one clock divided by 1/2 is inputted to an FF8 and the other clock is inputted to an FF9. The clock obtained by inversion or non-inversion is inputted to a read AND circuit 15 and also inverted by an NOT circuit 13 and the inverted result is inputted to an AND circuit 14. While the clock inputted to the AND circuits 14, 15 is at H level, a data inputted to the AND circuits 14, 15 is read through an OR circuit 16, and an output phase locked to the read clock is obtained. Even if the input data and the write clock are shifted by + or -0.5 bit in this way, the same operation as above is performed and the two input data are phase locked automatically.

Description

Detailed Description of the Invention (al) Technical Field of the Invention The present invention provides a method for transmitting signals that are transmitted using a digital data transmission method and that can be used to transmit signals that are in the same phase when a phase difference of up to ±05 bits occurs due to a difference in cable length, etc. This invention relates to a phase conversion method that automatically converts signals into phase signals.

(bl) Prior art and problems When transmitting two signals of the same phase using the digital data transmission method to the other station, a phase difference occurs when the two signals are received by the other station due to the difference in cable length. When two signals of the same phase transmitted using a digital transmission method are sent back to a single partner station, the signals may be returned due to irregularities in the delay in the circuits of each partner station and differences in the cable lengths of the cables of each partner station. A phase difference occurs between the two signals.

Conventionally, the method described below has been used to bring the phase difference signals into the same phase.

FIG. 1 is a block diagram of a conventional phase conversion method.

In the figure, 1 is a transmitter, a 2-digit device, a 3- and 4-digit delay circuit,
5.5' is a data signal line, and 6.6' is a clock signal line of a clock synchronized with the data.

When transmitting device l transmits two pieces of data having the same phase and a clock data signal line 5', 5', and clock signal line 6.6' synchronized with each other, the data signal line 5
If the data signal line 5 and the clock signal line 6' are longer than the clock signal line 6, the signal will stop more slowly if it passes through the data signal line 5' and the clock signal line 6'. In this case, in order to make the phases of the data passing through the data signal lines 5 and 5' the same, the data and clock passing through the data signal line 5 and the clock signal line 6 are
The data signal line 5' is manually delayed to match the phase of the data and clock passing through the signal line 6' so that they are in phase.

For this reason, this method has the disadvantage that it is time-consuming and -
There is a drawback that the difference in cable delay caused by changes in temperature, etc., remains as an error.

(C) Purpose of the Invention In view of the above-mentioned drawbacks, the purpose of Xylophone 1 Mei is to provide a phase conversion method that can automatically transform signals into completely in-phase signals when a phase difference of up to ±05 bits occurs. .

(d) Structure of the Invention In order to achieve the above object, the present invention inputs a clock synchronized with an input signal to a frequency dividing circuit, and divides the clock frequency by 2 into 18
Data of the input signal is alternately written into two flip-flops using two-phase clocks with different lifespans of 0 degrees, - the read clock to synchronize the data of the universal signal is divided by two using a frequency divider circuit, 2 at the moment when the data of the input signal is input into one of the two flip-flops.
The frequency-divided read clock is inverted or not inverted depending on the phase state of the frequency-divided read clock, and the first frequency-divided read clock is passed through the inverting means or not. Two phase selection clocks having a phase difference of 180 degrees are obtained, and data stored in the two flip-flops is selectively outputted by the selection means using the two phase selection clocks, thereby synchronizing with the readout clock. This is a phase conversion method characterized by outputting input signal data.

3- (el　Example of the invention An embodiment of the present invention will be explained below according to the drawings.

FIG. 2 is a block diagram of a phase conversion circuit according to an example of the present invention.
The 1 dimension in FIG. 3 corresponds to the waveform timing of each part in FIG. 2.

In the figure, 7 and 11 frequency divider circuits, 8 to 10 are flip-flops (hereinafter referred to as F'F), 12 is an exclusive OR circuit (hereinafter referred to as EX-0'R), 13 is a not circuit, 14.15
1 is an AND circuit, and 16 is an OR circuit.

In step 21, the input data shown in Fig. 3, which is input to FFs 8 and 9, is output in phase synchronization with the readout clock shown in Fig. 3, which is input to the frequency dividing circuit 11. Synchronized data (% not shown) The input data shown in Figure 3 is phase-synchronized.The write clock shown in Figure 3 ωJ that is input to the frequency divider circuit 7 is connected to the input data 4 shown in Figure 3 (A). - Fully phase synchronized.

The operation of the circuit shown in FIG. 2 will be explained below.

The write clock shown in ) in FIG.
One of the clocks shown in FIG. 3 (C) K, which has been divided by two, is input to FF8, and the other clock shown in FIG. 3 (G) is input to FF9, and the clock shown in FIG. The third
The input signal data shown in Figure (4) is alternately input to FF8 and FF9.
write to. The data shown in this writing 11 and 3 (Di(F) are the AND circuit 15, 14 and the OR circuit 16, respectively).
and K are input to a selection circuit configured by K.

On the other hand, the read clock shown in FIG. Depending on the situation when the power is turned on, the third
The clock shown in Figure (Jl) or Figure 3 (J,)
It is uncertain whether the clock shown in <(J+) will be the inverted clock. This clock is input to FF10, and by reading it with the clock divided by 2 shown in 31st R1 (C1), it is possible to select the readout of FF8° and FF9 at the moment when the contents of FF8 are rewritten, rather than the output of FF10. The state of signal j is output. Therefore, Fig. 3 (Jt)
In the case of the clock shown in , H as shown in No. 31g1 (L)
In the case of the clock shown at No. 33121 (Jt), the level becomes <L level as shown in FIG. 3 (I,). When the H level is input to EX-0R12, the divided-by-2 clock shown in Figure 3 (J,) is inverted; The rotated clock is not inverted, and the output from the EX-OR 12 becomes the clock shown in Figure 3), and is controlled so that the contents of the FF 8 do not change during the readout period by the selection signal g. The clock obtained by inverting or non-inverting as described above is input to the read AND circuit 15 and is inverted by the NOT circuit 3 to become the clock shown in FIG. 3 and input to the AND circuit 14. While the clock shown in FIG. 3 (Foundation) input to the AND circuit 14.15 is at H level, the clock shown in FIG. 3 (F) is input to the AND circuit 14.15.
The data shown in O)) is outputted from the AND circuits 14 and 15, and then passed through the OR circuit 16 to obtain an output phase-synchronized with the read clock shown in FIG. 3, as shown in FIG. Therefore, the data shown in Figure 3 (including the DJ and C) As can be seen by comparing P) in Fig. 3 and the circle, even if the input data and write clock shown in Fig. 3 (4) 03) are shifted by ±0.5 bits, the same operation as above is performed, and the two inputs Data can be automatically phase-synchronized〇(f) Effects of the Invention As explained in detail above, according to the present invention, two signals of the same phase transmitted using a digital data transmission method can be synchronized at maximum ±
If a phase difference occurs up to the 05 bit, it can be automatically converted to completely the same phase, which has the effect of saving the effort of phase adjustment.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional phase conversion system, FIG. 2 is a block diagram of a phase conversion circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of waveforms of various parts in FIG. 7- In the figure, 1 is a transmitting device, a 2-digit receiving device, a 3- and 4-digit delay circuit,
5.5' is a data signal line, 6.6' is a clock signal line,
7.11 is a frequency divider circuit, 8~10Fi flip-flop,
12 is an exclusive OR circuit, 13 is a not circuit, 14.1
5 represents an AND circuit, and 16 represents an OR circuit. 8-

Claims (1)

[Claims] A clock synchronized with the input signal is input to the frequency divider circuit, and the data of the input signal is alternately written to two flip-flops using two phase clocks whose frequency is divided by 2 and whose phase is 180 degrees different from each other. , - The frequency of the power readout clock that synchronizes the data of the universal signal is divided by 2 using a frequency dividing circuit, and the frequency is divided by 2 at the moment when the data of the input signal is written into one of the above two flip-flops. The read clock frequency-divided by two is inverted or not depending on the phase state of the extracted derived clock. 2 with 180 degree phase difference
A phase selection clock is obtained, and the data stored in the two flip-flops is selectively outputted by the selection means using the two phase selection clocks, thereby outputting the data of the input signal synchronized with the readout clock. Characteristic phase conversion method.