JPS5952856B2 - Phase adjustment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase adjustment method for setting the phase delay amount of a digital signal between two or more points to a predetermined value using a delay circuit operated by high-speed pulses. It is something.

FIG. 1 shows an example of a conventional phase adjustment method.

The signal passes through a delay circuit 21, is modulated by a master station modulator 22, passes through a line 23, and is reproduced as data by a slave station demodulator 24. This signal is modulated again by the slave station modulator 25, passes through a line 26 having the same delay as the I line 23, and is sent to the master station demodulator 25.
It is demodulated by 7. The output of the demodulator 27 is sent to the delay circuit 2
It passes through a delay circuit 28 having the same delay amount as 1. The phase difference △φ (delay time △τ) between the two signals at the input part of the delay circuit 21 and the output part of the delay circuit 28 is measured by the phase difference measurement circuit 29, and the reference value Δφc (delay The delay amounts of the delay circuits 21 and 28 are changed until they match the time Δτc). If the line from the master station to the slave station and the line from the slave station to the master station are balanced, the delay phase to the slave station is △φc/2 (delay time △τc/2). Given. Circuit 30 and circuit 31 are high-speed clock pulse generation circuits for generating necessary high-speed clock pulses to operate delay circuits 21 and 28, respectively. Here, the high speed clock pulse needs to be synchronized with the delayed signal. An explanatory diagram of this is shown in FIG. FIG. 2a shows a specific example of a delay circuit, and FIG. 2b and c are time charts for explaining step a. 2 shows a case in which synchronization is achieved, and c in FIG. 2 shows a case in which synchronization is not achieved. In both cases, a shift register that operates at the rising edge of a high-speed clock Ch is used. In the case of , the delay is an integer multiple of τ1, but in the case of c, the initial delay is insufficient, so the overall delay is not an integer multiple of τ1. If the high-speed clock pulse of the circuit 30 is operated using a clock pulse created by frequency-dividing the high-speed clock pulse from the source of the signal S, the high-speed clock pulse of the circuit 30 will remain synchronized with the signal.
No special operation is required for synchronization, but circuit 3]
The high-speed clock pulse generating circuit of 2.0 requires a special operation for oscillating the high-speed clock pulse in synchronization with the output signal of the demodulator 27, and has the disadvantage of being complicated. When the number of slave stations increases, a high-speed clock synchronized with the signal sent from each slave station is required, which is disadvantageous in terms of cost efficiency. The purpose of the present invention is to eliminate these drawbacks by adjusting the phase between the master station and the slave station without the need for a high-speed clock pulse train that is sent back from the slave station and synchronized with the signal. This provides a phase adjustment method that provides

The present invention will be explained in detail below.

FIG. 3 shows a specific embodiment of the present invention.

The signal is modulated by a modulator 42 on the master station side through a delay circuit 41, and reproduced as data by a demodulator 44 on the slave station side through a line 43. This signal passes through a line 46 modulated by a slave station modulator 45, and then passes through a master station demodulator 4.
7 is demodulated as data. The circuit 48 is a delay circuit for delaying the signal sent from the master station side to the slave station side. Set. Circuit 50 is a high speed clock pulse generation circuit for operating delay circuits 41 and 48. Here, the delay amount in the delay circuit 48 is set to decrease by the same value Δτ. This means that, for example, if one stage of shift register is added to the delay circuit 41, the delay circuit 48 only needs to have one stage. Now the third
Regarding the figure, if the delay time of the signal from the input of the modulator 42 to the output of the demodulator 44 is τx, the delay time from the modulator 45 to the output of the demodulator 47 is the modulator 42 and 45 lines 43 and 46 demodulator If 44 and 47 are similar, it becomes τx. Here, the delay amount of the delay circuit 41 is △
Let τ be the delay amount of the delay circuit 48 as τMax−Δτ.
τMax is the maximum delay amount of the delay circuit 48.

The delay circuits 41 and 4 are configured such that the difference between the signal delay from the input of the delay circuit 41 to the output of the demodulator 47 and the signal delay from the output of the delay circuit 48 matches the reference value ΔτC.
If △τ is adjusted in 8, then △τ+2τx−(
τMax−△τ)=△τC Therefore, the signal delay time τh from the input of the master station delay circuit 41 to the output of the slave station demodulator 44 is τh=△τ+τx=(τMax+△τC)
/2, it becomes a fixed value determined only by the maximum delay amount τMax of the delay circuit 48 and the reference delay amount ΔτC. FIG. 4 shows a second embodiment of the invention. In FIG. 3, the signal passed to the circuit 48 is synchronized with the signal passed to the circuit 41, and in the phase difference measuring circuit 49, the amount of delay of the signal from the input of the circuit 41 to the output of the circuit 47, and the amount of delay of the signal passed to the circuit 41 are measured. The signal pattern does not have to be the same as that passed to the circuit 41, as long as the difference between the signal delay amount and the signal delay amount of 48 can be measured. For example, as shown in FIG. 4, a signal S from the master station is passed through a first delay circuit 71, modulated by a modulator 72, passed through a line 73, demodulated by a demodulator 74, and modulated again. The phase difference measurement circuit 7
Enter into 9.

On the other hand, the signal S is subjected to pattern matching by a pattern matching circuit 81. Here, "circuit 8" is configured to output a low level only when a pattern match is achieved. The output of the circuit 81 is passed to the delay circuit 78, and the output of the delay circuit 78 is input to the phase difference measuring section 79. Since the signal S at the input of circuit 71 and the output signal of pattern match circuit 81 are synchronized, the same high speed clock pulse can be used to operate delay circuits 71 and 78. Phase difference measurement circuit 7
9 is provided with a pattern matching circuit 82 which is the same as the circuit 81, and the output of the circuit 82 is set to be low level only when a pattern match is achieved. The circuit 83 is a phase difference measuring circuit that displays the time difference between two signals instantaneously showing a low level as an angle. As described above, in the case of FIG. 4, just as in the case of the specific example of the present invention in FIG. 3, phase adjustment between the master station and the slave station can be performed using only one high-speed tarlock pulse generation circuit.

As explained above, according to the present invention, since the same signal is passed through the delay circuits 41 and 48, there is only one high-speed clock pulse generation circuit that is synchronized with the signal even if there are many slave stations. It has the advantage of being nice to have.

[Brief explanation of the drawing]

Figure 1 shows a specific example of a conventional phase adjustment method. Figure 2 shows a specific example of a delay circuit and a time chart of the high-speed clock pulse for operating the delay circuit and the delay circuit input signal. be. Figure 3 shows the first embodiment of the present invention.
Embodiment of FIG. 4 A second embodiment of the present invention. 21, 28,
41, 48, 71, 78: Delay circuit, 22, 42, 72
: Master station side modulator, 23, 26, 43, 46, 73, 76
: Line line, 24, 44, 74: Slave side demodulator, 25
, 45, 75: slave station side modulator, 27, 47, 77: master station side demodulator, 29, 49, 79, 83: phase difference measurement circuit,
30, 31, 50, 80: high-speed pulse generation circuit, 81,
82 pattern match circuit.

Claims (1)

[Claims] 1. In a signal transmission system between distant points, a first delay circuit is provided at a first point, a signal passing through the first delay circuit is sent to a second point, and a signal received at the second point is transmitted. a signal sent back to a first point, and at the first point, sent through the first delay circuit to a second point;
For the signal synchronized with the signal sent to the second point through the delay circuit, the delay amount is reduced from the predetermined delay amount by the same value as the delay amount inserted in the first delay circuit. the output of the second delay circuit and the signal sent back from the second point is measured, and the phase measurement result is a certain determined value. A phase adjustment method characterized in that the signal delay time at the first point and the second point is adjusted by simultaneously changing the delay amounts of the first and second delay circuits.