JPS5810900B2 - Isou Saisei Gohoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase readjustment method for a facsimile receiver employing an independent synchronization method.

The main synchronization methods for facsimile transmission are power synchronization and independent synchronization, but the independent synchronization method is generally used for transmission between areas where the power frequency is 50Hz and 60Hz, or between areas with poor power supply conditions. It is true.

Since the oscillation source of the independent synchronization method requires high precision stability, a crystal oscillator is generally used, but in actual facsimile receivers, the oscillator is 1×10-5/d due to cost considerations.
It is common to use a crystal oscillator with stability on the order of ay.

Therefore, it cannot be said that there is no difference in the oscillation frequency between the transmitter and the receiver, so that a so-called synchronous flow appears on the receiving surface during long-term continuous operation.

If this state continues, the image surface will protrude from the recording paper and become unreadable.

Moreover, if synchronization is re-established in the middle of the synchronization process to avoid this problem, the screen will be temporarily divided at that point, which is not preferable.

Therefore, the present invention proposes a phase re-alignment method for facsimile receivers that can always reproduce an image without synchronization on recording paper without dividing the screen by performing phase re-alignment on each blank area of the screen, such as the margin between lines. provide.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of main parts showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes a NAND circuit having two inputs: a transmission phase signal A1 (periodic pulse signal in the transmission signal A in FIG. 2) and a reception phase signal B of the same period, which is uniquely generated on the reception side; is a counter circuit that counts the clock signal CP while the NAND circuit 1 output is present (while signals A1 and B match), 3 is a retriggerable monomulti that is triggered by the counter circuit 2 output, and 4 is a retriggerable This is an R-S flip-flop that is reset at the output change point of the monomulti 3 and set by the transmission phase signal A1.

These NAND circuit 1, counter circuit 2, retriggerable monomulti 3, and R-S flip-flop 4 constitute a phase matching circuit, and while gated by the NAND circuit 1 output, a clock signal CP of a certain level or more is output. When the counter circuit 2 counts, the retriggerable monomulti 3 operates, and the R-S flip-flop 4, which is reset at the output change point, is set by the transmission phase signal A1, thereby matching (
period) state, and a phase matching signal H is sent out.

On the other hand, the other circuit portions constitute a phase readjustment circuit that operates the phase matching circuit again when the image signal A2 is not present in successive failed scan lines of the transmission signal A.

In other words, this phase re-matching circuit is reset by the NAND circuit 5 which handles the transmission signal A and the blanking signal C by two people, and the output D of the NAND circuit 5 (signal corresponding to the image signal A2 of the transmission signal A), and the reception phase an n-line detection circuit 6 that counts the signal B; an R-S flip-flop γ that is reset by the output of the n-line detection circuit 6 that counts a set value of n (for example, n=3) and is set by the signal; The reset pulse generation circuit 8 generates the reset pulse E at the falling edge of the blanking signal C, and the reset pulse E is generated only while being gated by the output F of the R-S flip-flop 7.
The NAND circuit 9 passes through the R-S flip-flop 10 which is reset by the signal and set by the NAND circuit 9 output G, and the output of the R-S flip-flop 10 is differentiated and sent to the reset terminal of the R-S flip-flop 4. It consists of a differentiating circuit 11 for guiding.

The operation of the circuit of the above configuration will be explained with reference to the time chart of FIG.

As mentioned above, when the received transmission signal A is guided to the NAND circuit 5 with the initial phase matching already completed and the R-S flip-flop 4 set, the state of the image signal A2 of the transmission signal A is changed. The n-line detection circuit 6 is reset by a signal corresponding to .

Here, as mentioned above, n of the n line detection circuit 6 is set to "3".
When set to , the n-line detection circuit 6 sends an output and resets the R-S flip-flop 7 when the reception phase signal B having the same period as the transmission phase signal A1 is counted three times in succession.

The R-S flip-flop 7 is set by a signal corresponding to the image signal A2.

On the other hand, a reset pulse E from the reset pulse generation circuit 8 is also generated for each scan.
can pass through the NAND circuit 9 during the period when the R-S flip-flop 7 is reset and the signal F is generated.

Therefore, when the signal G is sent out from the NAND circuit 9, the preceding three consecutive scanning periods (between four consecutive transmission phase signals) L1. L2. This means that the image signal A2 was not present in L3.

Strictly speaking, it is just before the final transmission phase signal A1 (the transmission phase signal immediately after the scanning period L3), and the space between this final transmission phase signal A1 and the preceding signal G is blanked by the signal C.

Therefore, when the signal G is generated, the R-S flip-flop 10 is set, and its changing point is detected by the differentiating circuit 11, so that the R-S flip-flop of the phase matching circuit that was in the set state is detected.
Flip-flop 4 is reset.

Then, it is set again and realigned with the transmission phase signal A1 (the aforementioned final transmission phase signal) that arrives immediately after that.

The above-mentioned change in the output H of the R-S flip-flop 4 (reset → set) indicates that the phase between the transmitter and the receiver has been realigned, but if the transmitted document is a text, this operation will occur in the blank space between the lines. Since this is reliably carried out, realignment is carried out for each margin even during long-term continuous operation, and it is possible to prevent illegibility due to synchronization deviation.

Furthermore, since the phase realignment position is a blank area where there is no image signal, there is no possibility of division in the received image.

Furthermore, due to the relationship between the margin area and the setting value of n, if the R-S flip-flop 7 is not set even after re-alignment is performed (if the image signal A2 does not arrive), multiple signals G are sent in succession. occurs, and each time the R-S flip-flop 4
To avoid this, once the R-S flip-flop 10 is set with the signal G, the image signal A is activated again.
This state is maintained until 2 arrives, and the realignment is performed only once at each margin.

In addition, if there are frames surrounding text in the transmitted manuscript, the frames will be detected at both ends between each line, and will be identified as if the manuscript surface had no margins, and realignment will be performed between the lines. do not have.

In such a case, an N-line detection circuit for emptying detection is provided separately, and the output of this N-line detection circuit is sent to the n-line detection circuit 6.
The above-mentioned problem can be solved by guiding the signal to the reset terminal of

As described above, according to the phase re-alignment method of the present invention, which re-aligns the phase when the absence of image signals is detected in consecutive multiple scanning periods, such as between each line of text, an independent synchronization method is adopted. When a facsimile receiver is operated continuously for a long period of time, it is possible to faithfully reproduce the transmitted image without causing synchronization or division of the received image.

It should be noted that the present invention is not limited to the above-mentioned embodiment in which n=3, and can be implemented by setting n arbitrarily and by variously modifying the circuit configuration.

[Brief Description of the Drawings] Fig. 1 is a block diagram of main parts showing one embodiment of the present invention, Fig. 2 is a block diagram of main parts showing an embodiment of the present invention;
The figures are signal waveform diagrams of various parts used to explain the above embodiment. 1.5, 9... NAND circuit, 2... Counter circuit, 3... Retriggerable mono multi,
4,7゜10...R-S flip-flop, 6
. . . N line detection circuit, 8 . . . Reset pulse generation circuit, 11 . . . Differential circuit.

Claims (1)

[Claims] 1. A first means for identifying a transmission phase signal from a received facsimile signal and determining whether or not there is an image signal between each transmission phase signal; a second means for performing phase realignment using a final transmission phase signal when detecting that there is no image signal in the image signal;
After the phase realignment is performed by the second means, the second means continues until the image signal is detected again by the first means.
and third means for rendering the means inoperative.