JPS605588Y2 - Protection device for insulated gate type semiconductor devices - Google Patents

Protection device for insulated gate type semiconductor devices

Info

Publication number
JPS605588Y2
JPS605588Y2 JP1978019543U JP1954378U JPS605588Y2 JP S605588 Y2 JPS605588 Y2 JP S605588Y2 JP 1978019543 U JP1978019543 U JP 1978019543U JP 1954378 U JP1954378 U JP 1954378U JP S605588 Y2 JPS605588 Y2 JP S605588Y2
Authority
JP
Japan
Prior art keywords
electrode
insulated gate
protection device
oxide film
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1978019543U
Other languages
Japanese (ja)
Other versions
JPS54122774U (en
Inventor
靖祐 今井
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1978019543U priority Critical patent/JPS605588Y2/en
Publication of JPS54122774U publication Critical patent/JPS54122774U/ja
Application granted granted Critical
Publication of JPS605588Y2 publication Critical patent/JPS605588Y2/en
Expired legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【考案の詳細な説明】 本考案は絶縁ゲート型半導体装置の保護装置の改良に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a protection device for an insulated gate type semiconductor device.

第1図に従来の絶縁ゲート型半導体装置の保護装置の上
面図を本腰第2図に第1図の■−■線断面図を示す。
FIG. 1 shows a top view of a conventional protection device for an insulated gate type semiconductor device, and FIG. 2 shows a cross-sectional view taken along the line ■--■ in FIG.

この保護装置はN型のシリコン基板1にP型の拡散抵抗
領域2を形威し、その一端を入力端子電極3に接続しそ
の他端を基板1に形威された絶縁ゲート型半導体装置(
図示せず)のゲート電極に接続され、また抵抗領域2に
突出した舌片4を形威して舌片4と基板1とで形威され
るPN接合上の酸化膜5をフィールド酸化膜6より薄く
しこの酸化膜5上を蒸着アルミニウムの電極7で被覆し
且つ電極7を接地電位にして電極7下のPN接合耐圧を
絶縁ゲート型半導体装置のゲート酸化膜破壊電圧より低
くして絶縁ゲート型半導体装置を静電破壊から保護して
いた。
This protection device is an insulated gate type semiconductor device (
The oxide film 5 on the PN junction formed by the tongue 4 and the substrate 1 is connected to the field oxide film 6 by forming the tongue 4 which is connected to the gate electrode (not shown) and protruding into the resistance region 2. The oxide film 5 is made thinner, the oxide film 5 is covered with an electrode 7 made of vapor-deposited aluminum, and the electrode 7 is grounded to make the PN junction breakdown voltage below the electrode 7 lower than the gate oxide film breakdown voltage of an insulated gate type semiconductor device to form an insulated gate. This protects type semiconductor devices from electrostatic damage.

第3図にこの等価回路図を示す。FIG. 3 shows this equivalent circuit diagram.

第3図に於いてD□は拡散抵抗領域2と基板1とで形成
されるダイオードであり、Rは拡散抵抗領域2の約水Ω
程度の抵抗であり、D2は舌片4と基板1とで形威され
る耐圧の低いダイオードである。
In FIG. 3, D□ is a diode formed by the diffused resistance region 2 and the substrate 1, and R is the approximately water Ω of the diffused resistance region 2.
D2 is a diode with a low breakdown voltage formed by the tongue piece 4 and the substrate 1.

斯る保護装置に於いて入力端子電極3にダイオードD□
を順方向バイアスする高い正の静電気たとえば+100
V程度が印加されると基板1も+100V程度に持ち上
げられ、ダイオードD2を形威している部分薄い酸化膜
5下の基板1も+100V程度となり薄い酸化膜5には
+100V程度印加されて絶縁破壊してしまう欠点があ
った。
In such a protection device, a diode D□ is connected to the input terminal electrode 3.
For example, +100
When about V is applied, the substrate 1 is also lifted to about +100V, and the substrate 1 under the thin oxide film 5 forming the diode D2 also becomes about +100V, and about +100V is applied to the thin oxide film 5, causing dielectric breakdown. There was a drawback to it.

本考案は斯る欠点に鑑みてなされ、従来の欠点を完全に
除去した絶縁ゲート型半導体装置の保護装置を提供する
ものである。
The present invention has been devised in view of these drawbacks and provides a protection device for an insulated gate type semiconductor device that completely eliminates the conventional drawbacks.

以下第4図乃至第6図を参照して本考案の一実施例を詳
述する。
An embodiment of the present invention will be described in detail below with reference to FIGS. 4 to 6.

本考案に依る保護装置は第4図および第5図に示す如く
、N型のシリコン半導体基板11にP型の拡散抵抗領域
12を設け、その一端に入力端子電極13を接続しその
他端に基板11に形威された絶縁ゲート型半導体装置(
図示せず)のゲート電極を接続し、拡散抵抗領域12か
ら突出した舌片14を形威し、この舌片14に近接して
舌片14を囲むようにP型の保護拡散領域15を設け、
舌片14と保護拡散領域15で挾まれた基板11上およ
び互いに対向した舌片14と保護拡散領域15のPN接
合上の酸化膜16をフィールド酸化膜17より薄く形成
腰この酸化膜16上を電極18で被覆して前述した対向
する舌片14と保護拡散領域15のPN接合耐圧を低く
し且つ電極18と保護拡散領域15とを接続して構成さ
れる。
As shown in FIGS. 4 and 5, the protection device according to the present invention is provided with a P-type diffused resistance region 12 on an N-type silicon semiconductor substrate 11, an input terminal electrode 13 is connected to one end of the region, and the substrate is connected to the other end of the P-type diffused resistance region 12. Insulated gate semiconductor device (
A gate electrode (not shown) is connected to the gate electrode, a tongue piece 14 protruding from the diffusion resistance region 12 is formed, and a P-type protective diffusion region 15 is provided close to this tongue piece 14 so as to surround the tongue piece 14. ,
The oxide film 16 is formed to be thinner than the field oxide film 17 on the substrate 11 sandwiched between the tongue piece 14 and the protective diffusion region 15 and on the PN junction between the tongue piece 14 and the protective diffusion region 15 facing each other. The electrode 18 is coated with the electrode 18 to lower the PN junction breakdown voltage between the opposing tongue piece 14 and the protective diffusion region 15, and the electrode 18 and the protective diffusion region 15 are connected.

願主の構成の保護装置の等価回路を第6図に示す。FIG. 6 shows an equivalent circuit of the protection device constructed by the applicant.

D□は拡散抵抗領域12と基板11とで形成されるダイ
オードであり第3図のD□と同一のものである。
D□ is a diode formed by the diffused resistance region 12 and the substrate 11, and is the same as D□ in FIG.

Rは第3図に同様に拡散抵抗領域12の約2にΩ程の抵
抗である。
Similarly to FIG. 3, R is a resistance of about 2 Ω of the diffused resistance region 12.

Tは基板11舌片14保護拡散領域15および電極18
で形成される保護用のMOS トランジスタである。
T represents the substrate 11 tongue 14 protective diffusion region 15 and electrode 18
This is a protection MOS transistor formed by.

願主した本考案に依る保護装置は入力端子電極13にた
とえば+100V程度の高い静電気が印加されると前述
した如く基板11も+100V程度に持ち上げられるが
、保護拡散領域15の舌片14に対向したPN接合耐圧
は電極18により薄い酸化膜16の絶縁破壊電圧以下た
とえば40Vになっており、基板11の+100V程度
の静電気は上述した保護拡散領域15の低耐圧のPN接
合を通つて保護拡散領域15から電極18に印加される
ため電極18と基板11とは同電位となり薄い酸化膜1
6は絶縁破壊から保護される。
In the protection device according to the present invention proposed by the applicant, when high static electricity of, for example, about +100V is applied to the input terminal electrode 13, the substrate 11 is also lifted to about +100V as described above. The junction breakdown voltage is, for example, 40V below the dielectric breakdown voltage of the thin oxide film 16 due to the electrode 18, and static electricity of about +100V on the substrate 11 is transferred from the protection diffusion region 15 through the low breakdown voltage PN junction of the protection diffusion region 15 mentioned above. Since the voltage is applied to the electrode 18, the electrode 18 and the substrate 11 have the same potential, and the thin oxide film 1
6 is protected from dielectric breakdown.

以上に詳述した如く本考案に依れば基板に印加される高
い静電気を接合耐圧を低く設定した保護拡散領域から電
極に導き薄い酸化膜の両端と等電位とするために従来よ
り高い電圧の静電気等に対して保護ができる様になり、
より完全な保護装置が実現できる。
As detailed above, according to the present invention, a voltage higher than that of the conventional method is applied in order to guide the high static electricity applied to the substrate from the protective diffusion region with a low junction breakdown voltage to the electrode and make it equal potential with both ends of the thin oxide film. Provides protection against static electricity, etc.
A more complete protection device can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を説明する上面図、第2図は第1図の■
−■線断面図、第3図は従来例の等価回路図、第4図は
本考案を説明する上面図、第5図は第4図の■−■線断
面図、第6図は本考案の等価回路図である。 11は半導体基板、12は拡散抵抗領域、13は入力端
子電極、14は舌片、15は拡散保護領域、16は薄い
酸化膜、17はフィールド酸化膜、18は電極である。
Figure 1 is a top view explaining the conventional example, and Figure 2 is the same as in Figure 1.
-■ line sectional view, Figure 3 is an equivalent circuit diagram of the conventional example, Figure 4 is a top view explaining the present invention, Figure 5 is a ■-■ line sectional view of Figure 4, and Figure 6 is the present invention. FIG. 11 is a semiconductor substrate, 12 is a diffused resistance region, 13 is an input terminal electrode, 14 is a tongue piece, 15 is a diffusion protection region, 16 is a thin oxide film, 17 is a field oxide film, and 18 is an electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一端を入力端子電極に他端を絶縁ゲート型半導体装置の
ゲート電極に接続された一導電型の拡散抵抗領域を設け
、該抵抗領域に舌片を形威し、該舌片に近接して一導電
型の保護拡散領域を形威し、前記舌片と保護拡散領域間
の酸化膜を薄くして該酸化膜上を電極で被覆し且つ該電
極を前記保護拡散領域と接続して成る絶縁ゲート型半導
体装置の保護装置。
A diffused resistance region of one conductivity type is provided, one end of which is connected to an input terminal electrode and the other end of which is connected to a gate electrode of an insulated gate semiconductor device, a tongue piece is formed in the resistance region, and a tongue piece is formed adjacent to the tongue piece. an insulated gate formed by forming a conductive type protective diffusion region, thinning an oxide film between the tongue and the protective diffusion region, covering the oxide film with an electrode, and connecting the electrode to the protective diffusion region; protection device for type semiconductor devices.
JP1978019543U 1978-02-15 1978-02-15 Protection device for insulated gate type semiconductor devices Expired JPS605588Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1978019543U JPS605588Y2 (en) 1978-02-15 1978-02-15 Protection device for insulated gate type semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1978019543U JPS605588Y2 (en) 1978-02-15 1978-02-15 Protection device for insulated gate type semiconductor devices

Publications (2)

Publication Number Publication Date
JPS54122774U JPS54122774U (en) 1979-08-28
JPS605588Y2 true JPS605588Y2 (en) 1985-02-21

Family

ID=28848843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1978019543U Expired JPS605588Y2 (en) 1978-02-15 1978-02-15 Protection device for insulated gate type semiconductor devices

Country Status (1)

Country Link
JP (1) JPS605588Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577950A (en) * 1980-06-19 1982-01-16 Toshiba Corp Semiconductor integrated circuit device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673427A (en) * 1970-02-02 1972-06-27 Electronic Arrays Input circuit structure for mos integrated circuits
JPS512527U (en) * 1974-06-24 1976-01-09

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673427A (en) * 1970-02-02 1972-06-27 Electronic Arrays Input circuit structure for mos integrated circuits
JPS512527U (en) * 1974-06-24 1976-01-09

Also Published As

Publication number Publication date
JPS54122774U (en) 1979-08-28

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