JPH0693496B2 - Transistor protector - Google Patents
Transistor protectorInfo
- Publication number
- JPH0693496B2 JPH0693496B2 JP61034728A JP3472886A JPH0693496B2 JP H0693496 B2 JPH0693496 B2 JP H0693496B2 JP 61034728 A JP61034728 A JP 61034728A JP 3472886 A JP3472886 A JP 3472886A JP H0693496 B2 JPH0693496 B2 JP H0693496B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- transistor
- resistor
- conductive region
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、相補型MOSトランジスタなどのトランジス
タの保護装置に係り、特に、トランジスタの静電破壊強
度の向上に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection device for a transistor such as a complementary MOS transistor, and more particularly, to improvement in electrostatic breakdown strength of the transistor.
従来、相補型MOSトランジスタ回路は、第５図に示すよ
うに、ＰチャネルエンハンスメントMOS電界効果トラン
ジスタ（以下PchMOSFETという）２と、Ｎチャネルエン
ハンスメントMOS電界効果トランジスタ（以下NchMOSFET
という）４を直接に接続するとともに、各PchMOSFET2お
よびNchMOSFET4の共通にしたゲートに対して抵抗６を介
してゲート入力端子（ピン）８が形成され、また、PchM
OSFET2とNchMOSFET4の接続点には出力端子10が形成され
ている。なお、抵抗６はたとえば、ポリシリコンからな
る高抵抗で構成される。Conventionally, as shown in FIG. 5, a complementary MOS transistor circuit has a P-channel enhancement MOS field effect transistor (hereinafter referred to as PchMOSFET) 2 and an N-channel enhancement MOS field effect transistor (hereinafter referred to as NchMOSFET).
4) is directly connected, and a gate input terminal (pin) 8 is formed through a resistor 6 to the common gate of each Pch MOSFET 2 and Nch MOSFET 4, and PchM
An output terminal 10 is formed at the connection point between the OSFET 2 and the Nch MOSFET 4. The resistor 6 is composed of, for example, a high resistance made of polysilicon.
そして、ゲート入力端子８に加わる数kVの高電圧の静電
気による破壊からPchMOSFET2およびNchMOSFET4を保護す
るため、PchMOSFET2のゲート・ソース間には、ゲート側
をアノードにしてダイオード12が挿入され、また、NchM
OSFET4のゲート・ソース間にも、ゲート側をカソードに
してダイオード14が挿入されている。Then, in order to protect the Pch MOSFET 2 and the Nch MOSFET 4 from being destroyed by static electricity of a high voltage of several kV applied to the gate input terminal 8, a diode 12 is inserted between the gate and the source of the Pch MOSFET 2 with the gate side as an anode, and NchM
The diode 14 is also inserted between the gate and the source of the OSFET 4 with the gate side as the cathode.
このような相補型MOSトランジスタ回路において、ゲー
ト入力部の構造は、第６図に示すように、シリコンなど
からなる半導体基板16の表面層にシリコン酸化膜などの
絶縁膜18を設置し、この絶縁膜18の表面に選択的にポリ
シリコン層からなる抵抗６を形成し、この抵抗６の表面
を覆うシリコン酸化膜などの絶縁膜20を形成した後、抵
抗６の表面を覆う絶縁膜20に選択的に開口22、24を形成
して配線導体26、28を設置している。そして、蒸着によ
って設置された配線導体26、28の表面にはパッシベーシ
ョンを目的とした絶縁膜30が形成され、絶縁膜30に開口
を設けて露出させた配線導体26に対して、ゲート入力端
子８を構成するリードワイヤがボンディングされてい
る。In such a complementary MOS transistor circuit, as shown in FIG. 6, the gate input portion has a structure in which an insulating film 18 such as a silicon oxide film is provided on the surface layer of a semiconductor substrate 16 made of silicon or the like, A resistor 6 made of a polysilicon layer is selectively formed on the surface of the film 18, an insulating film 20 such as a silicon oxide film covering the surface of the resistor 6 is formed, and then the insulating film 20 covering the surface of the resistor 6 is selected. Specifically, the openings 22 and 24 are formed and the wiring conductors 26 and 28 are installed. An insulating film 30 for the purpose of passivation is formed on the surfaces of the wiring conductors 26, 28 provided by vapor deposition, and the gate input terminal 8 is provided for the wiring conductor 26 exposed by forming an opening in the insulating film 30. Is bonded to the lead wire.
ところで、このような相補型MOSトランジスタ回路の耐
圧Vdは、抵抗６を構成するポリシリコン層と、半導体基
板16との間におけるシリコン酸化膜などからなる絶縁膜
18の膜厚によって決定されるが、通常、絶縁膜18は薄
く、大きな静電破壊強度は期待できない。By the way, the withstand voltage Vd of such a complementary MOS transistor circuit is determined by an insulating film such as a silicon oxide film between the polysilicon layer forming the resistor 6 and the semiconductor substrate 16.
Although it is determined by the film thickness of 18, the insulating film 18 is usually thin and large electrostatic breakdown strength cannot be expected.
そこで、この発明は、このような相補型MOSトランジス
タなどの各種のトランジスタの静電破壊強度を向上させ
たトランジスタの保護装置の提供を目的とする。Therefore, an object of the present invention is to provide a transistor protection device in which the electrostatic breakdown strength of various transistors such as the complementary MOS transistor is improved.
この発明のトランジスタの保護装置は、第１図に例示す
るように、半導体基板（16）の表面層に絶縁層（絶縁膜
18）を設置し、この絶縁層上にトランジスタのゲートに
接続される抵抗体（抵抗６）を設置するとともに、この
抵抗体に接続される配線導体（26）を設置し、この配線
導体上に接続した端子部（ゲート入力端子８）を備えた
トランジスタ（例えばPchMOSFET2、NchMOSFET4）の保護
装置であって、前記端子部を接続すべき前記配線導体の
下層側の前記半導体基板の表面層に前記半導体基板と反
対導電型の導電領域（32）を設置し、前記端子部と前記
半導体基板との間に、前記導電領域と前記端子部との間
の前記絶縁層による第１のキャパシタ（C1）と、前記導
電領域と前記半導体基板とのPN接合領域（34又は38）に
よる第２のキャパシタ（CPN）とを直列に挿入させたこ
とを特徴とする。As shown in FIG. 1, the transistor protection device of the present invention has an insulating layer (insulating film) on a surface layer of a semiconductor substrate (16).
18) is installed, a resistor (resistor 6) connected to the gate of the transistor is installed on this insulating layer, and a wiring conductor (26) connected to this resistor is installed on the insulating conductor. A protection device for a transistor (for example, PchMOSFET2, NchMOSFET4) having a connected terminal portion (gate input terminal 8), wherein the semiconductor is provided on a surface layer of the semiconductor substrate below the wiring conductor to which the terminal portion is connected. A conductive region (32) having a conductivity type opposite to that of the substrate is provided, and a first capacitor (C 1 ) is provided between the terminal portion and the semiconductor substrate by the insulating layer between the conductive region and the terminal portion. And a second capacitor (C PN ) formed by a PN junction region (34 or 38) between the conductive region and the semiconductor substrate is inserted in series.
この発明のトランジスタの保護装置では、端子部（ゲー
ト入力端子８）の設置部分における基板（半導体基板16
など）内にPN接合領域34（またはPN接合領域38）を形成
したので、端子部（ゲート入力端子８）と基板（半導体
基板16など）との間に、PN接合領域34（またはPN接合領
域38）からなるキャパシタが設置されるので、このキャ
パシタの付加によって基板（半導体基板16など）と端子
部（ゲート入力端子８）との間に設置された絶縁膜18、
20に対する実効電圧が低下し、ニユポーラトランジスタ
やバイポーラトランジスタなどの静電破壊強度を高める
ことができる。In the transistor protection device of the present invention, the substrate (semiconductor substrate 16) in the installation portion of the terminal portion (gate input terminal 8) is
Etc.), the PN junction region 34 (or PN junction region 38) is formed, so that the PN junction region 34 (or PN junction region) is formed between the terminal portion (gate input terminal 8) and the substrate (semiconductor substrate 16, etc.). 38) is installed, the insulating film 18, which is installed between the substrate (semiconductor substrate 16 or the like) and the terminal portion (gate input terminal 8) by adding this capacitor,
The effective voltage for 20 decreases, and the electrostatic breakdown strength of the bipolar transistor, the bipolar transistor, etc. can be increased.
以下、この発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、この発明のトランジスタの保護装置の実施例
を示す。FIG. 1 shows an embodiment of a transistor protection device of the present invention.
第１図に示すように、このトランジスタの保護装置は、
ゲート入力部にポリシリコン層などで形成された抵抗体
として抵抗６、端子部としてゲート入力端子８の設置範
囲に対応する半導体基板16の表面層に半導体基板16とは
反対導電型の導電領域32を形成することにより、半導体
基板16と導電領域32とからなるPN接合領域34を設置して
なるものである。すなわち、半導体基板16がＮ型半導体
で構成される場合、導電領域32はＰ型半導体領域（Ｐウ
ェル）を形成し、また、半導体基板16がＰ型半導体で構
成される場合、導電領域32はＮ型半導体領域（Ｎウェ
ル）を形成する。このような導電領域32が形成は、半導
体基板16の表面にイオン注入あるいは不純物拡散などの
方法で行うものである。As shown in FIG. 1, the protection device for this transistor is
A conductive region 32 having a conductivity type opposite to that of the semiconductor substrate 16 is formed on the surface layer of the semiconductor substrate 16 corresponding to the installation range of the resistor 6 as a resistor formed of a polysilicon layer or the like in the gate input portion and the gate input terminal 8 as the terminal portion. By forming the above, the PN junction region 34 including the semiconductor substrate 16 and the conductive region 32 is provided. That is, when the semiconductor substrate 16 is made of an N-type semiconductor, the conductive region 32 forms a P-type semiconductor region (P well), and when the semiconductor substrate 16 is made of a P-type semiconductor, the conductive region 32 is An N-type semiconductor region (N well) is formed. The formation of such a conductive region 32 is performed by a method such as ion implantation or impurity diffusion on the surface of the semiconductor substrate 16.
このような導電領域32が形成された半導体基板16の表面
には、絶縁層としてシリコン酸化膜などの絶縁膜18が設
置され、導電領域32の範囲内に位置する絶縁膜18の表面
には、ポリシリコン層からなる抵抗６が設置され、この
抵抗６の表面は絶縁膜18の表面に設置したシリコン酸化
膜などの絶縁膜20によって覆われている。抵抗６の表面
を覆う絶縁膜20に対して選択的に開口22、24が形成され
て配線導体26、28が金属蒸着によって設置され、各配線
導体26、28の表面にパッシベーションを目的とした絶縁
膜30が形成され、絶縁膜30に開口を設けて露出させた配
線導体26に対して、ゲート入力端子８を構成するリード
ワイヤが溶着されている。An insulating film 18 such as a silicon oxide film is provided as an insulating layer on the surface of the semiconductor substrate 16 on which the conductive region 32 is formed, and on the surface of the insulating film 18 located within the conductive region 32, A resistor 6 made of a polysilicon layer is provided, and the surface of the resistor 6 is covered with an insulating film 20 such as a silicon oxide film provided on the surface of the insulating film 18. Openings 22 and 24 are selectively formed in the insulating film 20 covering the surface of the resistor 6 and wiring conductors 26 and 28 are installed by metal vapor deposition, and insulation for the purpose of passivation is provided on the surface of each wiring conductor 26 and 28. The film 30 is formed, and the lead wire forming the gate input terminal 8 is welded to the wiring conductor 26 exposed by forming an opening in the insulating film 30.
したがって、このような構成によれば、抵抗６またはゲ
ート入力端子８と、半導体基板16との間には、絶縁膜18
および導電領域32が介在している。このため、このよう
な絶縁膜18に対する導電領域32の設置によって、抵抗６
またはゲート入力端子８と、半導体基板16との間には、
第２図に示すように、絶縁膜18による第１のキャパシタ
C1に対して、PN接合領域34によって形成された第２キャ
パシタCPNが直列に設置される。この結果、従来の絶縁
膜18のみによるキャパシタC1に対して、キャパシタCPN
が直列に接続されたことになり、このキャパシタCPNの
分圧によってキャパシタC1に対する実効電圧が低下する
ため、その低下分だけ耐圧Vdが高くなり、トランジスタ
に対する静電破壊強度が向上する。Therefore, according to such a configuration, the insulating film 18 is provided between the resistor 6 or the gate input terminal 8 and the semiconductor substrate 16.
And the conductive region 32 is interposed. Therefore, when the conductive region 32 is provided on the insulating film 18, the resistance 6 is reduced.
Alternatively, between the gate input terminal 8 and the semiconductor substrate 16,
As shown in FIG. 2, the first capacitor formed of the insulating film 18 is used.
A second capacitor C PN formed by the PN junction region 34 is installed in series with C 1 . As a result, with respect to the capacitor C 1 by only the conventional insulating film 18, the capacitor C PN
Are connected in series, and the partial voltage of this capacitor C PN lowers the effective voltage for the capacitor C 1. Therefore, the breakdown voltage Vd increases by the amount of the reduction, and the electrostatic breakdown strength for the transistor improves.
第３図は、この発明のトランジスタの保護装置の他の実
施例を示す。FIG. 3 shows another embodiment of the transistor protection device of the present invention.
第１図に示した実施例では、半導体基板16の表面層に半
導体基板16とは反対導電型の１つの導電領域32を設置し
たが、この実施例の保護装置は、半導体基板16の表面層
に半導体基板16とは反対導電型の導電領域32を設置する
とともに、その導電領域32の内部に導電領域32とは反対
導電型の導電領域36を設置したものである。そして、導
電領域32、36は、ゲート入力端子８から抵抗６の連続し
た電位傾斜を考慮して、絶縁耐圧上必要な抵抗６の高電
位分布側の範囲、たとえば、ゲート入力端子８から抵抗
６の半分程度の範囲に設定する。In the embodiment shown in FIG. 1, one conductive region 32 having a conductivity type opposite to that of the semiconductor substrate 16 is provided on the surface layer of the semiconductor substrate 16. However, the protective device of this embodiment has a surface layer of the semiconductor substrate 16. A conductive region 32 having a conductivity type opposite to that of the semiconductor substrate 16 is provided, and a conductive region 36 having a conductivity type opposite to that of the conductive region 32 is provided inside the conductive region 32. In consideration of the continuous potential gradient from the gate input terminal 8 to the resistor 6, the conductive regions 32 and 36 have a range on the high potential distribution side of the resistor 6, which is necessary for the dielectric strength, for example, from the gate input terminal 8 to the resistor 6. Set the range to about half.
このように、二重に導電領域32、36を設置することによ
って、半導体基板16と導電領域32との間にPN接合領域34
が形成され、また、導電領域32と導電領域36との間にPN
接合領域38が形成される。In this way, by providing the conductive regions 32 and 36 doubly, the PN junction region 34 is provided between the semiconductor substrate 16 and the conductive region 32.
Is formed, and PN is formed between the conductive region 32 and the conductive region 36.
The bonding area 38 is formed.
したがって、このような二重の導電領域32、36の設置に
よってPN接合領域34、38を形成した場合によってPN接合
領域34、38を形成した場合、第４図に示すように、抵抗
６またはゲート入力端子８と半導体基板16との間には、
絶縁膜18によるキャパシタC1に対して、各PN接合領域3
4、38によって形成されたキャパシタCPN1、CPN2が直列
に接続されることになる。この結果、前記実施例に比較
して追加されたキャパシタCPN2の分圧だけキャパシタC1
に対する実効電圧がより低下し、抵抗６またはゲート入
力端子８と半導体基板16との間の耐圧Vdは、キャパシタ
CPN2の分だけ高められて、静電破壊強度が向上する。Therefore, when the PN junction regions 34 and 38 are formed by forming the double conductive regions 32 and 36 and the PN junction regions 34 and 38 are formed, as shown in FIG. Between the input terminal 8 and the semiconductor substrate 16,
Against capacitor C 1 due to the insulating film 18, the PN junction area 3
The capacitors C PN1 and C PN2 formed by 4, 38 are connected in series. As a result, the capacitor C 1 is divided by the partial voltage of the added capacitor C PN2 as compared with the above embodiment.
The effective voltage with respect to is further decreased, and the withstand voltage Vd between the resistor 6 or the gate input terminal 8 and the semiconductor substrate 16 becomes
It is increased by C PN2 and the electrostatic breakdown strength is improved.
そして、導電領域32、36は、第１図に示した導電領域32
と同様に抵抗６またはゲート入力端子８を包囲する範囲
に設置しても同様の効果が得られるが、二重に導電領域
32、36の設置によってPN接合領域34、38を形成した場
合、耐圧が向上するので、その向上した耐圧に応じて低
電位分布側の形成範囲を削減しても、十分な絶縁破壊強
度を得ることができる。The conductive regions 32 and 36 are the conductive regions 32 shown in FIG.
Similar effects can be obtained by installing the resistor 6 or the gate input terminal 8 in a range surrounding the same, but the double conductive region
When the PN junction regions 34 and 38 are formed by installing the 32 and 36, the withstand voltage is improved, so that sufficient dielectric breakdown strength can be obtained even if the formation range on the low potential distribution side is reduced according to the improved withstand voltage. be able to.
なお、各実施例ではゲート入力端子８側に抵抗６が設置
された場合について説明したが、入力側に抵抗６が設置
されない場合にも、ゲート入力端子８などの端子部が形
成された半導体基板16内にPN接合領域34、または二重の
PN接合領域34、38を形成して、トランジスタを静電破壊
から保護することができる。In each of the embodiments, the case where the resistor 6 is installed on the gate input terminal 8 side has been described. However, even when the resistor 6 is not installed on the input side, a semiconductor substrate having a terminal portion such as the gate input terminal 8 is formed. PN junction area 34 in 16 or double
The PN junction regions 34, 38 can be formed to protect the transistor from electrostatic breakdown.
また、実施例ではユニポーラトランジスタを例に取って
説明したが、この発明はバイポーラトランジスタにも同
様に適用して同様の効果が得られる。この場合、PN接合
領域は、バイポーラトランジスタのベース端子などの端
子部を設置された半導体基板内に設置されることによ
り、ユニポーラトランジスタの場合と同様に静電破壊強
度を向上させることができる。Further, although the unipolar transistor has been described as an example in the embodiments, the present invention can be similarly applied to the bipolar transistor to obtain the same effect. In this case, the PN junction region is installed in the semiconductor substrate in which the terminal portion such as the base terminal of the bipolar transistor is installed, so that the electrostatic breakdown strength can be improved as in the case of the unipolar transistor.
以上説明したように、この発明によれば、端子部の設置
部分における基板内にPN接合領域を形成したので、端子
部と基板との間に、PN接合領域で形成されたキャパシタ
が挿入されることになり、そのキャパシタの付加によっ
て静電破壊強度を向上させることができる。As described above, according to the present invention, since the PN junction region is formed in the substrate in the installation portion of the terminal portion, the capacitor formed in the PN junction region is inserted between the terminal portion and the substrate. Therefore, the electrostatic breakdown strength can be improved by adding the capacitor.
第１図はこの発明のトランジスタの保護装置の実施例を
示す断面図、第２図は第１図に示したトランジスタの保
護装置の等価回路を示す回路図、第３図はこの発明のト
ランジスタの保護装置の他の実施例を示す断面図、第４
図は第３図に示したトランジスタの保護装置の等価回路
を示す回路図、第５図は相補型MOSトランジスタ回路を
示す回路図、第６図は第５図に示した相補型MOSトラン
ジスタ回路のゲート入力部を示す断面図である。 ２…PchMOSFET（トランジスタ） ４…NchMOSFET（トランジスタ） ６…抵抗（抵抗体） ８…ゲート入力端子（端子部） 16…半導体基板 18…絶縁膜（絶縁層） 26…配線導体 32…導電領域 34、38…PN接合領域 C1…第１のキャパシタ CPN…第２のキャパシタ。FIG. 1 is a sectional view showing an embodiment of a transistor protection device of the present invention, FIG. 2 is a circuit diagram showing an equivalent circuit of the transistor protection device shown in FIG. 1, and FIG. Sectional drawing which shows the other Example of a protective device, 4th
FIG. 5 is a circuit diagram showing an equivalent circuit of the transistor protection device shown in FIG. 3, FIG. 5 is a circuit diagram showing a complementary MOS transistor circuit, and FIG. 6 is a complementary MOS transistor circuit shown in FIG. It is sectional drawing which shows a gate input part. 2 ... Pch MOSFET (transistor) 4 ... Nch MOSFET (transistor) 6 ... Resistor (resistor) 8 ... Gate input terminal (terminal part) 16 ... Semiconductor substrate 18 ... Insulating film (insulating layer) 26 ... Wiring conductor 32 ... Conductive region 34, 38 ... PN junction region C 1 ... First capacitor C PN ... Second capacitor.
Claims (1)
の絶縁層上にトランジスタのゲートに接続される抵抗体
を設置するとともに、この抵抗体に接続される配線導体
を設置し、この配線導体上に接続した端子部を備えたト
ランジスタの保護装置であって、 前記端子部を接続すべき前記配線導体の下層側の前記半
導体基板の表面層に前記半導体基板と反対導電型の導電
領域を設置し、 前記端子部と前記半導体基板との間に、前記導電領域と
前記端子部との間の前記絶縁層による第１のキャパシタ
と、前記導電領域と前記半導体基板とのPN接合領域によ
る第２のキャパシタとを直列に挿入させたことを特徴と
するトランジスタの保護装置。1. An insulating layer is provided on a surface layer of a semiconductor substrate, a resistor connected to a gate of a transistor is provided on the insulating layer, and a wiring conductor connected to the resistor is provided. A transistor protection device comprising a terminal portion connected to a wiring conductor, wherein a conductive region of a conductivity type opposite to that of the semiconductor substrate is provided on a surface layer of the semiconductor substrate below the wiring conductor to which the terminal portion is to be connected. And a first capacitor formed between the terminal portion and the semiconductor substrate by the insulating layer between the conductive region and the terminal portion, and a PN junction region between the conductive region and the semiconductor substrate. A protection device for a transistor, wherein a second capacitor is inserted in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034728A JPH0693496B2 (en) | 1986-02-19 | 1986-02-19 | Transistor protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61034728A JPH0693496B2 (en) | 1986-02-19 | 1986-02-19 | Transistor protector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62193164A JPS62193164A (en) | 1987-08-25 |
| JPH0693496B2 true JPH0693496B2 (en) | 1994-11-16 |
Family
ID=12422378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61034728A Expired - Lifetime JPH0693496B2 (en) | 1986-02-19 | 1986-02-19 | Transistor protector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0693496B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009038099A (en) * | 2007-07-31 | 2009-02-19 | Sanyo Electric Co Ltd | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54127684A (en) * | 1978-03-27 | 1979-10-03 | Nec Corp | Semiconductor device |
-
1986
- 1986-02-19 JP JP61034728A patent/JPH0693496B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62193164A (en) | 1987-08-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |