JPS6045865A - 情報処理装置 - Google Patents

情報処理装置

Info

Publication number
JPS6045865A
JPS6045865A JP15280283A JP15280283A JPS6045865A JP S6045865 A JPS6045865 A JP S6045865A JP 15280283 A JP15280283 A JP 15280283A JP 15280283 A JP15280283 A JP 15280283A JP S6045865 A JPS6045865 A JP S6045865A
Authority
JP
Japan
Prior art keywords
request signal
interrupt request
control device
controlled
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15280283A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6359181B2 (enrdf_load_stackoverflow
Inventor
Yoshihiro Eitai
永躰　義博
Toshio Shimada
嶋田　俊雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15280283A priority Critical patent/JPS6045865A/ja
Publication of JPS6045865A publication Critical patent/JPS6045865A/ja
Publication of JPS6359181B2 publication Critical patent/JPS6359181B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP15280283A 1983-08-22 1983-08-22 情報処理装置 Granted JPS6045865A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15280283A JPS6045865A (ja) 1983-08-22 1983-08-22 情報処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15280283A JPS6045865A (ja) 1983-08-22 1983-08-22 情報処理装置

Publications (2)

Publication Number Publication Date
JPS6045865A true JPS6045865A (ja) 1985-03-12
JPS6359181B2 JPS6359181B2 (enrdf_load_stackoverflow) 1988-11-18

Family

ID=15548471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15280283A Granted JPS6045865A (ja) 1983-08-22 1983-08-22 情報処理装置

Country Status (1)

Country Link
JP (1) JPS6045865A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145412A (en) * 1980-04-14 1981-11-12 Hitachi Ltd Interruption signal receiving circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145412A (en) * 1980-04-14 1981-11-12 Hitachi Ltd Interruption signal receiving circuit

Also Published As

Publication number Publication date
JPS6359181B2 (enrdf_load_stackoverflow) 1988-11-18

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