JPS6045018A - Formation of ohmic electrode - Google Patents
Formation of ohmic electrodeInfo
- Publication number
- JPS6045018A JPS6045018A JP15271883A JP15271883A JPS6045018A JP S6045018 A JPS6045018 A JP S6045018A JP 15271883 A JP15271883 A JP 15271883A JP 15271883 A JP15271883 A JP 15271883A JP S6045018 A JPS6045018 A JP S6045018A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- semiconductor substrate
- etching
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
Description
【発明の詳細な説明】
本発明は、半導体基板表面にオーム性電極を形成する方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming an ohmic electrode on the surface of a semiconductor substrate.
表面に高濃度のＰ型またはｎ型の層を有する半導体基板
上に、１！流狭窄措造を有するオーム性電極を形成する
方法としては、従来より第１図に示す方法が用いられて
いる。即ち、（１−ａ）Ｉｃおいて表面忙高濃度のＰ型
またはｎ型の層を有する半導体基板１上忙熱酸化やＯＶ
Ｄ等の方法により絶縁膜２を形成する。次１ｃ（１−ｂ
）で、絶縁膜２１Ｃエツチングにより電流注入用の開口
部４を設けるための７オトレジスト膜３よりなるマスク
をフォトリングラフィにより形成する。（１−ｃ）では
フォトレジスト膜３をマスクとして適当な選択エツチン
グ液により絶縁膜３に開口部４を設ける。続いて＜５−
ｄ）で適当な剥離剤を用いてフォトレジストを除去した
後、適当な表面処理液により開口部４に露出している半
導体基板１０表面をわずかにエツチングする。その後、
（１ｅ）ＶＣｊａいて蒸着法等によりオーム性＠触用の
金Ｍ広５を被着してから熱処理してオーム性Ｔｎ極を形
成する。1! on a semiconductor substrate having a highly concentrated p-type or n-type layer on the surface. As a method for forming an ohmic electrode having a flow constriction structure, the method shown in FIG. 1 has been used conventionally. That is, in (1-a) Ic, thermal oxidation or OV
The insulating film 2 is formed by a method such as D. Next 1c (1-b
), a mask made of a photoresist film 3 is formed by photolithography to provide an opening 4 for current injection by etching the insulating film 21C. In (1-c), an opening 4 is formed in the insulating film 3 using a suitable selective etching solution using the photoresist film 3 as a mask. Then <5-
After removing the photoresist using an appropriate stripping agent in step d), the surface of the semiconductor substrate 10 exposed in the opening 4 is slightly etched using an appropriate surface treatment liquid. after that,
(1e) An ohmic Tn electrode is formed by depositing an ohmic @tactile gold layer 5 using VCja vapor deposition or the like, and then heat-treating it.
ところで第１図に示した方法には次の様な欠点が存在す
る。それは（１−ｄ）Ｉｃおいて、剥離剤で７オトレジ
ストを除去する際、開口部４内の様な液体がよどみやす
い場所の清浄化が烈しく、表面処理液によるエツチング
を施した後でもレジスト残滓が存在して、（１−ｃ）で
被着されたオーム性接触用の金ＲＩ！Ｘ５と半導体基板
１表面との間の固有接触抵抗の増大化や、接触領域内で
の不均一を招く点である。そこで本発明の目的とすると
ころは、上述の様な半導体基板表面に電流狭窄構造を有
するオーム性電極を形成する際忙生じやすい、オーム性
接触部の固有接触抵抗の増大や接触領域内での不均一を
防止して、低接触抵抗でかつ均一な接触を有するオーム
性電極の形成方法を提供するとと忙ある。However, the method shown in FIG. 1 has the following drawbacks. In (1-d) Ic, when removing the photoresist 7 with a stripping agent, the cleaning of areas where the liquid tends to stagnate, such as the inside of the opening 4, is intense, and even after etching with the surface treatment liquid, resist residue remains. is present and gold RI for ohmic contact deposited with (1-c)! This leads to an increase in the specific contact resistance between X5 and the surface of the semiconductor substrate 1, and non-uniformity within the contact area. Therefore, an object of the present invention is to reduce the increase in the specific contact resistance of the ohmic contact portion and the increase in the contact area within the contact area, which tend to occur when forming an ohmic electrode with a current confinement structure on the surface of a semiconductor substrate as described above. There is an urgent need to provide a method for forming ohmic electrodes that prevent non-uniformity and have low contact resistance and uniform contact.
第２図に本発明Ｉｃ基く、オーム性電極の形成方法を示
す。先ず（２−ａ ）で、表面に高濃度のＰ型またはｎ
型の層を有する半導体基板１上に熱酸化やＯＶＤ等の方
法により胞ｆｉ！２を形成する。次Ｋ（２−ｂ）で、絶
縁膜２にエツチングにより電流注入用の開口部４を設け
るための７オトンジスト膜３よりなるマスクを７オトリ
ングラフイにより形成する。（２−ｃ）ではフォトレジ
スト膜３をマスクとして適当なエツチング液により絶縁
膜２のエツチングを行う。しかし、ここでは絶縁膜２の
エツチングを完了せず姥、薄く残しておくという点が第
１図の従来法と異なっている。この後（２−ｄ）におい
てフォトレジストの剥離を行うが、刺離法としては、従
来の様な液体状の剥離剤を用いた方法でなく、開口部４
内にレジスト残滓を生じる事の極めて少ない酸素プラズ
マ処理を用いる。第１図の従来法においては剥離工程に
対し酸素プラズマ処理を行おうとしても、開口部に露出
している半導体基板表面の酸化等の損傷を招き易く、そ
の使用には難点があったのに対し、本発明に基（方法で
は（２−ｄ）の剥離時には、開口部４に薄く絶＃、膜２
が残されているので酸素プラズマ処理を行っても半導体
基板１の表面Ｆｃｖ４傷を生じない。FIG. 2 shows a method for forming an ohmic electrode based on Ic of the present invention. First, in (2-a), there is a high concentration of P type or n type on the surface.
A cell fi! is formed on the semiconductor substrate 1 having a mold layer by a method such as thermal oxidation or OVD. form 2. In the next step K (2-b), a mask made of a 7-oto-dist film 3 is formed by etching the insulating film 2 to form an opening 4 for current injection by etching. In (2-c), the insulating film 2 is etched using a suitable etching solution using the photoresist film 3 as a mask. However, this method differs from the conventional method shown in FIG. 1 in that the etching of the insulating film 2 is not completed and a thin layer is left. After this, in (2-d), the photoresist is peeled off, but instead of using a conventional method using a liquid peeling agent, the photoresist is peeled off from the opening 4.
Oxygen plasma treatment is used, which produces very little resist residue inside the film. In the conventional method shown in Figure 1, even if oxygen plasma treatment was attempted during the stripping process, it would easily cause damage such as oxidation to the surface of the semiconductor substrate exposed in the opening, and its use was difficult. On the other hand, in the method (2-d) according to the present invention, a thin, absolute #2 film is applied to the opening 4.
Since Fcv4 remains, even if oxygen plasma treatment is performed, no Fcv4 scratches will occur on the surface of the semiconductor substrate 1.
続いて、フォトレジストの剥離終了後、（２ｅ）におい
て半導体基板ｌを６食しない適当な選択エツチング液に
より絶縁膜２のエツチングを行って開口部４に薄く残っ
ている絶９８２を除去してから、適当な表面層（！Ｉ！
液により半導体基板１の表面をわずかにエツチングする
。その後（２−ｆ）において蒸着法等によりオーム性接
触用の金属膜５を被着してから熱処理してオーム性電極
の形成工程が終了する。Subsequently, after the photoresist is removed, the insulating film 2 is etched using a suitable selective etching solution that does not etch the semiconductor substrate 1 in step (2e), and the thin layer 982 remaining in the opening 4 is removed. , a suitable surface layer (!I!
The surface of the semiconductor substrate 1 is slightly etched with the liquid. Thereafter, in step (2-f), a metal film 5 for ohmic contact is deposited by vapor deposition or the like and then heat-treated to complete the process of forming the ohmic electrode.
本発明の具体的な実施例としては半導体基板ｌとして、
液相エピタキシャル成長あるいは拡散等によってＰ型不
純物を高濃度にドーピングされたＩｎＰあるいはＩｎＧ
ａＡｓＰ等の表面層を有するＩｒ＋Ｐ基板、絶縁膜２と
しては、ＯＶＤ法によって形成された厚さ４０００八程
度のＳｉｎ、膜、第２図の（２−ｄ）及び（２−ｅ）の
ｓｔｏ、ｇのエツチング液としては、７ツ酸、フッ化７
ンモニウム及び水よりなる混合液、（２−ｃ）における
エツチングにおいて開口部Ｉｃ残すＳｉｎ、の膜厚とし
ては１０００人程度１（２−ｅ）ＦＣおいて用いられる
半導体基板表面の処理液としては、硫酸、過酸化水素及
び水よりなる混合液、（２−ｆ）におけるオーム性接触
用の金Ｆ４膜５としてはＴｉ、Ｐｔの順で被着させられ
た二層膜があげ以上の様に本発明は、電流狭窄構造を有
するオーム性電極の形成に関し、電流注入用の開口をエ
ツチングによりＰ３縁膜に設げる際のマスクとして用い
られるフォトレジストＰＡのｌＩＩ 煎が、酸素プラズ
マ処理によって極めて良好釦行われるという特徴を有し
ているので、従来に比べて、接触領域の固有接触抵抗が
低くかつ領域内での均一性にも優れたオーム性電極の形
成方法が提供される。As a specific embodiment of the present invention, as a semiconductor substrate l,
InP or InG doped with a high concentration of P-type impurities by liquid phase epitaxial growth or diffusion, etc.
An Ir+P substrate having a surface layer such as aAsP, an insulating film 2 of about 4,000 mm thick formed by an OVD method, an sto as shown in (2-d) and (2-e) in FIG. As the etching solution for g, 7 acid, fluoride 7
The film thickness of the mixed solution consisting of ammonium and water, which leaves the opening Ic in the etching in (2-c), is about 1000.1 (2-e) As the processing solution for the surface of a semiconductor substrate used in FC, The gold F4 film 5 for ohmic contact in the mixed solution of sulfuric acid, hydrogen peroxide and water (2-f) is a two-layer film deposited in this order of Ti and Pt. The present invention relates to the formation of an ohmic electrode having a current confinement structure, and relates to the formation of an ohmic electrode having a current confinement structure. Since the method has the characteristic of being formed using a button, a method for forming an ohmic electrode is provided which has a lower specific contact resistance in the contact area and excellent uniformity within the area compared to the conventional method.
第１図は、従来のオーム性電極の形成方法を示す図、第
２図は本発明に基くオーム性電極の形成方法を示す図で
ある。なお図において
ｌ・・・半導体基板、２・・・Ｐ３ｎ膜、３・・・フォ
トレジスト膜、４・・・開口部、５・・・オーム性接触
用の金第１図
４
第２ＭFIG. 1 is a diagram showing a conventional method for forming an ohmic electrode, and FIG. 2 is a diagram showing a method for forming an ohmic electrode according to the present invention. In the figure, l: semiconductor substrate, 2: P3n film, 3: photoresist film, 4: opening, 5: gold for ohmic contact.
Claims (1)
被着せしめる工程と、フォトレジスト膜をマスクとして
電流注入用の開口部に限定して前記絶縁膜をわずかな厚
みを残してエツチングする工程と、前記フォトレジスト
膜を酸素プラズマ処理して除去する工程と、前記開口部
に残存する絶縁膜が除去されるまで、前記半導体基板を
腐蝕しない選択エツチング液により絶縁膜をエツチング
する工程と、前記開口部に露出した半導体基板表面を表
面処理液によりわずか処エツチングする工程と、前記開
口部上にオーム性接触用の金パ膜を被着せしめた後、熱
処理を行う工程とを含むことを特徴とするオーム性電極
の形成方法。A step of depositing a civil insulating film on the semiconductor substrate having a high concentration impurity layer on the surface, and a step of etching the insulating film leaving a slight thickness only in the opening for current injection using a photoresist film as a mask. , a step of removing the photoresist film by oxygen plasma treatment; a step of etching the insulating film with a selective etching solution that does not corrode the semiconductor substrate until the insulating film remaining in the opening is removed; The method is characterized by comprising the steps of slightly etching the surface of the semiconductor substrate exposed in the opening with a surface treatment solution, and a step of applying heat treatment after depositing a gold film for ohmic contact on the opening. A method for forming ohmic electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15271883A JPS6045018A (en) | 1983-08-22 | 1983-08-22 | Formation of ohmic electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15271883A JPS6045018A (en) | 1983-08-22 | 1983-08-22 | Formation of ohmic electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6045018A true JPS6045018A (en) | 1985-03-11 |
Family
ID=15546632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15271883A Pending JPS6045018A (en) | 1983-08-22 | 1983-08-22 | Formation of ohmic electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045018A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59224232A (en) * | 1984-04-27 | 1984-12-17 | Komatsu Ltd | Work carrier |
-
1983
- 1983-08-22 JP JP15271883A patent/JPS6045018A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59224232A (en) * | 1984-04-27 | 1984-12-17 | Komatsu Ltd | Work carrier |
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