JPH06283547A - Manufacturing method of semiconductor device and thin film transistor - Google Patents

Abstract

PURPOSE:To obtain a thin film transistor having excellent transistor characteristics by cleaning up the surface of a semiconductor layer before it is etched away. CONSTITUTION:Metallic layer 20, 21 are formed on semiconductor layers 11, 12 to selectively etch away the metallic layers 20, 21 and then the semiconductor layer 12 exposed by the etching step with the surface thereof cleaned up is to be etched away layer. For example, Cr-made metallic layer 20 and Al-made metallic layer 21 are formed on an n type amorphous silicon 12 and a gate insulating film 10. Next, after the formation of a resist pattern, the metallic layers 20, 21 are etched away to form source electrodes 13, 14 and drain electodes 15, 16. Next, the surface of the n type amorphous silicon 12 to be exposed after etching away the metallic layer 20 is treated with fluoric acid to be cleaned up. Finally, the surface of the treated n type amorphous silicon 12 is to be dry-etched away to obtain the specific transistor structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used in a liquid crystal display device, for example.

[0002]

6 to 11 are sectional views for explaining a first example of a conventional process in manufacturing a thin film transistor. The structure will be described with reference to FIG. 11 which is the final view of the process. An insulating substrate 8 as a substrate for constructing a transistor structure, a gate electrode 9, and a gate insulating film 10 for maintaining insulation of the gate electrode 9 form a base layer. The i-type amorphous silicon 11 is formed on the base layer. An n-type amorphous silicon 12 is formed thereon, and source electrodes 13 and 14 and drain electrodes 15 and 16 are formed symmetrically thereon.

Next, a first example of a conventional thin film transistor manufacturing process will be described in order with reference to the flowchart of FIG. In the step shown in FIG. 6, the gate electrode 9 is formed in a desired pattern on the insulating substrate 8 made of glass or the like with chromium or the like. Subsequently, in the step shown in FIG. 7, a gate insulating film 10 is formed by using silicon nitride, silicon oxide, or the like, and an i-type amorphous silicon 11 which is amorphous silicon which is not doped with nothing and an n-type which is doped with impurities. The type amorphous silicon 12 is formed by using the plasma CVD method (step S21).

Next, a desired resist pattern is formed,
In the process shown in FIG. 8, both ends of the n-type amorphous silicon 12 and the i-type amorphous silicon 11 are removed by dry etching. After that, the resist is removed, and the metal layer 20 made of chromium and the metal layer 21 made of aluminum, which are the bases of the source electrode and the drain electrode, are formed in the process shown in FIG. 9 (step S22). Next, after forming a resist pattern, in the process shown in FIG. 10, the metal layers 20 and 21 are etched to form the source electrodes 13 and 14 and the drain electrodes 15 and 16 (step S23).
In the step shown in FIG. 1, the n-type amorphous silicon 12 is etched (step S24) to obtain a desired transistor structure.

12 to 18 are sectional views for explaining a second example of a conventional process in manufacturing a thin film transistor. The structure will be described with reference to FIG. 18, which is the final view of the process. An insulating substrate 8 as a substrate for constructing a transistor structure, a gate electrode 9, and a gate insulating film 10 for maintaining insulation of the gate electrode 9 form a base layer. An i-type amorphous silicon 11 and an etching stopper 17 for protecting the i-type amorphous silicon 11 are formed on the base layer. An n-type amorphous silicon 12 is formed thereon, and further, source electrodes 13 and 14 and drain electrodes 15 and 16 each composed of two layers are symmetrically formed thereon.

Next, a second example of the conventional thin film transistor manufacturing process will be described in order with reference to the flowchart of FIG. In the step shown in FIG. 12, the gate electrode 9 is formed in a desired pattern on the insulating substrate 8 made of glass or the like with chromium or the like. Subsequently, in the step shown in FIG. 13, the gate insulating film 10 is formed using silicon nitride, silicon oxide, or the like,
An i-type amorphous silicon 11 which is amorphous silicon which is not doped and an etching stopper 17 are formed thereon by plasma CVD using silicon nitride or silicon oxide as a material.

Next, a desired resist pattern is formed,
In the step shown in FIG. 14, the etching stopper 17 is selectively removed by dry etching. After removing the resist, in the step shown in FIG.
The n-type amorphous silicon 12 is formed on the 7 and the i-type amorphous silicon 11 (step S21). A plasma CVD method is used to form amorphous silicon.

Then, in the step shown in FIG. 16, a metal layer 20 of chromium and a metal layer 21 of aluminum which are the bases of the source electrode and the drain electrode are formed (step S2).
2). Next, after forming a resist pattern, in the step shown in FIG. 17, the metal layers 20 and 21 are etched (step S23) to form the source electrodes 13 and 14 and the drain electrodes 15 and 16, and then in the step shown in FIG. The n-type amorphous silicon 12 and the i-type amorphous silicon 11 are etched (step S24) to obtain a desired transistor structure.

When a thin film transistor is used as a liquid crystal display device, it is necessary to form a large number of thin film transistors having the structure shown in FIG. 11 or 18 on the substrate of the liquid crystal display device, and the performance of the liquid crystal display device is sufficiently exhibited. In order to do so, it is necessary to manufacture the thin film transistor uniformly and with good reproducibility.

[0010]

Since the conventional method of manufacturing a thin film transistor is configured as described above, when the metal layer 20 is formed of chromium, the steps of the first example shown in FIG. 10 and FIG. In the step of the second example shown, the chromium-silicon compound layer is formed on the surface of the n-type amorphous silicon 12 after the metal layers 20 and 21 are removed by etching. This chromium-silicon compound layer is formed at the interface where the chromium layer and the silicon layer contact. Since this layer cannot be removed by a commonly used cerium-based chromium etching solution, the chromium-silicon compound layer is not removed even if the chromium layer is removed, and the exposed surface of the n-type amorphous silicon 12 does not have chromium-silicon. The compound layer remains. This layer becomes an etching barrier during the subsequent dry etching of the n-type amorphous silicon 12 and causes a dead time in which the etching hardly progresses.

In FIG. 4, a graph 5 shows the relationship between the dry etching time and the dry etching amount for the sample in which the chromium-silicon compound layer is formed on the amorphous silicon and the sheet resistance is about 20 KΩ. The area indicated by reference numeral 7 in this graph 5 shows the characteristics of dead time. From this graph, it can be seen that etching hardly progresses for a while immediately after the start of etching. Further, in FIG. 4, a graph 6 shows the relationship between the dry etching time and the dry etching amount for the sample in which the chromium-silicon compound layer is formed on the amorphous silicon and the sheet resistance is about 3 KΩ. It can be seen from this graph 6 that when a chromium-silicon compound layer having a sheet resistance of about 3 KΩ is formed, the amorphous silicon is not etched at all.

Since the formation state of the chromium-silicon compound layer is sensitive to the surface state of the silicon layer, it is difficult to keep the surface state constant with good reproducibility when the substrate area is large and the silicon layer area is large. , It is difficult to form the chromium-silicon compound layer on the same substrate uniformly over a wide range with good reproducibility. Therefore, the reproducibility of the etching time cannot be obtained, and the etching time varies depending on the location even on the same substrate, so that uniform etching cannot be performed.

If the etching is not uniform in the substrate, the electrical characteristics of the thin film transistor become non-uniform, and when used in a liquid crystal display device, bright parts or dark parts appear in the display screen, which causes display unevenness. There was a problem. Further, in the step of etching the n-type amorphous silicon 12, when the etching is insufficient and the n-type amorphous silicon 12 remains on the i-type amorphous silicon 11 or the etching stopper 17, or in the first conventional example, the n-type amorphous silicon 12 is used. When the i-type amorphous silicon 11 under 12 is completely etched, the thin film transistor does not operate, and when it is used in a liquid crystal display device, the pixel of the liquid crystal display device corresponding to the thin film transistor does not display. Therefore, there is a problem that the display quality is remarkably deteriorated.

The present invention has been made to solve the above problems, and a method for manufacturing a thin film transistor having good transistor characteristics by cleaning the surface of amorphous silicon before etching amorphous silicon is provided. The purpose is to get.

[0015]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a metal layer on a semiconductor layer,
The method includes the steps of selectively etching the metal layer, cleaning the surface of the semiconductor layer exposed by the etching, and etching the semiconductor layer whose surface has been cleaned.

A first aspect of a method of manufacturing a thin film transistor according to the present invention is a step of preparing a base layer including a gate electrode and a gate insulating film, which are sequentially stacked on an insulating substrate,
Forming a silicon layer on the underlayer, forming a metal layer on the silicon layer, and etching a source electrode and a drain electrode by removing a predetermined portion of the metal layer by etching. The method includes: a step of cleaning the surface of the silicon layer exposed by removing a predetermined portion of the metal layer; and a step of etching the silicon layer whose surface is cleaned.

A second aspect of the method of manufacturing a thin film transistor according to the present invention is that in the step of forming the metal layer with a chromium layer and cleaning the surface of the silicon layer, the chromium-silicon compound layer on the surface of the silicon layer. Is removed using a solution containing hydrogen fluoride.

A third aspect of the method of manufacturing a thin film transistor according to the present invention is that, in the step of forming the metal layer with a chromium layer and cleaning the surface of the silicon layer, the chromium-silicon compound layer on the surface of the silicon layer. Is removed using a gas containing hydrogen fluoride.

A fourth aspect of the method of manufacturing a thin film transistor according to the present invention is that in the step of forming the metal layer with a chromium layer and cleaning the surface of the silicon layer, the chromium-silicon compound layer on the surface of the silicon layer. Is removed by sputter etching with an inert gas.

A fifth aspect of the method of manufacturing a thin film transistor according to the present invention further comprises a step of forming a mask for selectively performing the cleaning before the step of cleaning the surface of the silicon layer. ing.

[0021]

According to the method of manufacturing the semiconductor device of the present invention,
By cleaning the surface of the semiconductor layer exposed by etching, the metal-semiconductor compound layer remaining on the surface of the semiconductor layer that cannot be removed in the step of etching the metal layer can be removed. The semiconductor layer can be smoothly etched.

According to the first aspect of the method of manufacturing a thin film transistor of the present invention, the surface of the silicon layer exposed by removing a predetermined portion of the metal layer is cleaned so that it can be removed in the step of removing the metal layer. Without removing the layer of metal-silicon compound or the like left on the surface of the silicon layer, the etching of the silicon layer in the next step can be performed smoothly.

According to the second aspect of the method for manufacturing a thin film transistor according to the present invention, when the metal layer is formed of a chromium layer, a solution containing hydrogen fluoride is used to separate the silicon layer and the chromium layer. The chromium-silicon compound layer formed on the substrate can be removed.

According to the third aspect of the method of manufacturing a thin film transistor according to the present invention, when the metal layer is formed of a chromium layer, a gas containing hydrogen fluoride is used to separate the silicon layer and the chromium layer. The chromium-silicon compound layer formed on the substrate can be removed.

According to the fourth aspect of the method of manufacturing a thin film transistor according to the present invention, when the metal layer is formed of a chromium layer, sputter etching with inert ions is used to form a gap between the silicon layer and the chromium layer. Chromium formed on
The silicon compound layer can be removed.

According to the fifth aspect of the method of manufacturing a thin film transistor of the present invention, before the step of cleaning the surface of the silicon layer, a step of forming a mask for selectively performing the cleaning is provided. Thus, for example, the source electrode and the drain electrode can be prevented from being affected by cleaning, so that the cross-sectional shapes of the source electrode and the drain electrode can be maintained.

[0027]

1 is a flow chart showing the steps of a first embodiment of a method of manufacturing a thin film transistor according to the present invention. Hereinafter, a first embodiment of a method of manufacturing a thin film transistor according to the present invention will be described with reference to the flowchart of FIG. The finally obtained thin film transistor has the same structure as the conventional thin film transistor shown in FIG.

First, the gate electrode 9 is formed in a desired pattern with chromium or the like on the insulating substrate 8 made of glass or the like. Subsequently, the gate insulating film 10 is formed using silicon nitride, silicon oxide, or the like. Up to this point, refer to FIG. 6 and FIG.
This is the same as the conventional process shown in FIG.

Next, in step S1 shown in FIG. 1, i-type amorphous silicon 11 which is amorphous silicon which is not doped on the gate insulating film 10 and n-type amorphous silicon 12 which is doped with impurities such as phosphorus. Are formed by using the plasma CVD method.

Next, a desired resist pattern is formed,
N-type amorphous silicon by dry etching 1
2. Both ends of the i-type amorphous silicon 11 are removed. Then, the resist is removed. This step corresponds to the conventional step shown in FIG.

Next, in step S2, a chromium metal layer 2 serving as a base for the source and drain electrodes is formed on the n-type amorphous silicon 12 and the gate insulating film 10.
A metal layer 21 of 0 and aluminum is formed.

Next, after forming a resist pattern, in step S3, the metal layers 20 and 21 are etched to form the source electrodes 13 and 14 and the drain electrodes 15 and 1.
6 is formed.

Next, in step S4, a hydrofluoric acid treatment is performed to clean the surface of the n-type amorphous silicon 12 exposed after etching the metal layer 20 in step S3. As a hydrofluoric acid treatment method, for example, a wet method using a buffered hydrofluoric acid solution having a hydrogen fluoride concentration of 4.5% and an ammonium fluoride concentration of 35% (hereinafter abbreviated as BHF) is used for about 5 to 100 seconds. BHF processing is performed. By this treatment, the chromium-silicon compound layer formed on the surface of the n-type amorphous silicon 12 is removed.

Next, in step S5, dry etching is performed on the surface of the n-type amorphous silicon 12 subjected to the BHF process in step S4 to obtain a desired transistor structure. At this time, n-type amorphous silicon 1
2 Since the chromium-silicon compound layer on the exposed surface has been removed, the etching is extremely well performed as described later.

As a dry etching method, a mixed gas capable of highly selective etching with respect to silicon nitride and silicon oxide, for example, SF ₆ + C ₂ HCl ₂ F ₃ + O ₂ is made into plasma, and the mixed gas is put therein. This is performed by exposing the thin film transistor substrate that has undergone the steps up to step S4. In the thin film transistor having the structure of FIG.
Since it is necessary to dry-etch the n-type amorphous silicon 12 having a thickness of about nm or less, the dry etching rate is set to about 10 nm to 50 nm per minute.

Next, a second embodiment of the thin film transistor manufacturing method according to the present invention will be described. In the second embodiment, the structure of the thin film transistor finally obtained is shown in FIG.
This is the same as the conventional thin film transistor shown in FIG. Since the basic procedure is the same as that of the first embodiment, it will be described with reference to the flowchart of FIG. 1 similarly to the first embodiment.

First, the gate electrode 9 is formed in a desired pattern with chromium or the like on the insulating substrate 8 made of glass or the like, and subsequently the gate insulating film 10 is formed with silicon nitride or silicon oxide. An i-type amorphous silicon 11 which is amorphous silicon which is not doped and an etching stopper 17 are formed thereon by plasma CVD using silicon nitride or silicon oxide as a material.

Next, a desired resist pattern is formed,
The etching stopper 17 is selectively removed by dry etching. After that, the resist is removed. Up to this point, the process is the same as the conventional process shown in FIGS.

Next, in step S1 shown in FIG. 1, the n-type amorphous silicon 12 doped with impurities such as phosphorus is formed on the etching stopper 17 and the i-type amorphous silicon 11.

Subsequently, in step S2, metal layers 20 and 21 made of chromium and aluminum, which are the bases of the source electrode and the drain electrode, are formed.

After forming a resist pattern, the metal layers 20 and 21 are etched to form the source electrodes 13 and 14 and the drain electrodes 15 and 1 in step S3.
6 is formed.

The following step S4 and step S
In step 5, the steps similar to the steps S4 and S5 described in the first embodiment are performed to obtain a desired transistor structure. In this case, as described above, the n-type amorphous silicon 12 is etched very well.

However, in the case of the thin film transistor having the structure of FIG. 18 in step S5, the dry etching rate of the n-type amorphous silicon 12 is 50 nm to 200 nm per minute.
Set to about nm.

Here, the goodness of etching of the n-type amorphous silicon 12 in the above embodiment will be considered. In FIG. 4, the thin film transistor substrate after the steps up to step S4 is replaced with SF ₆ + C ₂ HCl ₂ F ₃ + O.
Graph 4 shows the relationship between the etching time and the etching amount when etching is performed by exposing the mixed gas of ₂ to the plasma. The etching amount increases with the etching time, and the phenomenon of dead time in which the etching hardly progresses as shown by reference numeral 7 is not observed.
By eliminating the dead time, reproducibility of the etching time is obtained, so that the etching amount is constant, and the etching time is different on the same substrate due to the difference in the formation state of the chromium-silicon compound layer on the same substrate. Since such a phenomenon also disappears, the uniformity of etching is improved.

Therefore, the electric characteristics of the thin film transistor become uniform, and when used in a liquid crystal display device, display unevenness does not occur. In addition, the etching of the n-type amorphous silicon 12 is insufficient and the n-type amorphous silicon 12 remains on the i-type amorphous silicon 11 or the etching stopper 17, or the i-type under the n-type amorphous silicon 12 in the first conventional example. Since the phenomenon due to the dead time such as the complete etching of the amorphous silicon 11 is eliminated, the defective portion of the liquid crystal display device due to the inoperability of the thin film transistor does not occur.

The dead time varies depending on the etching amount of each of the unprocessed amorphous silicon on which the chromium-silicon compound layer is not formed and the amorphous silicon on which the chromium-silicon compound layer is formed. It can also be evaluated by using the relative etching amount obtained by comparison. In FIG.
A graph 18 shows the relationship between the buffer hydrofluoric acid treatment time and the relative etching amount for the sample in which the chromium-silicon compound layer is formed on the amorphous silicon and the sheet resistance is about 3 KΩ. Graph 19 shows the relationship between the buffer hydrofluoric acid treatment time and the relative etching amount for a sample in which a chromium-silicon compound layer is formed on amorphous silicon and the sheet resistance is about 20 KΩ.
When the relative etching amount is 1, the dead time can be approximated to 0. Therefore, in FIG. It can be seen that the treatment reduces the dead time to zero and advances the dry etching of amorphous silicon.

Both the first and second embodiments of the method of manufacturing a thin film transistor according to the present invention described above can be modified in various ways.

As a first modification, the chromium-silicon compound layer may be removed using dilute hydrofluoric acid in the step of hydrofluoric acid treatment for cleaning the amorphous silicon surface in step S4 shown in FIG. .

As a second modification, in the step of hydrofluoric acid treatment for cleaning the amorphous silicon surface in step S4 shown in FIG. 1, the chromium-silicon compound layer is removed by buffering with a solution containing hydrofluoric acid other than hydrofluoric acid. You may use it. The solution containing hydrofluoric acid is, for example, a mixed solution of hydrofluoric acid and nitric acid, a mixed solution of hydrofluoric acid, nitric acid, acetic acid, a mixed solution of hydrofluoric acid and ethanol, or the like.

As a third modification, in the step of hydrofluoric acid treatment for cleaning the surface of the amorphous silicon in step S4 shown in FIG. 1, the chromium-silicon compound layer may be removed by hydrogen fluoride gas. As a method, it is performed by exposing the thin film transistor substrate, which has undergone the processes up to step S3, to hydrogen fluoride gas. As a method of supplying the hydrogen fluoride gas, anhydrous hydrogen fluoride gas may be used, or a method of gasifying from a hydrofluoric acid solution may be used.

Next, a fourth modification will be described with reference to the flowchart of FIG. The process up to step S13 is the same as the process up to step S3 in each of the first and second embodiments described above. Then, as step S14, the surface of the n-type amorphous silicon 12 exposed after etching the chromium metal layer 20 in step S13 is sputter-etched. The sputter etching method is performed by generating plasma of an inert gas by using, for example, a parallel plate type plasma processing apparatus, and exposing the thin film transistor substrate after the process up to step S13 to the plasma. Argon gas or the like is used as the inert gas in consideration of the sputtering effect and the like. The gas pressure inside the plasma processing apparatus is usually 1 to 10 Pa for processing.

Next, in step S15, SF ₆ + C ₂ H
A mixed gas composed of Cl ₂ F ₃ + O ₂ is turned into plasma, and the thin film transistor substrate which has been subjected to the steps up to step S14 is exposed to the plasma, whereby dry etching of amorphous silicon is performed. This step corresponds to the step S5 in each of the first and second embodiments described above.

In this fourth modification, step S1
Also by the sputter etching of No. 4, the effect of removing the chromium-silicon compound layer on the surface of the amorphous silicon can be obtained similarly to the buffer hydrofluoric acid treatment described in step S4 of the first and second embodiments.

As a fifth modification, when the hydrofluoric acid treatment of the surface of the n-type amorphous silicon 12 is performed in step S4 shown in FIG. 1, the metal layers 20 and 21 are etched in step S3 and the source electrodes 13 and After removing the resist pattern used to form the drain electrode 14 and the drain electrode 15 and 16, the surface and end faces of the source electrode and the drain electrode are protected so as not to be exposed to hydrofluoric acid or a solution containing hydrofluoric acid. A new resist pattern may be formed and then hydrofluoric acid treatment may be performed.

Further, in the case where the structure of the source electrode and the drain electrode is the two-layer structure in which the aluminum layer is formed on the chromium layer as in the first and second embodiments, the chromium layer is The aluminum layer may be formed protruding like an eaves, but the chrome layer is not affected by the cleaning treatment of the silicon layer surface with hydrofluoric acid or a solution containing hydrofluoric acid or hydrogen fluoride gas. , Only the eaves-shaped portion of the aluminum layer is side-etched with hydrofluoric acid or a solution containing hydrofluoric acid or hydrogen fluoride gas to avoid the eaves structure of the source and drain electrodes, and to manufacture a thin film transistor after the process according to the present invention. The coverage of the protective film of the thin film transistor formed in the process can be improved.

[0056]

According to the method of manufacturing a semiconductor device of the first aspect, by cleaning the surface of the semiconductor layer exposed by etching, a metal-semiconductor compound which becomes an etching barrier is formed on the surface of the semiconductor layer. It can be removed, and the subsequent etching of the semiconductor layer can be smoothly performed.

According to the method of manufacturing a thin film transistor of the present invention, the silicon layer exposed by removing a predetermined portion of the metal layer is cleaned to thereby form a metal on the surface of the silicon layer which causes an dead time as an etching barrier.
The silicon compound layer is removed. By eliminating the dead time, reproducibility of the etching time is obtained, so that the etching amount is constant, and the etching time is different on the same substrate due to the difference in the formation state of the metal-silicon compound layer on the same substrate. Since such a phenomenon also disappears, the uniformity of etching is improved. For this reason, the thin film transistor has uniform electric characteristics, and when used in a liquid crystal display device, display unevenness does not occur.

Further, since the phenomenon due to the dead time such as the etching of the silicon layer being insufficient and left behind, or the silicon layer not requiring etching being completely etched, is eliminated, the liquid crystal display device due to the inoperability of the thin film transistor. The defective portion is not generated, and the quality of the liquid crystal display device is improved.

According to the method of manufacturing a thin film transistor according to the third aspect of the present invention, the solution containing hydrogen fluoride is used for cleaning the surface of the silicon layer after removing the metal layer made of the chromium layer. It is not necessary to perform the layer removing operation in vacuum, and the efficiency of the chromium-silicon compound layer removing operation can be improved.

According to the method of manufacturing a thin film transistor of the present invention, the gas containing hydrogen fluoride is used for cleaning the surface of the silicon layer after removing the metal layer made of the chromium layer. The chromium-silicon compound layer can be removed without damaging the.

According to the method of manufacturing a thin film transistor according to claim 5, the silicon layer is formed by using the plasma etching method of the inert gas for cleaning the surface of the silicon layer after removing the metal layer made of the chromium layer. The subsequent process of etching and continuous processing are possible, and the manufacturing process can be simplified. Further, since no chemical liquid is used, it is not necessary to treat the waste liquid, and the cost can be improved.

According to the thin-film transistor manufacturing method of the sixth aspect, when the surface of the silicon layer is subjected to cleaning treatment, portions such as the surface and the end face of the metal layer which are not exposed to the chemical liquid for cleaning are to be treated. By protecting with a mask, the cross-sectional shapes of the source electrode and the drain electrode do not change due to the chemical solution, etc., so that it is possible to effectively manufacture a thin film transistor having a structure in which it is important to maintain the shapes of the source electrode and the drain electrode. be able to.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of a processing procedure of a method of manufacturing a thin film transistor according to the present invention.

FIG. 2 is a flowchart showing an example of a processing procedure of a method of manufacturing a thin film transistor according to the present invention.

FIG. 3 is a flowchart showing steps of a conventional method of manufacturing a thin film transistor.

FIG. 4 is a graph showing a dry etching characteristic of a sample subjected to a buffer hydrofluoric acid treatment according to an example of the present invention.

FIG. 5 is a graph showing the relationship between the processing time of the buffer hydrofluoric acid treatment and the dry etching amount according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the first step of the method of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining the second step of the method of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining a third step of the method of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining the fourth step of the method of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining a fifth step of the method of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining the sixth step of the method of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining the first step of the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining the second step of the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

FIG. 14 is a cross-sectional view for explaining the third step of the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view for explaining the fourth step of the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

FIG. 16 is a cross-sectional view for explaining a fifth step of the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view for explaining the sixth step of the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view for explaining the seventh step of the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

[Explanation of symbols]

 5 Dry etching characteristics of sample with sheet resistance 3 KΩ 6 Dry etching characteristics of sample with sheet resistance 20 KΩ 7 Dead time characteristics 8 Insulating substrate 9 Gate electrode 10 Gate insulating film 11 i-type amorphous silicon 12 n-type amorphous silicon 13 Source electrode (chromium) 14 Gate Electrode (Aluminum) 15 Source Electrode (Chromium) 16 Gate Electrode (Aluminum) 17 Etching Stopper 18 Sheet Resistance 3KΩ Sample Properties 19 Sheet Resistance 20KΩ Sample Properties 20 Electrode Layer

[Procedure amendment]

[Submission date] October 29, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

6 to 11 are sectional views for explaining a first example of a conventional process in manufacturing a thin film transistor. The structure will be described with reference to FIG. 11 which is the final view of the process. An insulating substrate 8 as a substrate for constructing a transistor structure, the base layer is formed by the gate electrode 9 and the Gate insulating film 10. The i-type amorphous silicon 11 is formed on the base layer. An n-type amorphous silicon 12 is formed thereon, and the source electrode 1 is further formed thereon.
3 and 14 and drain electrodes 15 and 16 are formed symmetrically.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

12 to 18 are sectional views for explaining a second example of a conventional process in manufacturing a thin film transistor. The structure will be described with reference to FIG. 18, which is the final view of the process. An insulating substrate 8 as a substrate for constructing a transistor structure, the base layer is formed by the gate electrode 9 and the Gate insulating film 10. An i-type amorphous silicon 11 and an etching stopper 17 for protecting the i-type amorphous silicon 11 are formed on the base layer. An n-type amorphous silicon 12 is formed thereon, and further, source electrodes 13 and 14 and drain electrodes 15 and 16 each composed of two layers are symmetrically formed thereon.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

In FIG. 4, a graph 5 shows the relationship between the dry etching time and the dry etching amount for the sample in which the chromium-silicon compound layer is formed on the amorphous silicon and the sheet resistance is about 20 kΩ . The area indicated by reference numeral 7 in this graph 5 shows the characteristics of dead time. From this graph, it can be seen that etching hardly progresses for a while immediately after the start of etching. Further, in FIG. 4, a graph 6 shows the relationship between the dry etching time and the dry etching amount for the sample in which the chromium-silicon compound layer is formed on the amorphous silicon and the sheet resistance is about 3 kΩ . It can be seen from this graph 6 that when a chromium-silicon compound layer having a sheet resistance of about 3 kΩ is formed, the amorphous silicon is not etched at all.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

A first aspect of a method of manufacturing a thin film transistor according to the present invention is a step of preparing a base layer including a gate electrode and a gate insulating film, which are sequentially stacked on an insulating substrate,
Forming a silicon layer on the underlayer, forming a metal layer on the silicon layer, and etching a source electrode and a drain electrode by removing a predetermined portion of the metal layer by etching. The method includes: a step , a step of cleaning the surface of the silicon layer exposed by removing a predetermined portion of the metal layer, and a step of etching the silicon layer having the surface cleaned.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

According to the fifth aspect of the method of manufacturing a thin film transistor of the present invention, before the step of cleaning the surface of the silicon layer, a step of forming a mask for selectively performing the cleaning is provided. Thus, for example, the source electrode and the drain electrode can be prevented from being affected by the cleaning, so that the cross-sectional shapes of the source electrode and the drain electrode can be maintained.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction content]

The dead time varies depending on the etching amount of each of the unprocessed amorphous silicon on which the chromium-silicon compound layer is not formed and the amorphous silicon on which the chromium-silicon compound layer is formed. It can also be evaluated by using the relative etching amount obtained by comparison. In FIG.
A graph 18 shows the relationship between the buffer hydrofluoric acid treatment time and the relative etching amount for the sample in which the chromium-silicon compound layer is formed on the amorphous silicon and the sheet resistance is about 3 kΩ . A graph 19 shows the relationship between the buffer hydrofluoric acid treatment time and the relative etching amount for a sample in which a chromium-silicon compound layer is formed on amorphous silicon and has a sheet resistance of about 20 kΩ .
When the relative etching amount is 1, the dead time can be approximated to 0. Therefore, in FIG. 5, the buffer having a sheet resistance of about 3 kΩ is about 60 seconds or more, and the sheet resistance of about 20 kΩ is about 20 seconds or more. Dead time is reduced to 0 by hydrofluoric acid treatment, and there is no dead time
It turns out that dry etching of silicon is possible
It

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FIG. 1 is a flowchart showing an example of a processing procedure of a method of manufacturing a thin film transistor according to the present invention.

FIG. 2 is a flowchart showing an example of a processing procedure of a method of manufacturing a thin film transistor according to the present invention.

FIG. 3 is a flowchart showing steps of a conventional method of manufacturing a thin film transistor.

FIG. 4 is a graph showing a dry etching characteristic of a sample subjected to a buffer hydrofluoric acid treatment according to an example of the present invention.

FIG. 5 is a graph showing the relationship between the processing time of the buffer hydrofluoric acid treatment and the dry etching amount according to the embodiment of the present invention.

6 is a sectional view for explaining a first step of the first example of the manufacturing method of the thin film transistor.

7 is a sectional view for explaining the second step of the first example of the manufacturing method of the thin film transistor.

8 is a sectional view for explaining a third step of the first example of a method for manufacturing a thin film transistor.

9 is a sectional view for explaining a fourth step of the first example of a method for manufacturing a thin film transistor.

[10] Fifth first example of a method for manufacturing a thin film transistor
It is sectional drawing for demonstrating a process.

[11] Sixth of the first example of a method for manufacturing a thin film transistor
It is sectional drawing for demonstrating a process.

[12] first in the second example of the method for manufacturing the thin film transistor
It is sectional drawing for demonstrating a process.

[13] The second of the second example of the method for manufacturing the thin film transistor
It is sectional drawing for demonstrating a process.

[14] The third of the second example of the method for manufacturing the thin film transistor
It is sectional drawing for demonstrating a process.

[15] Fourth second example of the method for manufacturing the thin film transistor
It is sectional drawing for demonstrating a process.

[16] Fifth second example of the method for manufacturing the thin film transistor
It is sectional drawing for demonstrating a process.

[17] Sixth second example of the method for manufacturing the thin film transistor
It is sectional drawing for demonstrating a process.

[18] Seventh of the second example of the method for manufacturing the thin film transistor
It is sectional drawing for demonstrating a process.

[Explanation of symbols] 5 dry etching characteristics of a sample having a sheet resistance of 3 kΩ 6 dry etching characteristics of a sample having a sheet resistance of 20 kΩ 7 dead time characteristics 8 insulating substrate 9 gate electrode 10 gate insulating film 11 i-type amorphous silicon 12 n-type amorphous Silicon 13 Source electrode (chrome) 14 Source electrode (aluminum) 15 Drain electrode (chrome) 16 Drain electrode (aluminum) 17 Etching stopper 18 Sheet resistance 3 kΩ sample characteristics 19 Sheet resistance 20 kΩ sample characteristics 20 Chromium metal Layer 21 Aluminum metal layer

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[Figure 4]

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[Figure 5]

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Otani, 997 Miyoshi, Nishigoshi-cho, Kikuchi-gun, Kumamoto Inside Advanced Display Co., Ltd. (72) Masahiro Hayama, 997 Miyoshi, Nishigoshi-cho, Kikuchi-gun, Kumamoto Advanced Company・ In the display

Claims (6)

[Claims] 1. A step of forming a metal layer on a semiconductor layer, a step of selectively etching the metal layer, a step of cleaning the surface of the semiconductor layer exposed by the etching, and a step of cleaning the surface A method of manufacturing a semiconductor device, comprising: 2. A step of preparing a base layer including a gate electrode and a gate insulating film, which are sequentially stacked on an insulating substrate, a step of forming a silicon layer on the base layer, and a step of selecting on the silicon layer. A step of forming a metal layer, a step of forming a source electrode and a drain electrode by removing a predetermined portion of the metal layer by etching, and a step of forming a silicon layer exposed by removing a predetermined portion of the metal layer. A method of manufacturing a thin film transistor, comprising: a step of cleaning a surface; and a step of etching the silicon layer whose surface has been cleaned. 3. The step of forming the metal layer with a chromium layer and cleaning the surface of the silicon layer removes the chromium-silicon compound layer on the surface of the silicon layer using a solution containing hydrogen fluoride. The method for manufacturing a thin film transistor according to claim 2, further comprising: 4. The step of forming the metal layer with a chromium layer and cleaning the surface of the silicon layer removes the chromium-silicon compound layer on the surface of the silicon layer using a gas containing hydrogen fluoride. The method for manufacturing a thin film transistor according to claim 2, further comprising: 5. The step of forming the metal layer with a chromium layer and cleaning the surface of the silicon layer comprises removing the chromium-silicon compound layer on the surface of the silicon layer by sputter etching with an inert gas. The method of manufacturing a thin film transistor according to claim 2, comprising: 6. The method of manufacturing a thin film transistor according to claim 2, further comprising a step of forming a mask for selectively performing the cleaning before the step of cleaning the surface of the silicon layer.