JPH07106585A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To shorten the manufacturing process of a self-alignment thin film transistor, reduce the manufacturing cost, and improve contact characteristics. CONSTITUTION:After an upper protective insulating film 15 of a thin film transistor is patterned in a self-alignment manner by a gate electrode 12, metal or silicide is selectively grown only on the thin film of a semiconductor layer 14, thereby realizing a thin film transistor whose parasitic capacitance is small.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a liquid crystal display, E
The present invention relates to a method of manufacturing a thin film transistor used for an L display or the like.

[0002]

2. Description of the Related Art A conventional self-aligned thin film transistor (hereinafter abbreviated as SA-TFT (S-TFT) will be described with reference to the drawings.
elf-Alighned Thin Film Transistor))).

FIG. 2 is a schematic sectional view of a thin film transistor showing a method of manufacturing a general self-aligned thin film transistor in the order of steps. Substrate 1, gate electrode 2, gate insulating film 3,
The semiconductor film 4, the silicide film 7, the source / drain wiring electrodes (including the diffusion barrier film) 8 and the upper protective film 5 are the main constituent elements. Here, a Cr film is used as the gate electrode 2, a silicon nitride film is used as the gate insulating film 3 and the upper protective film 5, and amorphous silicon (hereinafter, a is used as the semiconductor film 4).
-Si) film, a chrome silicide film as the silicide film 7, and a titanium film (T) as the source / drain wiring electrode 8.
A two-layer film of i) and aluminum film (Al) (the Ti film is a diffusion barrier layer and contacts the silicide film) is used.

Next, the manufacturing process will be described with reference to FIGS. 2 (a), 2 (b), 2 (c) and 2 (d). First, as shown in FIG. 2A, the silicon nitride film of the upper protective film 5 is formed by a normal photolithography process by wet etching with a 1: 6 mixed solution of hydrofluoric acid and ammonium fluoride. At this time, in order to reduce the parasitic capacitance (Cgs) caused by the overlap between the gate electrode 2 and the source / drain wiring electrode 8, the upper protective film 5 is patterned to fill the width of the gate electrode 2 by backside exposure.

Next, a high concentration semiconductor film 4 for ohmic contact is formed by an ion doping method, a plasma CVD method or the like. A Cr film 6 is formed thereon by a sputtering method or the like. Then, as shown in FIG. 2B, a silicide film 7 is formed between the semiconductor film 4 and the Cr film 6 by heat treatment.
To form. After that, when Cr is etched with a Cr etching solution, the silicide film 7 remains without being etched, and the state shown in FIG. 2C is obtained. Next, if the source / drain wiring electrode 8 is formed of a two-layer film such as a titanium film and an aluminum film, the state shown in FIG.
FT is completed. In the TFT having this structure, since the source / drain wiring electrode 8 and the upper protective film 5 can be formed separately from each other, the parasitic capacitance (Cgs) can be reduced (for example, JP-A-63-168052 and JP-A-1). -011368 publication).

[0006]

The conventional manufacturing method as shown in the above example requires three steps of forming a metal film, solid phase growth of silicide by heat treatment, and etching the metal film. Further, structurally, since only the silicide film 7 is a conductive layer between the end portion of the source / drain wiring electrode 8 and the upper protective film 5, the electric resistance of the silicide film 7 is as small as possible, and the electric resistance of the substrate 1 is small. It is required to be homogeneous over the entire surface. However, the silicide film formed by the solid-phase reaction has a small film thickness, it is difficult to realize low resistance, and it remains a practical problem in terms of uniformity and reproducibility.

In view of the above problems, it is an object of the present invention to greatly simplify the manufacturing process of a self-aligned thin film transistor and to provide a manufacturing method of a thin film transistor having a small parasitic capacitance.

[0008]

In order to solve the above problems and achieve the object, the present invention provides a thin film transistor having a gate electrode, a gate insulating film, a semiconductor layer, and an upper protective insulating film, wherein the upper protective insulating film is formed. Is patterned by a gate electrode in a self-aligned manner, and a step of selectively growing a metal or a silicide only on the thin film of the semiconductor layer.

[0009]

In the method of manufacturing a thin film transistor according to the present invention, a technique of selectively growing metal or silicide on a base material is used. Since the conductive layer grows only on the thin film of the semiconductor layer and is not formed on the upper protective insulating film, the contact portion having a low parasitic capacitance can be formed in a self-aligned manner in one step.

According to this method, the manufacturing process of the self-aligned thin film transistor is greatly simplified, and the thin film transistor having good characteristics and good conductivity on the entire surface of the substrate, in which the source / drain wiring electrode portion of the thin film transistor has good conductivity. it can.

As the conductive thin film capable of selective growth, W, Mo, Ta, Nb, Ti, Zr, Hf, Cr, V, Fe,
Metal thin films such as Co, Ni, Cu, Al and Au and thin films of silicide which is a compound of metal and silicon can be used. The most common technique is tungsten hexafluoride
A selective W-CVD technique is known in which a tungsten thin film is selectively grown by plasma CVD using a mixed gas of (WF ₆ ), silane (SiH ₄ ) and hydrogen (H ₂ ). Silane
In some cases, fluorinated silane (SiH ₂ F ₂ ) may be used instead of (SiH ₄ ).

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a thin film transistor according to each embodiment of the present invention will be described below with reference to the drawings. 1 (a), 1 (b) and 1 (c) are schematic sectional views of a thin film transistor showing a method of manufacturing the thin film transistor of the first embodiment of the present invention in the order of steps. Reference numeral 11 is a substrate, 12 is a gate electrode, 13 is a gate insulating film, 14 is a semiconductor layer, 15 is an upper protective insulating film, 16 is a selective CVD film, and 17 is a source / drain wiring electrode. Here, the gate electrode 12 is a Cr film, the gate insulating film 13 and the upper protective insulating film 15 are silicon nitride films, the semiconductor layer 14 is an amorphous silicon film (a-Si), and the selective CVD film 16 is a W thin film. Source / drain wiring electrode
A two-layer film of titanium film and aluminum film was used as 17.

Below, the upper protective insulating film 15 is a plasma CV.
A silicon nitride film formed by the D method, an amorphous silicon film whose semiconductor layer 14 is formed by the plasma CVD method,
Then, the manufacturing method in the case where the source / drain wiring electrode 17 is a two-layer film of a titanium film and an aluminum film formed by the sputtering method will be described in detail.

Positive resist OFPR-800 (Tokyo Oka
After forming a predetermined pattern with a product (manufactured by K.K.), the upper silicon nitride film was dry-etched with a parallel plate type dry etching device (RF power supply 13.56 MHz). As etching gas, CF ₄ is 170 SCCM, CHF ₃ is 30 SCCM and He is 100 S
Introduced CCM, set the pressure to 0.2 Torr, and set the RF power to 2
kW (0.8 W / cm ² ) was input. After etching under these conditions, the resist film was peeled off and washed, and phosphorus (P) as an n-type dopant was implanted in an ion doping apparatus (mass non-separation type). The gas used was PH ₃ diluted with H ₂ and having a concentration of 5%, and was injected under the conditions of an acceleration voltage of 8 kV and a dose amount of 2 × 10 ¹⁵ ions / cm ² . FIG. 1A shows a schematic sectional view at this point.

After that, a tungsten thin film was selectively grown on the high-concentration semiconductor thin film by using a plasma CVD method using a mixed gas of tungsten hexafluoride (WF ₆ ) and silane (SiH ₄ ). The substrate temperature is 250 ° C and the partial pressure of WF ₆ is 4
× 10 ~ ³ Torr, SiH ₄ partial pressure is 1 × 10 ~ ³ Torr, total pressure is 30
× 10 ~ ³ Torr,

[0016]

[Outer 1]

The film forming rate was about 1000Å / min, and 1000Å was formed. FIG. 1B shows a schematic sectional view at this point. The electric resistance of the W thin film is 50 μΩcm, the sheet resistance is 5 Ω / □, and the on resistance Ron of the TFT is Ron>
Since it is 10 ⁵ Ω / □, a sufficiently low value is obtained as the conductive film of the contact portion.

Then, as shown in FIG.
A two-layer film of a titanium film and an aluminum film, which is the drain wiring electrode 17, was formed by sputtering. The etching of the upper silicon nitride film was performed using hydrofluoric acid and ammonium fluoride in a ratio of 1: 6.
You may wet-etch with a mixed solution. In the selective W-CVD process described above, the selectivity may be impaired depending on the type of base and surface conditions such as cleanliness and oxidation degree. In that case, an oxide film having better selectivity than a nitride film may be used as a base, or CVD may be performed after surface modification as shown in the second embodiment. In addition, when the above-mentioned reaction gas contains a gas that is a source of the high-concentration doping impurity element, the above-described step of forming the high-concentration layer by ion doping can be omitted. When the semiconductor layer is Si, BH ₃ and BF ₃ in P type, PH _{3 in} N type,
Select from PF ₃ , AsH _3, etc. Next, a second embodiment will be shown.

[0019]

[Outside 2]

Here, in a plasma CVD reaction vessel,
A step of performing dry etching on the substrate to remove the oxide film on the surface was provided.

CF ₄ / C is used as a dry etching gas.
With the mixed gas of HF ₃ / He, under the conditions used for etching the upper silicon nitride in the first embodiment,
Etched for 10 seconds.

[0022]

[Outside 3]

By the manufacturing method described above, the gate electrode 1
2, gate insulating film 13, semiconductor layer 14 and upper protective insulating film 1
After the step of patterning the upper protective insulating film 15 in a self-aligned manner with the gate electrode 12 of the thin film transistor having 5, the metal or the silicide is selectively grown only on the thin film of the semiconductor layer 14, and the parasitic capacitance is small. Realize a thin film transistor.

Although the amorphous silicon film is used as the semiconductor layer, it is obvious that the same effect can be expected even if the film is a polycrystalline silicon film. In addition to the W film as a metal, as a conductive thin film capable of selective growth, Mo, T
a, Nb, Ti, Zr, Hf, Cr, V, Fe, Co, Ni, C
A metal thin film of u, Al, Au or the like and a thin film of a silicide which is a compound of metal and silicon can be used. Also, CV
In addition to fluorides such as WF ₆ and MoF ₆ , carbonyls such as W (CO) ₆ and Al (CH ₃ ) ₃ and Al (C
_{H 3) 2 H, Al (} O-iso-C 3 H 7) 3, Zr (O-iso-C
_{3 H 7) 4, Fe (} C 5 H 5) 2, Co (C 5 H 5) organometallic compounds such as _2, alkoxide, metallocenes such as can be used. Further, chlorides such as WCl ₆ , MoCl ₅ , and TiCl ₄ can also be used. Although silane reduction was used as the reducing action in the above examples, it is not limited to SiH ₄ , and disilane Si ₂ H ₆ , fluorosilane SiHF ₃ , SiH ₂ F _2, or the like may be used, or H ₂ , NH. _{3, N 2 H 2, NF} 3 may be reduced in like. It is also possible to use silicide, which is a compound of metal and silicon, as the conductive thin film capable of selective growth. In the case of the first embodiment described above, when the SiH ₄ / WF ₆ ratio is increased, the Si content is increased and a silicide film is obtained. However, since the selectivity decreases, SiH ₄ / W
Select an F ₆ ratio of 1 or less.

[0025]

As described above, according to the manufacturing method of the present invention, the upper protective insulating film of the thin film transistor having the gate electrode, the gate insulating film, the semiconductor layer, and the upper protective insulating film is patterned by the gate electrode in a self-aligned manner. After the step of forming a thin film, a metal or a silicide is selectively grown only on the thin film of the semiconductor layer to realize a thin film transistor having a small parasitic capacitance.

By this method, the manufacturing process of the self-aligned thin film transistor is greatly simplified, and the thin film transistor having good characteristics and good uniformity in the source / drain wiring electrode portions of the thin film transistor is formed. it can. As a result, a short channel SA-TFT with a small parasitic capacitance was realized, and the display quality of the active matrix LCD could be improved.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a thin film transistor showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention in process order.

FIG. 2 is a schematic cross-sectional view of a thin film transistor showing a conventional method for manufacturing a general self-aligned thin film transistor in process order.

[Explanation of symbols]

11 ... Substrate, 12 ... Gate electrode, 13 ... Gate insulating film,
14 ... Semiconductor layer, 15 ... Upper protective insulating film, 16 ... Select CV
D film, 17 ... Source / drain wiring electrode.

Claims (3)

[Claims] 1. A gate electrode, a gate insulating film, a semiconductor layer,
And a step of patterning the upper protective insulating film in a self-aligned manner with a gate electrode of a thin film transistor having an upper protective insulating film, and a step of selectively growing a metal or a silicide only on the thin film of the semiconductor layer. A method of manufacturing a thin film transistor, comprising: 2. The thin film of the semiconductor layer is an amorphous silicon film, and after forming a high concentration layer for ohmic contact by ion implantation, tungsten hexafluoride (WF ₆ ), silane (SiH ₄ ), and hydrogen (H ₂ ) are formed. 2. The method for manufacturing a thin film transistor according to claim 1, wherein the tungsten thin film is selectively grown on the thin film of the high-concentration semiconductor layer by using the CVD method using the mixed gas of. 3. A step of etching a natural oxide film on the thin film of the semiconductor layer before the step of selectively growing a metal or a silicide only on the thin film of the semiconductor layer. Item 3. A method of manufacturing a thin film transistor according to Item 1 or 2.