JPS6043858A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6043858A JPS6043858A JP15264983A JP15264983A JPS6043858A JP S6043858 A JPS6043858 A JP S6043858A JP 15264983 A JP15264983 A JP 15264983A JP 15264983 A JP15264983 A JP 15264983A JP S6043858 A JPS6043858 A JP S6043858A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- layer
- high melting
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010408 film Substances 0.000 claims abstract description 57
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 3
- 229910052758 niobium Inorganic materials 0.000 claims abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 claims abstract 3
- 238000000034 method Methods 0.000 claims description 14
- 230000008018 melting Effects 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 30
- 239000011229 interlayer Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000001947 vapour-phase growth Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000010936 titanium Substances 0.000 abstract description 4
- 239000010955 niobium Substances 0.000 abstract description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 abstract description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 239000011733 molybdenum Substances 0.000 abstract description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052715 tantalum Inorganic materials 0.000 abstract description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract 2
- 239000010937 tungsten Substances 0.000 abstract 2
- 229910000838 Al alloy Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 229910000714 At alloy Inorganic materials 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001805 chlorine compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、電極配線層としてアルミニウム（ＡＡ ）膜
若しくはＡＡを主成分とする合金膜を用いた半導体装置
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device using an aluminum (AA) film or an alloy film containing AA as a main component as an electrode wiring layer.
従来、半導体装置の電極配線層とし２ては、スパッタリ
ング法により被着したＡｔ膜が広く使われている。第１
図はＡｔ配線を用いた２層配線構造を示す素子断面図で
ある。シリコン基板１１中に拡散領域１２を設けた後、
絶縁膜１３を形成し、コンタクトホール１４をあけて第
１層目のＡｔ配線層１５を形成する。次いで、層間の絶
縁膜１６を堆積させ、スルーホール１７をあけて第２層
目のＡｔ配線層１８を形成して２層配線構造が構成され
ている。Conventionally, an At film deposited by a sputtering method has been widely used as the electrode wiring layer 2 of a semiconductor device. 1st
The figure is a cross-sectional view of an element showing a two-layer wiring structure using At wiring. After providing the diffusion region 12 in the silicon substrate 11,
An insulating film 13 is formed, a contact hole 14 is made, and a first At wiring layer 15 is formed. Next, an interlayer insulating film 16 is deposited, and a through hole 17 is formed to form a second At wiring layer 18, thereby forming a two-layer wiring structure.
このよう外構造を得る場合、層間絶縁膜１６は通常４０
０〔℃〕程度に基板を加熱して気相成長法によシ形成す
る。この際、第１層目のＡｔ配線層１５上には局部的に
突起（ヒロック）１９を生じ易い。このヒロック１９は
、層間絶縁膜１６の異常成長を引きおこす要因となシ、
その結果絶縁膜１６の機械的強度が弱くなシフラック２
０を生ずる。クラック２０は層間絶縁膜１６上の第２層
目のＡｔ配線層１８と第１層目のＡｔ配線層１５との間
の電気的短絡の原因となったシ、クラックを通しての水
の浸入などによるＡｔ配線の腐食を引き起こすため、Ａ
ｔ配線の信頼性を著しく低下させる。When obtaining such an external structure, the interlayer insulating film 16 usually has a thickness of 40 mm.
The substrate is heated to about 0° C. and formed by vapor phase growth. At this time, protrusions (hillocks) 19 are likely to be locally formed on the first At wiring layer 15. This hillock 19 is a factor that causes abnormal growth of the interlayer insulating film 16.
As a result, the mechanical strength of the insulating film 16 is weak.
yields 0. The crack 20 is caused by an electrical short circuit between the second At wiring layer 18 on the interlayer insulating film 16 and the first At wiring layer 15, or by water intrusion through the crack. Because it causes corrosion of At wiring,
This significantly reduces the reliability of the t-wiring.
一方、半導体集積回路では素子の微細化及び高集積化に
伴ないＡｔ配線幅は２〔μｍ〕から１〔μｍ〕へと益々
微細化の方向にある。このよう々微細Ａｔ配線では必然
的に電流密度が高くなるため、エレクトロマイグレーシ
ョンによる断線が大きな信頼性低下の一因となる。On the other hand, in semiconductor integrated circuits, the At wiring width is becoming smaller and smaller from 2 [μm] to 1 [μm] as elements become smaller and more highly integrated. Since the current density is inevitably high in such fine At wiring, disconnection due to electromigration becomes a cause of a large decrease in reliability.
Ａｔ配線のヒロック及びエレクトロマイグレーション防
止対策としては、従来いくつかの方法か提案されている
。例えばＡＡ中に数％のＣｕを含有させた合金膜によシ
ヒロック及びエレクトロマイグレーションを防止する方
法があるが、この方法はＡｔ配線の微細化に対して十分
でない。Several methods have been proposed to prevent hillocks and electromigration in At wiring. For example, there is a method of preventing Schichlock and electromigration by using an alloy film containing several percent of Cu in AA, but this method is not sufficient for miniaturization of At wiring.
また、Ａｔ配線層の中間或いは表面にＴ ｉ ＋ Ｃｒ
、Ｖなどの金属丑たはそれらの硅化物を設ける方法が提
案されている。この方法はエレクトロマイグレーション
防止の効果はおるが、ヒロック防止の点では、Ａ７配線
の側面が被覆されていないため、Ａｔ配線の側面にヒロ
ックが発生し、配線間及び配線層間の電気的絶縁性が十
分でない。また、素子の微細化に伴なって、コンタクト
ホール１４及びスルーホール１７のサイズも微細化する
必要があシ、必然的に急峻な深い穴となるため、スパッ
タリング法によ）被着したＡｔ膜の被覆性が悪くなる。In addition, Ti + Cr is added in the middle or on the surface of the At wiring layer.
, V, or their silicides have been proposed. Although this method has the effect of preventing electromigration, in terms of hillock prevention, since the sides of the A7 wiring are not coated, hillocks will occur on the sides of the At wiring, and the electrical insulation between wirings and wiring layers will deteriorate. not enough. In addition, with the miniaturization of elements, the size of the contact hole 14 and the through hole 17 must also be miniaturized, which inevitably results in steep and deep holes. coverage becomes poor.
このため、エレクトロマイグレーションによる断線が生
じ易個］、配線の信頼性が著しく低下する等の問題があ
った。For this reason, there are problems such as wire breakage due to electromigration and wiring reliability being significantly reduced.
本発明の目的は、Ａｔ膜やＡｔ合金膜等からなる配線層
のヒロックの発生を抑制し、剛エレクトロマイグレーシ
ョン特性を向上させると共に微細な接続孔に対しても高
い信頼性を有する配線層を実現し得る半導体装置の製造
方法を提供することにある。The purpose of the present invention is to suppress the occurrence of hillocks in wiring layers made of At films, At alloy films, etc., to improve rigid electromigration characteristics, and to realize wiring layers that have high reliability even with minute connection holes. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be manufactured by using a semiconductor device.
本発明の骨子は、配線層の表面を高融点金属によって被
覆することにある。The gist of the present invention is to coat the surface of the wiring layer with a high melting point metal.
すなわち本発明は、半導体装置の製造方法において、Ａ
ｔＨＪ？Ａｔ合金膜等を所楚の配線パターンに加工した
後、該配線パターンの露出表面にのみ高融点金屑薄膜を
選択気相成長によって形成せしめるようにした方法であ
る。That is, the present invention provides a method for manufacturing a semiconductor device in which A.
tHJ? In this method, after processing an At alloy film or the like into a predetermined wiring pattern, a high melting point gold scrap thin film is formed only on the exposed surface of the wiring pattern by selective vapor phase growth.
本発明によれば、Ａｔ膜やＡｔ合金膜等からなる配線パ
ターンの露出表面を高融点金属薄膜で完全に被覆してい
るため、Ａｔ配線のヒロック発生を完全に抑制し、耐エ
レクトロマイグレーション特性を大幅に向上することが
できる。しかも、高融点金属薄膜を気相成長法によって
形成するため、微細な接続孔のＡＡ配綜上にも一様な厚
さに高融点薄膜を被着することができ、接続部での配線
の信頼性が大幅に改善できる。さらに、高融点金属はＡ
ｔに比べて耐食性に優れているため、配線の副食性も改
善できる。したがって、化わ′Ｊ性の高い微細なＡｔ配
線を形成することができ、半導体製造技術分野における
有用性は絶大である。According to the present invention, since the exposed surface of the wiring pattern made of At film, At alloy film, etc. is completely covered with a high melting point metal thin film, the occurrence of hillocks in At wiring is completely suppressed, and the electromigration resistance is improved. can be significantly improved. Moreover, since the high melting point metal thin film is formed by vapor phase growth, it is possible to deposit the high melting point thin film to a uniform thickness even on the AA helix of the minute connection holes, and the wiring at the connection part can be easily formed. Reliability can be significantly improved. Furthermore, the high melting point metal is A
Since it has superior corrosion resistance compared to t, it can also improve the side corrosion of wiring. Therefore, it is possible to form a fine At wire with high warpability, and its usefulness in the field of semiconductor manufacturing technology is enormous.
以下、本発明の詳細を図示の実施例によって説明する。 Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第２図（ａ）〜（ｃ）は本発明の一実施例に係わる半導
体装置製造を示す断面図である。先ず、第２（、）に示
す如く、例えはｐ形シリコン基板２１の所定領域に砒素
（Ａｓ）等の不純物をイオン注入して熱処理を行ないｎ
型拡散層２２を形成した仮、全面に絶縁膜２３として例
えば５ｌｏ２膜或いはＰＳＧ膜（リンシリケートガラス
）を気相成長法力とによシ被着する。続いて、この絶縁
膜２３の所定個所に写真食刻法及び反応性イオンエツチ
ング法を用いコンタクトホール２４をアケ、Ａｔ膜（着
しくはＡｔを主成分とするＣｕ或いはＳｉとのＡｔ合金
膜）２５をスパッタ法によ、９０．５〜１．０〔μｍ〕
の厚□さで形成し、写真食刻法と反応イオンエツチング
法とによりＡｔ膜２５を所定の配線パターンに加工する
。FIGS. 2(a) to 2(c) are cross-sectional views showing the manufacture of a semiconductor device according to an embodiment of the present invention. First, as shown in the second part (,), for example, an impurity such as arsenic (As) is ion-implanted into a predetermined region of the p-type silicon substrate 21, and heat treatment is performed.
After forming the type diffusion layer 22, an insulating film 23, such as a 5LO2 film or a PSG film (phosphosilicate glass), is deposited on the entire surface by vapor deposition. Subsequently, contact holes 24 are formed in predetermined locations of this insulating film 23 using photolithography and reactive ion etching, and an At film (or an At alloy film with Cu or Si whose main component is At) is formed. 25 by sputtering method, 90.5 to 1.0 [μm]
The At film 25 is formed into a predetermined wiring pattern by photolithography and reactive ion etching.
次いで、第２図（ｂ）に示す如（Ａｔ配線パターンの露
出表面のみに、例えば六弗化タングステン（Ｗ６）ガス
とＨ２ガスを用いた気相成長法にょ９ タンガスｆ ｙ
（Ｗ） 膜２６ ヲ２００〜２０００ＣＸ：］の厚さ
に被着し、第１の配線層を形成する。この時のＷ膜２６
の被着条件としては基板温度２５０℃〜４００［：ｕ）
、反応炉内の圧力ｌＸｌ０−２〜７６０ （Ｔｏｒｒ
） 、 ＷＦ６ガスの分圧１ ｘ １０−’〜５ ｘ
１０−２（Ｔｏｒｒ ）の範囲が望ましい。また、Ｗ膜
２６を被着する際の基板温度はこの工程でのＡｔヒロッ
クの発生を防止するために３５０Ｃ℃）以下が望ましい
。さらに、Ｗ膜厚を２ｏｏ０１：Ｘ）以上にすると絶縁
Ｍ２３の表面にもＷ粒子が局部的に成長するため、Ｗ膜
厚は２０００［Ｘ）以下が望ましい。Next, as shown in FIG. 2(b), only the exposed surface of the At wiring pattern is grown using a vapor phase growth method using, for example, tungsten hexafluoride (W6) gas and H2 gas.
(W) Film 26 is deposited to a thickness of 200 to 2000 CX: to form a first wiring layer. At this time, the W film 26
The deposition conditions are a substrate temperature of 250°C to 400°C [:u)
, the pressure in the reactor lXl0-2~760 (Torr
), Partial pressure of WF6 gas 1 x 10-' ~ 5 x
A range of 10-2 (Torr) is desirable. Further, the substrate temperature when depositing the W film 26 is desirably 350° C. or less in order to prevent the occurrence of At hillocks in this step. Furthermore, if the W film thickness is 2oo01:X) or more, W particles will locally grow on the surface of the insulation M23, so the W film thickness is preferably 2000[X) or less.
次に、第２図（、）に示す如く第１の配線層上に層間絶
島膜２７として例えばプラズマＣＶＤ法などによシＳｉ
Ｏ□膜２２を０．８〜１〔μｍ〕形成後、写真食刻法と
反応性イオンエツチング法とによシスルーホール２８を
設ける。続いて、第１層Ａｔ配線パターンを形成したの
と同様にして、第２層Ａｔ配線パターンを形成する。か
くして２層Ａｔ配線構造が実現されることになる。尚第
２図中２９はＡｔ膜３０はＷ膜を示している。Next, as shown in FIG. 2(a), an interlayer isolated film 27 of Si is formed on the first wiring layer by, for example, plasma CVD.
After forming the O□ film 22 to a thickness of 0.8 to 1 μm, a through-hole 28 is formed by photolithography and reactive ion etching. Subsequently, a second layer At wiring pattern is formed in the same manner as the first layer At wiring pattern was formed. In this way, a two-layer At wiring structure is realized. Note that 29 in FIG. 2 indicates that the At film 30 is a W film.
このようにして得られた２層Ａｔ配線構造は第１層目の
配線層上にヒロックが生じないため配線層間の電気的絶
縁性は破壊電圧が６００〜ＳＯＯ〔■〕、リーク電流が
Ｉ Ｘ １０−１３（Ａ）以下（２０Ｖ印加において）
で、従来のものに比して大幅に改善された。また、この
ヒロックの防止によって眉間絶縁膜のクラック等の欠陥
もなくなシ、さらにＡｔの露出表面全体を完全にＷ膜で
被覆しているため、配線の腐食などの不良も全くなくな
った。ｔた、エレクトロマイグレーションにより生ずる
断線不良も大幅に改善され、配線寿命が従来に比べて約
１桁長くなり、ｉ Ｃｐｔｎ〕の微細配線幅での信頼性
が飛躍的に向上した。これはＡｔを・ぐターンユング後
に被覆特性の優れた気相成長法によシＡｔ表面を一様な
厚さのＷ膜で被覆している効果が、１〔μｍ〕と言う微
細配線部及び１〔μｍ口〕の微細コンタクトホール、ス
ルーホール部で顕著に現われることによる。In the two-layer At wiring structure thus obtained, no hillocks occur on the first wiring layer, so the electrical insulation between the wiring layers has a breakdown voltage of 600~SOO [■] and a leakage current of IX. 10-13(A) or less (at 20V applied)
This is a significant improvement over the previous version. Moreover, by preventing hillocks, there are no defects such as cracks in the glabellar insulating film, and since the entire exposed surface of At is completely covered with the W film, defects such as corrosion of wiring are completely eliminated. In addition, disconnection defects caused by electromigration have been greatly improved, the wiring life has been extended by about an order of magnitude compared to the conventional method, and the reliability of iCptn in fine wiring widths has been dramatically improved. This is due to the fact that the At surface is coated with a W film of uniform thickness by the vapor phase epitaxy method with excellent coating properties after turning the At. This is because it appears conspicuously in fine contact holes and through-holes of 1 [μm diameter].
なお、本発明は上述した実施例に限定されるものではな
い。例えに、上記実施例では２層配線について述べたが
１層配線或いは３層以上の多層配線に適用しても同様な
効果が得られる。Note that the present invention is not limited to the embodiments described above. For example, in the above embodiment, a two-layer wiring was described, but the same effect can be obtained even if the invention is applied to a single-layer wiring or a multilayer wiring of three or more layers.
また、配線材料はＡｔに限るものではなく、Ａｔを主成
分とするＡｔ合金展であってもよい。また、上記実施例
では高融点金属膜としてＷＦ６ガスによるＷ膜の気相成
長を用いた場合について説明したが、モリブデン（Ｍｏ
）、ニオブ（Ｎｂ）、タンタル（Ｔａ）或いはチタン（
Ｔｉ）の弗化物による気相成長膜を用いても同様の効果
が得られる。Further, the wiring material is not limited to At, and may be an At alloy containing At as a main component. Further, in the above embodiment, a case was explained in which vapor phase growth of a W film using WF6 gas was used as a high melting point metal film, but molybdenum (Mo
), niobium (Nb), tantalum (Ta) or titanium (
A similar effect can be obtained by using a vapor-phase grown film of Ti fluoride.
さらに、これらの金属の塩化物を利用してもよい。その
他、本発明の要旨を逸脱しない範囲で、種々変形して実
施することができる。Furthermore, chlorides of these metals may also be used. In addition, various modifications can be made without departing from the gist of the present invention.
第１図は従来の製造方法による素子構造を示す断面図、
第２図（ａ）〜（ｃ）は本発明の一実施例を説明するた
めの工程断面図である。
１１．２１・・シリコン基板、１２．２２・・・拡散層
、１３．２３・・・絶縁膜、１４．２４・・・コンタク
トホール、１５．１８．２５．２９・・・Ａｔ膜、１６
゜２７・・・層間１１１！！緑膜、１７．２８・・・ス
ルーホール、２６．３０・・・Ｗ膜。FIG. 1 is a cross-sectional view showing the device structure according to the conventional manufacturing method.
FIGS. 2(a) to 2(c) are process cross-sectional views for explaining one embodiment of the present invention. 11.21...Silicon substrate, 12.22...Diffusion layer, 13.23...Insulating film, 14.24...Contact hole, 15.18.25.29...At film, 16
゜27...Interlayer 111! ! green membrane, 17.28... through hole, 26.30... W membrane.
Claims (2)
する合金膜からなる配線層を有する半導体装置の製造方
法において、前記配線層の表面を選択気相成長法によっ
て形成した高、融点金属薄膜で完全に被覆したことを特
徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device having a wiring layer made of an aluminum film or an alloy film mainly composed of aluminum, the surface of the wiring layer is completely covered with a high melting point metal thin film formed by selective vapor deposition. A method for manufacturing a semiconductor device, characterized in that:
Ｔａ或いはＴｉｉ用いることを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。(2) As the high melting point metal film, W, Mo, Nb,
The method for manufacturing a semiconductor device according to claim 1, characterized in that Ta or Tii is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15264983A JPS6043858A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15264983A JPS6043858A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6043858A true JPS6043858A (en) | 1985-03-08 |
Family
ID=15545032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15264983A Pending JPS6043858A (en) | 1983-08-22 | 1983-08-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043858A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62290153A (en) * | 1986-06-06 | 1987-12-17 | Yokogawa Hewlett Packard Ltd | Manufacture of multilevel metallic integrated circuit |
| JPS62291948A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | Metal thin film miring and manufacture thereof |
| JPS63133648A (en) * | 1986-11-10 | 1988-06-06 | エイ・ティ・アンド・ティ・コーポレーション | Tungsten covering |
| JPS63185045A (en) * | 1987-01-28 | 1988-07-30 | Mitsui Mining & Smelting Co Ltd | Conductive film circuit |
| JPS63318139A (en) * | 1987-06-19 | 1988-12-27 | Matsushita Electric Ind Co Ltd | Metallic thin film wiring |
| JPS648645A (en) * | 1987-06-30 | 1989-01-12 | Nec Corp | Semiconductor integrated circuit |
| JPS6451445A (en) * | 1987-08-21 | 1989-02-27 | Toyo Boseki | Porous polyester chip |
| JPH01501985A (en) * | 1986-07-31 | 1989-07-06 | アメリカン テレフォン アンド テレグラフ カムパニー | Semiconductor devices with improved metallization |
| JPH0235753A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH02168651A (en) * | 1988-12-21 | 1990-06-28 | Nec Yamagata Ltd | Manufacture of semiconductor device |
| JPH02184824A (en) * | 1989-01-10 | 1990-07-19 | Fujitsu Ltd | Thin-film transistor matrix |
| JPH02312236A (en) * | 1989-05-26 | 1990-12-27 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH0372318A (en) * | 1989-08-11 | 1991-03-27 | Sharp Corp | Active matrix display device |
| JP2009224485A (en) * | 2008-03-14 | 2009-10-01 | Toyota Central R&D Labs Inc | Diode and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5467766A (en) * | 1977-11-10 | 1979-05-31 | Toshiba Corp | Semiconductor device |
| JPS5979550A (en) * | 1982-10-29 | 1984-05-08 | Hitachi Ltd | Manufacture of wiring structure |
-
1983
- 1983-08-22 JP JP15264983A patent/JPS6043858A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5467766A (en) * | 1977-11-10 | 1979-05-31 | Toshiba Corp | Semiconductor device |
| JPS5979550A (en) * | 1982-10-29 | 1984-05-08 | Hitachi Ltd | Manufacture of wiring structure |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62290153A (en) * | 1986-06-06 | 1987-12-17 | Yokogawa Hewlett Packard Ltd | Manufacture of multilevel metallic integrated circuit |
| JPS62291948A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | Metal thin film miring and manufacture thereof |
| JPH01501985A (en) * | 1986-07-31 | 1989-07-06 | アメリカン テレフォン アンド テレグラフ カムパニー | Semiconductor devices with improved metallization |
| JPS63133648A (en) * | 1986-11-10 | 1988-06-06 | エイ・ティ・アンド・ティ・コーポレーション | Tungsten covering |
| JPS63185045A (en) * | 1987-01-28 | 1988-07-30 | Mitsui Mining & Smelting Co Ltd | Conductive film circuit |
| JPS63318139A (en) * | 1987-06-19 | 1988-12-27 | Matsushita Electric Ind Co Ltd | Metallic thin film wiring |
| JPS648645A (en) * | 1987-06-30 | 1989-01-12 | Nec Corp | Semiconductor integrated circuit |
| JPS6451445A (en) * | 1987-08-21 | 1989-02-27 | Toyo Boseki | Porous polyester chip |
| JPH0235753A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH02168651A (en) * | 1988-12-21 | 1990-06-28 | Nec Yamagata Ltd | Manufacture of semiconductor device |
| JPH02184824A (en) * | 1989-01-10 | 1990-07-19 | Fujitsu Ltd | Thin-film transistor matrix |
| JPH02312236A (en) * | 1989-05-26 | 1990-12-27 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH0372318A (en) * | 1989-08-11 | 1991-03-27 | Sharp Corp | Active matrix display device |
| JP2009224485A (en) * | 2008-03-14 | 2009-10-01 | Toyota Central R&D Labs Inc | Diode and method of manufacturing the same |
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