JPS5979550A - Manufacture of wiring structure - Google Patents

Manufacture of wiring structure

Info

Publication number
JPS5979550A
JPS5979550A JP18904582A JP18904582A JPS5979550A JP S5979550 A JPS5979550 A JP S5979550A JP 18904582 A JP18904582 A JP 18904582A JP 18904582 A JP18904582 A JP 18904582A JP S5979550 A JPS5979550 A JP S5979550A
Authority
JP
Japan
Prior art keywords
wiring
aluminum
thickness
layer
intermetallic compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18904582A
Other languages
Japanese (ja)
Inventor
Kenji Hinode
憲治 日野出
Hiroji Saida
斎田 広二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18904582A priority Critical patent/JPS5979550A/en
Publication of JPS5979550A publication Critical patent/JPS5979550A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a wiring of high reliability by forming an intermetallic compound in uniform and sufficient thickness containing the side surface of an Al wiring, omitting an etching process and simplifying processes while eliminating problems caused by etching. CONSTITUTION:The Al wiring 3 in approximately 1mum thickness is formed on an Si substrate 1 with an SiO2 film 2, WF6+H2 are mixed into N2 gas, and W4 is applied selectively in the thickness of 300Angstrom . Most of W reacts with Al through treatment at 450 deg.C and an intermetallic compound layer is formed to the surface of the wiring 3, and the corrosion resistance and electromigration resistance of the wiring can be improved. Layer thickness coated hardly depend upon directions because of a CVD method, and the side surface of the wiring, particularly, only an Al surface, can also be coated with the metallic layer in uniform and sufficient thickness. Accordingly, a problem to be caused with the removal of a metal being not reacted can be avoided.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は集積回路素子等の配線構造体の製造法に関する
もので、配線の耐食性、耐エレクトロマイグレーション
性を改善するために、化学気相堆積法によって配線表面
に選択的にタングステン等の異種全域を被着させるもの
である。熱処理によって合金贋金形成すると更に特性が
向上する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a wiring structure such as an integrated circuit element. This method selectively deposits a different material such as tungsten over the entire surface of the wiring. The properties are further improved when the alloy is formed by heat treatment.

〔従来技術〕[Prior art]

公知ではないが先行技術として、アルミニウム配線k 
ハターンニング後、基板全面にバナジウムを蒸着し、熱
処理によってアルミニウム配線の表面に合金贋金形成さ
せた仮、未反応のバナジウムを除去するという技術があ
る。しかし、この方法には次に示すような改良すべき問
題点がある。1)バナジウム層を蒸着法で形成するため
、アルミニウム配線側面のバナジウム層が、配線上面に
比べて薄くなる。また配線パターンの形状、捷たけ蒸着
法によっては、側面にバナジウムがほとんど被着しない
場合がある。これl−1:配線の信頼性全低下させる。
Although not publicly known, as a prior art, aluminum wiring k
After patterning, there is a technique in which vanadium is vapor-deposited over the entire surface of the substrate, and the temporary, unreacted vanadium formed on the surface of the aluminum wiring by heat treatment is removed. However, this method has the following problems that should be improved. 1) Since the vanadium layer is formed by vapor deposition, the vanadium layer on the side surface of the aluminum wiring is thinner than the top surface of the wiring. Further, depending on the shape of the wiring pattern and the evaporation method used, vanadium may hardly be deposited on the side surfaces. This l-1: The reliability of wiring is completely reduced.

2)バナジウム蒸着、熱処理、未反応バナジウム除去と
工程が多い。3)未反応バナジウムの除去が難しい。金
属間化合物と未反応金属とで十分な選択性があり、基板
上のシリコン酸化膜舌金はとんどエッチしないエツチン
グを施すのが灯しい。
2) There are many steps including vanadium vapor deposition, heat treatment, and removal of unreacted vanadium. 3) It is difficult to remove unreacted vanadium. It is best to perform etching that has sufficient selectivity between intermetallic compounds and unreacted metals and hardly etch the silicon oxide film tongue on the substrate.

〔発明の目的〕[Purpose of the invention]

本発明の目的は次の点にある。■)側面を含む配線の表
面に、均一で十分な厚さの金属r■」化合物層を形、成
し、2)エツチング工程をイ・要にして工程を簡単にす
ると同時に、エツチングに起因する問題を避け、イハ頼
性の茜い配線の製造方法全提供する。
The purpose of the present invention is as follows. ■) Forming and forming a metal compound layer of uniform and sufficient thickness on the surface of the wiring including the side surfaces, and (2) Simplifying the process by making the etching process a key point, and at the same time eliminating the effects caused by etching. To avoid problems and provide a completely reliable manufacturing method for deep red wiring.

〔発甲]のI几1発〕 1)化学気相堆積法では、被着される層の厚さが、はと
んと方向に依らない。これを利用すればパターンニング
したアルミニウム配線の側面にも均一で十分な厚さの金
属層を設けることが容易である。
[1 shot of I-Ko] 1) In the chemical vapor deposition method, the thickness of the deposited layer does not depend on the direction. By utilizing this, it is easy to provide a uniform and sufficiently thick metal layer on the side surfaces of patterned aluminum wiring.

2)さらに、この方法ではアルミニウム配線の表面(側
面を含む)だけに金属層全被着させることができる。し
たがって未反応金属の除去に伴う問題を避けることがで
きる。すなわち、アルミニウムもしくd、アルミニウム
合金配線上に、選択的化学気相堆積法によシ、第二の異
種金属を形成させ、次いでその界面に金属間化合物層を
形成させるものである。
2) Furthermore, with this method, the entire metal layer can be deposited only on the surface (including the side surfaces) of the aluminum wiring. Problems associated with removing unreacted metals can therefore be avoided. That is, a second dissimilar metal is formed on the aluminum or aluminum alloy wiring by selective chemical vapor deposition, and then an intermetallic compound layer is formed at the interface thereof.

〔発明の実施例〕 以下、本発明を実施例を用いて説明する。[Embodiments of the invention] The present invention will be explained below using examples.

実施例1 第1図に示すようなシリコン酸化膜2全形成したシリコ
ン基板1上に、真壁蒸着法によシ、約1μm厚のアルミ
ニウム膜3を形成し、通常のフォトエツチング法により
、第2図に示すような配線パターン3を侍た。この基板
に、選択的化学気相堆積法によシ第3図のようにタング
ステン4を300人の厚さに被着した。披着東件は次の
通りであった。窒素ガスに、反応ガス、六弗化タングス
テンガス、及び水素ガスヲ混入して反応省に通じた。管
内圧力を約0.ITorr、温度全450Cに保って反
応させたところ、5分間で300人のタングステンをア
ルミニウム表面だけに選択的に被着させることができた
。配線側面部のタングステンj漠の厚ぢは、上面におけ
乙ものとほぼ同じであった。反応ガスを止め被着全停止
した後、継続(2て450CQ・−″、1時間昏゛ち、
アルミニウム・とタングステンの合金化を行なった。こ
の処理により、被着したタングステンの大部分はアルミ
ニウムと反応し、アルミニウム配線の表面に金属間化合
物層が形成さtた。
Example 1 On a silicon substrate 1 on which a silicon oxide film 2 as shown in FIG. A wiring pattern 3 as shown in the figure was prepared. Tungsten 4 was deposited on this substrate to a thickness of 300 mm by selective chemical vapor deposition as shown in FIG. The case presented was as follows. Nitrogen gas was mixed with reaction gas, tungsten hexafluoride gas, and hydrogen gas and passed to the reaction chamber. Reduce the pressure inside the pipe to approximately 0. When the reaction was carried out while maintaining the temperature at a total temperature of 450 C, it was possible to selectively deposit 300 tungsten particles only on the aluminum surface in 5 minutes. The thickness of the tungsten layer on the side surface of the wiring was almost the same as that on the top surface. After stopping the reaction gas and completely stopping the deposition, continue (2 to 450CQ・-'', stand still for 1 hour,
Alloying of aluminum and tungsten was carried out. Through this treatment, most of the deposited tungsten reacted with aluminum, and an intermetallic compound layer was formed on the surface of the aluminum wiring.

アルミニウム配線上なタングステンヲ選択的に成長させ
ることのできる条件は次のようなものであることがわか
った。簡単に制御できる条件として、温度、圧力、水素
ガス流量、六弗化タングステンガス流量、がある。この
中で選択成長の条件は2つのガス水素ガスおよび六弗化
タングステンガスの流量に強く依存し、流量がある範囲
内にあるとき選択成長が起こる。実験に使用した、直径
10crr1、長さ220(771の炉の場合は以下の
通りである。温度450 C1圧力(搬送ガスは窒素)
0.1Torrにおいて、六弗化タングステンガスの流
量が126cm3/分のとき、水素ガス流量10〜40
crn3/分の範囲で選択成長が起こる。六弗化タング
ステンガス流量を減らすと、水素ガス流量の範囲は狭く
なシ、六弗化タングステンの流量が3077713/分
の場合、水素ガスの範囲は10〜13c!n3/分とな
る。温度への依存は弱い。温度を下げると選択成長の範
囲は、水素ガス流量の多い側へ移動し、成長速度が急激
に減少する。
It has been found that the conditions under which tungsten can be selectively grown on aluminum wiring are as follows. Conditions that can be easily controlled include temperature, pressure, hydrogen gas flow rate, and tungsten hexafluoride gas flow rate. Among these, the conditions for selective growth strongly depend on the flow rates of the two gases, hydrogen gas and tungsten hexafluoride gas, and selective growth occurs when the flow rates are within a certain range. In the case of a furnace with a diameter of 10crr1 and a length of 220mm (771) used in the experiment, the following are: Temperature: 450C1 Pressure (carrier gas is nitrogen)
At 0.1 Torr, when the flow rate of tungsten hexafluoride gas is 126 cm3/min, the hydrogen gas flow rate is 10 to 40 cm3/min.
Selective growth occurs in the crn3/min range. When the tungsten hexafluoride gas flow rate is reduced, the range of hydrogen gas flow rate becomes narrower.If the flow rate of tungsten hexafluoride is 3077713/min, the range of hydrogen gas is 10~13c! n3/min. Weak dependence on temperature. When the temperature is lowered, the range of selective growth moves to the side where the hydrogen gas flow rate is large, and the growth rate sharply decreases.

実施例2 実施例1に示した方法で、表面全タングステンで覆った
アルミニウム、及びアルミニウムー銅合金配線全作製し
た。この配線に高密度の電流全通じ断線までの時間(寿
命)を測定し、表面合金層のない配線と比較した。配線
の寸法は、幅2μm1厚さ0.6μm1長さ100μm
1また、通電条件は、温度250CX電流密度2.5 
X 10 ’ A/cm” であった。結果を第4図に
示す。アルミニウムの場合は合金層を設けることにより
30〜80倍に寿命が延びた。アルミニウム・銅合金の
場合でも15倍程度に寿命は延びている。
Example 2 By the method shown in Example 1, aluminum whose entire surface was covered with tungsten and aluminum-copper alloy wiring were entirely fabricated. The time (lifetime) for this wiring to run through high-density current until disconnection was measured and compared with wiring without a surface alloy layer. Wiring dimensions are width 2μm, thickness 0.6μm, length 100μm.
1 Also, the current conditions are: temperature 250C x current density 2.5
X 10'A/cm". The results are shown in Figure 4. In the case of aluminum, by providing an alloy layer, the lifespan was extended by 30 to 80 times. In the case of aluminum-copper alloy, the life was also extended by about 15 times. Life expectancy is increasing.

実施例3 実施例1に示した方法で作製した配線の耐蝕性と次のよ
うにして調べた。3X4rpmに切断したチップi、T
o−5ステムに銀ペースト付し、超音波ボンディング法
で結線した。このチップの配線にはノiツシベーション
は設けず、−1だステム上でチップはむき出しの状態で
ある。温度85C,85%の加湿条件で、バイデス電界
全印加し断線腐蝕までの時間(寿命)を測定した。表面
合金層を設けたアルミニウム配線の平均寿命は約900
時間でアシ、表面合金層のない配線における値、■70
時間の約5倍の寿命が得られた。
Example 3 The corrosion resistance of the wiring fabricated by the method shown in Example 1 was investigated in the following manner. Chips i, T cut to 3X4 rpm
Silver paste was applied to the o-5 stem, and wires were connected using an ultrasonic bonding method. No noise is provided in the wiring of this chip, and the chip is exposed on the -1 stem. Under conditions of a temperature of 85C and 85% humidity, a full Vides electric field was applied and the time (life) until disconnection corrosion was measured. The average lifespan of aluminum wiring with a surface alloy layer is approximately 900 years.
Value for wiring without surface alloy layer, ■70
A lifespan approximately 5 times longer was obtained.

〔発明の効果〕〔Effect of the invention〕

本発明にJ:れば、上記実施例でも示したように、長寿
命のAt又はAt合金配線Cl造体が得られ、その工業
的価値は極めて大きい。
According to the present invention, as shown in the above embodiments, a long-life At or At alloy wiring Cl structure can be obtained, and its industrial value is extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図、第3図は半導体素子断面図、第4図は
、配線の通電寿命を示す図である。 1・・・シリコン基板、2・・・シリコン酸化膜、3・
・・ア第  1  図 烹 Z  図 監 袢 窒 嘉 3  図 ■ 4  図 「 °1 寿命 Cす
FIGS. 1, 2, and 3 are cross-sectional views of a semiconductor element, and FIG. 4 is a diagram showing the energization life of wiring. 1... Silicon substrate, 2... Silicon oxide film, 3.
...A No. 1 Diagram Z Diagram 3 Diagram■ 4 Diagram

Claims (1)

【特許請求の範囲】[Claims] fソ面を異種金属、若しくはその金属とアルミニウムと
の全居間化合物で覆ったイt¥造のアルミニウム、若し
くはアルミニウム合金配線において、異種金属、特にア
ルミニウムとの間に金属間化合物全形成する金属を、選
択的化学気相堆積法によって形成すること(il−特徴
とする配線構造体の製造方法。
In manufactured aluminum or aluminum alloy wiring whose surface is covered with a dissimilar metal or a complete compound of that metal and aluminum, a dissimilar metal, especially a metal that forms an intermetallic compound between it and aluminum, is , forming by a selective chemical vapor deposition method (il- A method for manufacturing an interconnect structure characterized by:
JP18904582A 1982-10-29 1982-10-29 Manufacture of wiring structure Pending JPS5979550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18904582A JPS5979550A (en) 1982-10-29 1982-10-29 Manufacture of wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18904582A JPS5979550A (en) 1982-10-29 1982-10-29 Manufacture of wiring structure

Publications (1)

Publication Number Publication Date
JPS5979550A true JPS5979550A (en) 1984-05-08

Family

ID=16234363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18904582A Pending JPS5979550A (en) 1982-10-29 1982-10-29 Manufacture of wiring structure

Country Status (1)

Country Link
JP (1) JPS5979550A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043858A (en) * 1983-08-22 1985-03-08 Toshiba Corp Manufacture of semiconductor device
JPS6134957A (en) * 1984-07-26 1986-02-19 Fujitsu Ltd Manufacture of semiconductor device
JPH0247831A (en) * 1988-08-10 1990-02-16 Toshiba Corp Manufacture of semiconductor device
US4988423A (en) * 1987-06-19 1991-01-29 Matsushita Electric Industrial Co., Ltd. Method for fabricating interconnection structure
US5126283A (en) * 1990-05-21 1992-06-30 Motorola, Inc. Process for the selective encapsulation of an electrically conductive structure in a semiconductor device
US5223455A (en) * 1987-07-10 1993-06-29 Kabushiki Kaisha Toshiba Method of forming refractory metal film

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513194A (en) * 1974-06-24 1976-01-12 Fuji Electric Co Ltd HINANJUDOHOKOJIDOSETSUTEIHOHO

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513194A (en) * 1974-06-24 1976-01-12 Fuji Electric Co Ltd HINANJUDOHOKOJIDOSETSUTEIHOHO

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043858A (en) * 1983-08-22 1985-03-08 Toshiba Corp Manufacture of semiconductor device
JPS6134957A (en) * 1984-07-26 1986-02-19 Fujitsu Ltd Manufacture of semiconductor device
US4988423A (en) * 1987-06-19 1991-01-29 Matsushita Electric Industrial Co., Ltd. Method for fabricating interconnection structure
US5223455A (en) * 1987-07-10 1993-06-29 Kabushiki Kaisha Toshiba Method of forming refractory metal film
JPH0247831A (en) * 1988-08-10 1990-02-16 Toshiba Corp Manufacture of semiconductor device
US5126283A (en) * 1990-05-21 1992-06-30 Motorola, Inc. Process for the selective encapsulation of an electrically conductive structure in a semiconductor device

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