JPS6042785A - Address controller for rom for pattern generator - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to an address control device for a read-only memory (hereinafter referred to as ROM) for a pattern generator.

(Prior Art) In a ROM that stores character patterns, etc., the - character pattern is usually divided into multiple parts (turns) and each partial pattern is stored at one address position in the ROM. For example, In the case of a character with a 16 x 16 dot pattern, as shown in Fig. 1, one character is divided into 16 partial patterns ■~[phase] whose partial patterns are 16 horizontal dots, and these partial patterns ■~[phase] are written in 16 consecutive address locations of the ROM.In this way, a large number of character patterns 7 are stored in the RO.
When reading a desired one-character pattern in M, conventionally, the start address of the desired character pattern (the address of the first partial pattern ■) is specified, the first partial pattern ■ is read out, and then the next Specify the address of the partial pattern ■, read the partial pattern ■, and then
By repeating such readout operations, when the last partial pattern [phase] is read out, the readout of one character pattern is completed.

Specifically, for example, as shown in Figure 1, one character pattern is composed of 16 partial patterns, and each partial address is R.
When stored in each address position of OM, one character pattern is read from the lower 4 bits A. - Specify the start address of the desired character pattern with A3 set to 0 and upper bits A4 to Am set to desired values, read the first partial pattern, and specify the subsequent 15 partial patterns using the lower pins of the address)A . This was done by sequentially specifying -A3. In this way, in the conventional addressing method, 1
When reading a character pattern, it is necessary to reset the address as many times as there are partial patterns, which has the drawback of increasing processing time. After reading the pattern for one character, you still want to access another character pattern.
The lower 4 bits of the address had to be cleared again.

(Objective) It is an object of the present invention to solve the problems of the prior art and to provide a ROM address control device that allows easy address specification and short processing time.

The present invention provides a ring counter for specifying the lower bits of an address, and increments the ring counter by a read control pulse (read notrope signal) from a processing device that accesses the ROM. By sequentially generating addresses for partial patterns within one character, it is not necessary to set addresses from the processing device for each partial pattern.

(Example) Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 2 is a block diagram of a system including a ROM for a character generator and its address section according to an embodiment of the present invention, and FIG. M3 is a flowchart showing its operation. This system is 80M1, and an address latch register 2 that latches the upper bits A4 to An of the specified address.
, an address latch register 3 that latches the lower pin l-Ao-A3 of the specified address, and a ring counter 4.
It is composed of a data output M5 from the ROM 1, a data bus 6 of the /stem, and control lines. In this example, one character is a 16 x 16 dosoto pattern as shown in Figure 1, and a partial pattern consisting of 16 pintos.
It is divided into [phases], and each partial pattern is stored in a ROM.
1 at each consecutive address.

That is, a single character pattern is stored in ROM 1 at 16 consecutive address locations. Four bits are required to specify the relative address position within the storage area for one character including these 16 address positions, so the lower address latch register 3 and ring counter 4 are
Consists of focus.

When the processing unit (hereinafter referred to as CPU) accesses ROM 1, the start address of the character pattern to be read is stored in address latch registers 2 and 3 by the OUT command, which is the I10 command, from the CPU, and the control signal l0WR generated by the command is sent. It is latched at the right timing. The contents of the lower bit address launch register 3 are set as 7 in the ring counter 4. Next, in response to a read command (IN command) from the CPU, the first partial pattern of the specified character pattern is read out. This is done at the timing of the control signal 10RD generated by the IN command, and the count value of the ring counter 4 is incremented by one at the trailing edge of the control signal 10RD. Therefore, when the CPU finishes reading the first partial pattern with the IN command, the character generator ROM accessed has advanced by one position.

Therefore, you can use just the IN command without having to set the address again.
Can read pattern contents. This IN command is 16
By repeating this process several times, a pattern of one character of 16×16 dots can be read out.

In this embodiment, the ring counter has 4 bits as described above, so it returns to 0 after counting 16 times. Therefore, if you want to read the character pattern of another address continuously,
Lower bit A. - There is no need to launch the address again in the address launch register 3 of A3, and the upper bits A4~
It is only necessary to set the start address of the pattern in the address latch register 2 of An (see FIG. 3). In addition,
Each character pattern is stored in ROM1 as the lower bit A of its first address. If the address is stored such that -A3 becomes oooo, the address latch register 3 for the lower bits can be omitted.

According to this embodiment, the number of instructions on the software is reduced compared to the prior art, and the access speed to the ROM for the character generator is increased.

FIG. 4 shows another embodiment of the present invention, in which the pattern generator ROM is composed of a plurality of ROMs, and one pattern (one character pattern) is stored across the plurality of ROMs K. 1 is a diagram showing a schematic configuration of a type 16×16 bit pattern generator; FIG. R.O.
M10 is composed of two ROMs 11 and 12, and the 16×16 donot pattern is divided into a left half pattern 16 and a right half pattern 17, which are stored in the ROMs 11 and 12, respectively. There is. The configuration for addressing this ROM includes an address latch register 13, a 4-bit ring counter 14,
and ROM switching flip-flop (F, F,) 15
have. The address latch register 13 latches the upper pins A4 to An of the start address. Lower bit A of address. -A3 is generated by a 4-bit ring counter 14. This 4-bit ring counter 14 is first cleared, and a carry pulse (carry) is generated when the count completes one cycle. ROM switching flip-flop 15 is inverted by the above carry pulse and is connected to ROMs 11 and 12 so that its output selects ROM +1 or 12.

To explain the operation of this embodiment, first, the start address of a desired pattern is placed in the address latch register 13. Each pattern is the lower bit A of its starting address.

-A3 is addressed in the ROM to be oooo, so the lower bit Ao-A3 clears the 4-bit ring counter 14 to generate the lower bit of the starting address. Therefore, it is necessary to launch only the upper bits A4 to An into the address latch register 13. Since the 4-bit ring counter 14 has no carry, the ROM switching flip-flop 15 selects the ROM 11 on the left side. Next, I from the CPU
The read strobe pulse (IORD), which is a read control signal created by the N command, causes the left ROM to
11 (i.e. address latch register 13 and 4-bit ring counter 14)
The storage contents of the address specified by ) are read out. At the trailing edge of this read strobe pulse, the 4-bit ring counter 14 is counted up by one. Therefore, with the next read strobe pulse, the stored contents of the address next to the first address are automatically read out. In this way, the CPU issues the read strobe pulse 16 times, and thereby the left-hand character pattern consisting of 16 partial patterns is successively read out.

When these 16 readings are completed, a carry is set in the 4-bit ring counter 14, which inverts the output of the ROM switching flip-flop 15, and the right ROM
12 is selected.

At this time, the output of the 4-bit ring counter 14 returns to 0, and therefore the contents of the first address of the right pattern are read out by the read strobe pulse. Then, in the same way as when reading characters on the left side, the address is incremented by the count up of the 4-bit ring counter 14 due to the trailing edge of the read strobe pulse.
By issuing read commands 16 times in succession, the PU automatically reads out the right pattern.

In this way, once the CPU first specifies the start address of the pattern it wants to read, it can read the contents of one character of a certain pattern simply by repeating the read command 32 times.

According to this embodiment, by the combination of the ROM switching F'J knob flop and the ring counter, it is not necessary to set the pattern start address again when reading the right pattern after reading the left pattern.
This has the advantage that there is no need to switch the output section). Therefore, the number of instructions on the software is reduced and the processing speed is increased.

In addition, in the above embodiment, the size of the pattern is 1
I will explain an example of a 6 x 16 dot pattern.
This can be of any size, and the number of ring counter pits, the number of ROM switching flip-flops, the number of ROMs, etc. can be appropriately selected accordingly.

(Effects) As described in the description of the embodiments, according to the present invention,
Since a ring counter is used so that the address is automatically increased by a pattern read command from the CPU, the number of commands on the software is reduced and the processing speed is increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the structure of a character pattern in a ROM, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a flowchart showing the operation of the embodiment of FIG. 2, and FIG. FIG. 5, a block diagram of another embodiment of the present invention, is a diagram showing an example of the structure of character patterns in R and OM in the embodiment of FIG. 4. ], 11.1.2...ROM, 2.
3.13 Address latch register,
4.14 ...... Ring counter, 15...
・・・・・・ROM switching flip-flop. Patent applicant Rico Co., Ltd. −

Claims (2)

[Claims] (1) An address launch that receives and stores address data of a pattern to be accessed stored in the pattern generator ROM from the processing device, and a 1. An address control device for a ROM for a pattern generator, comprising a ring counter that increments at the trailing edge of a pulse. (2) The pattern generator ROM includes a plurality of ROMs and an R for selecting the plurality of ROMs.
4. The ROM address control device for a pattern generator according to claim 1, further comprising: OM switching means, wherein said ROM switching means is controlled by a carry of said ring counter.