JPS6038796A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make write easy to make high integration, operations with a low voltage, and high-speed write possible by providing a power switch MOSFET for a CMOS flip flop of a memory cell and turning off the power switch at a write time. CONSTITUTION:The memory cell consists of a CMOSFF where inputs and outputs of CMOS inverters consisting of n type MOSFETs and p type MOSFETs Q1, Q2, Q3, and Q4 are cross-connected. The power switch consisting of p type MOSFETs Q7 and Q8 is provided between FETs Q2 and Q4 and a power source voltage VDD, and FETs Q7 and Q8 are turned off by a write control signal we which is set to the high level at a write time. Thus, the input impedance of the memory cell is high, and inverting write is performed easily and surely with a low voltage through transmitting gate MOSFETs Q5 and Q6 having low conductance characteristics and a column switch MOSFET, etc. As the result, high integration, operations with a low voltage, and high-speed write are possible in this semiconductor integrated circuit device.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and for example, a RAM configured with an 0MO3 (complementary MO3) circuit.
The present invention relates to a technology effective for semiconductor integrated circuit devices including random access memory (random access memory) and operating with a battery voltage of 1.5 volts.

[Background technology]

A pair of CMOS devices consisting of a p-channel MO3FET (insulated gate field effect transistor) and an n-channel MO3FET, whose inputs and outputs are cross-wired to each other.
A transmission gate MO3FE is provided between the inverter, its pair of input/output terminals, and its pair of complementary data lines.
A CMOS static type RAM using a memory cell consisting of T is well known (see May 2, 1977 issue of Nikkei Electronics magazine, pages 48 to 64 ff1).

When operating a semiconductor integrated circuit device including this CMOS static type RAM with a battery voltage of 1.5 volts,
The inventor of the present application has revealed that the following problem occurs. That is, under such a low voltage as described above, inversion writing of the CMOS flip-flop constituting the memory cell may become impossible. This is because, in order to invert the above-mentioned flip-flop, the series conductance characteristic of the transmission gate MOS FET and the drive MO3FE'r that forms the inverted write signal must be changed compared to the conductance characteristic of the MOSFET of the flip-flop circuit that is in the on state. It needs to be bigger. However, the source side of the transmission game) MOSFET is the drive MO3FET mentioned above.
The on-resistance causes the substrate effect to increase the actual threshold voltage. Therefore, in order to increase the conductance characteristics of a transmission MOSFET, the cell size must be increased.
This is because the size of the memory cell becomes large and the degree of integration is extremely reduced, making it impossible to put it to practical use.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a CMOS static RAM that achieves high integration and low voltage operation.

Another object of the invention is to provide a CMOS that realizes high-speed writing.
An object of the present invention is to provide a semiconductor integrated circuit device including a static type RAM.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a power switch MOS that selectively supplies voltage to a CMOS flip-flop that constitutes a memory cell.
FET is provided, and this power switch MOS FET
By turning T off during a write operation,
This facilitates writing into memory cells.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment in which the present invention is incorporated in an information processing device such as a one-chip microcomputer, although the present invention is not particularly limited thereto. Although not particularly limited, the RAM in the figure may be a known CMOS (complementary MO3) integrated circuit (
It is formed along with other circuits constituting a microcomputer or the like on a single semiconductor substrate such as a silicon single crystal using the manufacturing technology of IC.

The memory cell MC is an n-channel M as shown in FIG.
O3FETQI (Q3) and p-channel MO3FET
Q2 (Q4) is provided between a flip-flop circuit in which the input and output of a CMOS inverter are cross-wired to each other, and its pair of input/output terminals and data lines (or digit lines) D and D. between channels
Transmission gate MO3FETQ5 composed of 8FETs. Q
It consists of 6. Further, in this embodiment, in order to easily perform writing even at a low voltage, the p-channel MO3FETQ, 2. A p-channel MO3FET Q7.Q4 is connected between Q4 and the power supply voltage VDD. A power switch consisting of Q8 is provided. Although not particularly limited,
For the gates of these (7) MO3FETs Q7°Q8, a polysilicon layer integrally formed between memory cells MC arranged in the same row, which will be described later, is used.

As shown in FIG. 1, a plurality of memory cells MC with the above configuration
are arranged in a matrix. In other words, the transmission gate type MO3FETQ5 of the memory cells arranged in the same row
．． Gates such as Q6 are commonly connected to corresponding word lines wl and w2, and input/output terminals of memory cells arranged in the same column are connected to a pair of corresponding complementary data lines (or bit lines) DO, DO, respectively. and DI, connected to DI.

In FIG. 1, word line w1 is selected by an inverter DV serving as a drive circuit that receives a selection signal generated by an X address decoder X-DCR. The same applies to the other word line w2.

The X-address decoder X-DCR is configured by a vertical ROM (read-only memory), although it is not particularly limited. That is, an enhancement type MO3FET as a memory cell is formed at the intersection of an input line running in the vertical direction and an output line running in the horizontal direction as a memory cell, and a depletion type MO3FET is formed at a place without an O mark.
A FET is formed. M that constitutes these memory cells
O3FET is constituted by an n-channel MO3FET. Such MOS FETs are connected in series in the horizontal direction, and a p-channel inter-channel O5FET as a precharging means is connected between one end of the MOS FET and the power supply voltage VDD, and the other end of the series structure is connected to the ground potential of the circuit. n-channel MO3FE as a discharge means between
T is connected.

Then, an output signal (word line selection signal) is sent out from the connection end with the precharge MO3FET.

This X address decoder ;A complementary address signal with t is supplied.

A pair of data lines DO in the memory array.

DO, Dl, and Di are transmission gates MO3FETQ9. for data line selection, respectively. QIO and Qll, Q1
It is connected to the common data lines CD, CD through a column switch circuit composed of two. This common data line C
The input terminal of the read circuit RA and the output terminal of the write circuit WA are connected to D and CD. The write circuit WA is
Although not particularly limited, p-channel MO3FETQ17 and n-channel MO5FETQ1 are controlled by a combinational logic circuit LOG that receives write data and control signal i.
A three-state output MO3FET configured with 8 is utilized. That is, the combinational logic circuit LOG causes the control signal 1 to be at a high level when the write operation is not performed, so that the MOS FETQ17. Both QIBs are turned off. Then, during a write operation, the control signal stone becomes low level, so that the MO is activated according to the write data.
3FET Q17 or QlB is turned on and the common data line CD is set to high level or low level. For other common data lines 5, the same 3-state output M
An O5FET is provided and outputs a write signal having a phase opposite to that of the common data line CD during a write operation.

MO3FETQ9 that constitutes the above column switch circuit.
A selection signal is supplied to the gates of QIO, Qll, and Q12 from a Y address decoder Y-DCR, respectively.

This Y address decoder Y-DCR is constituted by a vertical ROM similar to that described above, and is supplied with complementary address signals VO+if and 3'01y1 as described above.

In addition, each data line is provided with a precharge MO3FE configured with a p-channel MO3FET, although this is not particularly limited.
TQ! 3 to Q16 are provided.

In the memory array having the above configuration, the write control signal W! is not particularly limited to the gate of the power switch MOS FET provided in the memory cell MC. is commonly supplied. That is, the power switch MO3FET configured with the above-mentioned p-channel MO3FET is
Q? , Q8, etc. are all turned off.

The write operation of this embodiment will be explained next.

During a write operation, one memory cell MC is brought into a selected state by the X and Y address decoders X and Y-DCH. Further, the common data lines CD and CD are set to high level and low level according to the write data. At this time, since the write control signal w6 is set to high level, the power switch MO3FET of the memory cell MC is turned off. Therefore, all memory cells MC hold stored information in their gate capacitances. In other words, the input impedance of all memory cells MC is brought into a high impedance state. In this state, the high level and low level of the common data 1lcD and cD are written into the selected memory cell. Therefore, write drive MO3FET with relatively small conductance characteristics
Even by using a transmission gate MO3FET and a transmission gate MO3FET, inversion writing of stored information can be easily performed.

Note that since the time required for the above writing, in other words, the time during which the power switch MO3FET is turned off, is extremely short, the information stored in the unselected memory cell MC may be lost due to the temporary off state of the power switch MO3FET. You won't get lost.

〔effect〕

(1) In addition to providing a power switch MO3FET in the old path of the CMOS flip-flop that constitutes the memory cell,
By turning it off during writing, the input impedance can be increased, so transmission gate MO3FET and column switch M with small conductance characteristics are used.
The effect that inversion writing can be easily performed even through OS FET or the like can be obtained.

(2) According to the above (1), the static RAM according to the present invention can be built into a semiconductor integrated circuit device that operates on a 1.5 volt battery (including photovoltaic) voltage. In other words, the CMOS gate circuit can operate satisfactorily even at a low voltage of about 1 volt, and the static RAM according to the present invention can perform inversion writing to the static RAM without depending on the ratio of the conductance characteristics, so the battery life can be reduced. Alternatively, even if the voltage becomes low as described above due to a decrease in the amount of received light, the information processing operation can be performed.

This allows static type RA with large power margin.
The effect is that a semiconductor integrated circuit device containing M can be obtained.

(3) Since writing to the memory cell can be performed by charging/discharging the input capacitance of the flip-flop circuit without depending on the ratio of conductance characteristics, the writing speed can be increased.

(4) Since the power switch MO3FET is in the off state, no current is generated in the CMOS inverter even if the input level of the flip-flop circuit becomes an intermediate level during inversion writing, thereby reducing power consumption. You can get the 'JJ result of being able to do it.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, one power switch MO3FET may be provided for each memory cell. That is, in the fJS2 diagram, the p-channel MO3F constituting the flip-flop circuit
ETQ2. Q4 or n-channel MO3FETQI.

A power switch including one p-channel MO3FET or n-channel MO3FET may be provided between the commonly connected source power supply voltage vDD of Q3 or the ground potential point of the circuit.

Further, the power switch MOS FET may be shared in the column direction. Then, only the power switch MOS FET of the memory cell in the row or column selected in the write operation may be turned off.

In addition, the transmission gate MO3FE'l that constitutes the memory cell
” is a p-channel MO3FET and n
By configuring it with a channel MO3FET, inversion writing may be performed even at a lower voltage. This is because when the CMOS transmission gate circuit described above is used, the write level can be transmitted without level loss due to threshold voltage.

Furthermore, address decoder, write c'j/'iui;
J out.

The specific configuration of peripheral circuits such as circuits can be of various types.

[Application field]

In the above description, the present invention will mainly be based on the invention developed by H., which is based on the static type integrated circuit built into a semiconductor integrated circuit device such as a microcomputer. Although we have explained the case where it is applicable to AM, there is no limitation thereto.For example, the static type I and ΔM of the above embodiment can be similarly applied to semiconductor memory devices. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a circuit E1 showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of a memory cell MC thereof, without showing the embodiment. X-ADB...X address buffer, Y-ADB...Y
Address buffer, X-DCR...X address decoder, Y-DCR...Y address decoder, MC...memory cell, RA...read circuit, WA...write circuit

Claims (1)

[Claims] 1. P-channel MO3FET and n-channel Mo5r
ET, and a flip-flop circuit composed of two inverters whose inputs and outputs are cross-wired to each other, and a transmission circuit provided between a pair of input/output terminals and a pair of complementary data lines. Game) MOSFET
and p-channel MO3FET or n-channel MO3
1. A semiconductor integrated circuit device comprising a memory array including a memory cell including a power switch MO5FET provided between one of the FETs and a voltage terminal and turned off during writing. 2. The semiconductor according to claim 1, wherein the memory array constitutes a RAM and is used as a data storage means for information processing according to a program written in a ROM. Integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device operates using a battery voltage of 1.5 volts as a power supply voltage.