JPS58179993A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the load capacity of a decoder to drive the word line at a high speed and then to select a memory element at a high speed, by activating only the memory element selection line that corresponds to a selected decoder via a transmitting switching element. CONSTITUTION:A column selecting address signal is set at a high level, and the signals supplied to memory elements 1 and 2 are set at a prescribed level respectively. The output of a row decoder XD is high, and the outputs of other row decoders XD are low. In such a case, a transmitting MISFET-Ti for the group 2 and a discharging MISFET-Qi for the group 1 are turned on. While a transmitting MISFET-Ti for the group 1 and a discharging MISFET-Qi for the group 2 are turned off. As a result, a row decoder drives only the word line of the selected row of the selected element group 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention mainly relates to a word line driving method for a memory device (hereinafter referred to as memory) using a metal-insulating film-semiconductor (hereinafter referred to as MIS) transistor.

FIG. 1 is a plan view of the main circuit blocks of a memory chip, in which memory cell blocks (1) and (2) forming two memory element groups are arranged corresponding to the rows between them. a row decoder (3) and a column decoder (4) arranged corresponding to the column of each memory cell block.
, (5).

FIG. 2 shows a row decoder (XDo NXD(n-1)) and a word line (WoNW(n-1)) of the memory chip shown in FIG.
-1))) and memory elements, as described above, the memory element groups (1), (2)
A total of n row decoders from 0 to (n-1) (X DoNX D (n-1)) placed between and operates to set the voltage level of all other remaining word lines to "Low".For example, when the 0th row is selected, only the output level of the row decoder (XDO) is set to "HIgh".
”, the output voltage level of (X I)+NX D (n-1) becomes “Low”.

Therefore, only the word line (Wo) is "High", and all other word lines (Wl"W (n-1)) are all "High".
All memory elements in the θ-th row in memory element groups (1) and (2) are selected. All that is left to do is to select one necessary column using the column decoder, and the intersection point is selected. Only one element will be selected.

However, such conventional memory devices are limited to word lines (W
oNW(n-1)) consists of two memory element groups (1) and (2
), it has a large stray capacitance, and the row decoder placed in the center has to drive this large stray capacitance, which has the disadvantage of increasing the time it takes to select a memory element.

The present invention has been made in order to eliminate the above-mentioned drawbacks of conventional memories, and includes providing a transmission switching element in each element selection line of a memory pin group shared on both sides of a decoder. When one of the decoders and one of the memory element groups is selected, only the element selection line corresponding to the selected decoder of the selected memory element group is activated via the transmission switching element. By doing so, the load capacitance of the decoder can be reduced and word lines can be driven at high speed, thereby speeding up the selection of memory elements.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 8, (To tNT(n −1) L:l
ll and (ToRNT(n-1)R) are transmission switching elements consisting of Mis) transistors, and (Qo
t"Q (n-t) and (Q OR-Q (n-1
)R) is when the word line which is the element selection line is in a floating state,
This is a discharge MIS transistor for driving the word line to a predetermined potential point such as a ground potential point or a fixed potential in the vicinity thereof.

(Agl), (AC3), (A&1), and (Ai) are used to invert the column selection address signal (Aα) using an inverter, etc., or perform desired processing such as amplification. This is the signal obtained by As shown in the figure,
The signal (Ωl) input to the gate of the transmission MIs transistor (ToL"T(nt)t,) for the memory element group (1) and the transmission M■S transistor (ToRNT) for the memory element group (2) The signals (Agl) input to the gates of (n-s)R) are inverted to each other, and are input to the gates of the discharge MIs transistors (QotNQ(nt)t) for the memory element group (1). signal (-2) and discharge M for memory element group (2).
The signal (-) input to the gate of the IS transistor (Qo*"Q(nt)R) is also in an inverted relationship. Moreover, the address signal (Agl) and (Ja) are also in an inverted relationship with each other, and (Agl) ) and (AC3) are also mutually inverted. Therefore, (Agl) and (AC3) may be the same signal, and ('; □l) and (n may also be the same signal.

The operation in this embodiment will be explained below.

Now, the column selection address signal (Aα) is “High”, the above signal (Agl) (AC3) is “High”,
(凋1), (Agl) are “Low” and the 0th
A row is selected and the output of the row decoder (XDo) is “H”.
other row decoders (XD+NXD (n
Consider the case where the output of -1)) is "Low". At this time MIS) transistor (Tor”T(n-1)it)
and (:QotNQ(nt)t) are in the on state,
It becomes low impedance and also MIS) transistor (T
otNT(nt)t) and [QoRNQ(n-1)l]
becomes a cutoff state and becomes high impedance. As a result, the row decoder signal is not transmitted to the memory element l\(1), and the MIs transistor (TotNT(nt)
t) makes it unselected.

On the other hand, for memory element l\(2), all row decoder signals are transmitted, but "High" is (X D
o), so in the end only the word line (Wow) is “H”.
and all other word lines (W
IR~W(n-1)i), (Wot, NW(n-t)
t,) becomes “Low”.

Therefore, the row decoder (XDO) decodes the word line (WO
The word line (WOL) of the unselected memory element l\(1) in the same row is not driven.

In other words, the load capacitance driven by the row decoder is only the stray capacitance of the memory element group on one side, and compared to the conventional circuit system, the load capacitance is reduced by half. Therefore, MIS transistor (T
otNT(n-1)t), (Tom~1'(n-1)
The on-resistance of the row decoder (XDoNXD(n-1
)) If you make it sufficiently smaller than the output impedance of
It is possible to drive word lines approximately twice as fast as conventional circuits.

Although the present invention has been described above in the case of an N-channel MIS, it can also be applied to a MIS memory using a P-channel MIS, and further to a memory using a bipolar transistor.

As described above, according to the present invention, since the word lines of unselected memory element groups are not activated, a high-speed semiconductor memory can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the main circuit blocks of a memory chip, FIG. 2 is a circuit diagram of the main part of a conventional memory, and FIG. 8 is a circuit diagram of the main part showing an embodiment of the memory of the present invention. (1)...Memory element group, (2)...Memory element group, xD0 to XD(n-1)...Decoder, WOR/VW(n-1)R and WOLA7W(n-1
)L - element selection line, ToiNT(n-1)i and T
otA7T(n-1)L ・"Transmission switching element. Agent Shin Kuzuno - (1 other person)

Claims (1)

[Claims] a first memory element group having n rows of element selection lines to which a plurality of memory elements are commonly connected; a second memory element group having n rows of element selection lines to which a plurality of memory elements are commonly connected; n decoders disposed between the first and second memory element groups and provided in common to element selection lines in the same row of the first and second memory element groups; A transmission switching element is provided on each element selection line of the first and second memory element groups, and one of the decoders is selected, and one of the first and second memory element groups is selected. is selected, only the element selection line in the row corresponding to the selected decoder of the selected memory element group is activated via the transmission switching element.