JPS6037813A - Timing signal extracting circuit - Google Patents

Timing signal extracting circuit

Info

Publication number
JPS6037813A
JPS6037813A JP14531283A JP14531283A JPS6037813A JP S6037813 A JPS6037813 A JP S6037813A JP 14531283 A JP14531283 A JP 14531283A JP 14531283 A JP14531283 A JP 14531283A JP S6037813 A JPS6037813 A JP S6037813A
Authority
JP
Japan
Prior art keywords
timing signal
circuit
signal
frequency
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14531283A
Other languages
Japanese (ja)
Inventor
Hiroaki Ikejiri
池尻 博明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP14531283A priority Critical patent/JPS6037813A/en
Publication of JPS6037813A publication Critical patent/JPS6037813A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

Abstract

PURPOSE:To restore a complete timing signal from a missing input timing signal by providing a frequency divider outputting a signal having the same frequency as that of the input timing signal and synchronizing the frequency-divider with the input timing signal. CONSTITUTION:An output of a fixed oscillator 17 oscillated in a frequency being an integral number of multiple of the frequency of the timing signal is frequency-divided by a frequency divider 18. The frequency divider 18 is a frequency divider being resettable and outputting a signal having a frequency the same as the frequency of the timing signal and is reset by the timing signal D inputted from an input terminal 1. Then a noise eliminating circuit 14 eliminates a noise component 9 included in the input timing signal C. Thus, even if the input timing signal C has a missing 10, the complete timing signal E is obtained from an output terminal 19.

Description

【発明の詳細な説明】 本発明は、雑音を含み、劣化しやすい入力タイミング信
号から、タイミング信号のみを抽出する回路において、
雑音を除失し、更にタイミング信号の脱落を補正し、タ
イミング信号脱落時にも内部タイミング信号を発生する
ことのできるタイミング信号抽出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a circuit for extracting only a timing signal from an input timing signal that includes noise and is susceptible to deterioration.
The present invention relates to a timing signal extraction circuit that can eliminate noise, correct timing signal dropout, and generate an internal timing signal even when the timing signal is dropped.

従来、雑音を含み、劣化しやすいタイミング信号から、
タイミング信号のみを抽出する回路としては、帯域フィ
ルタ、あるいは低域フィルタ、フンパレータ、波形成形
回路等から構成された雑音除去回路が使用されていた。
Conventionally, from timing signals that contain noise and are prone to deterioration,
As a circuit for extracting only the timing signal, a noise removal circuit composed of a bandpass filter, a low-pass filter, a humpator, a waveform shaping circuit, etc. has been used.

第1図に雑音除去回路の一例を示す01はタイミング信
号入力端子、2は抵抗3、コンデンサ4で構成した低域
フィルタ、5は低域フィルタ2の出力信号があらかじめ
設定した振幅値よりも大きいか小さいかによってその出
力を正負反転させるコンパレータ、6はコンパレータ5
の出力(Ft 号ヲ波形成形し、矩形波を発生する波形
成形回路、7は雑音を除去したタイミング信号出力端子
である。
Figure 1 shows an example of a noise removal circuit. 01 is a timing signal input terminal, 2 is a low-pass filter composed of a resistor 3 and a capacitor 4, and 5 is a low-pass filter whose output signal is larger than a preset amplitude value. A comparator that inverts the output depending on whether the output is positive or negative, 6 is a comparator 5
The output (Ft) is a waveform shaping circuit that shapes the waveform and generates a rectangular wave, and 7 is a timing signal output terminal from which noise has been removed.

尚、コンパレータは差動増幅器、あるいはO−MOSの
インバータスレショールドレベル等を利用した公知の回
路を全て適用することができる。
Note that any known circuit using a differential amplifier or an O-MOS inverter threshold level can be used as the comparator.

タイミング信号入力端子1がら入力したタイミング信号
を低域フィルタ2に入力すると、タイミング信号に含ま
れた雑音はその振幅が減衰し、次段のコンパレータ5の
スレショールドレベル、即ちあらかじめ設定した振幅値
を越えることができないため、タイミング信号出力端子
7からは、雑音を除去したタイミング信号が取り出せる
のである。
When the timing signal input from the timing signal input terminal 1 is input to the low-pass filter 2, the amplitude of the noise included in the timing signal is attenuated, and the amplitude is reduced to the threshold level of the next stage comparator 5, that is, the preset amplitude value. Therefore, a timing signal with noise removed can be taken out from the timing signal output terminal 7.

この様子を第2図に示す。This situation is shown in FIG.

第2図−人は、タイミング信号入力端子1より入力した
タイミング信号で、8は真のタイミング信号、9は混入
した雑音、10はタイミング信号の脱落を表わしており
、第2図−Bはタイミング信号出力端子7から出力され
るタイミング信号である。以上の如く、従来の雑音除去
回路を使用すれば、タイミング信号に含まれる雑音を除
去することは可能である。ところが、第2図に示すよう
に、タイミング信号脱落については何も補償するもので
はない。第2図−人のタイミング信号脱落10は、第2
図−Bの出力信号にも脱落として現われている。本来、
タイミング信号脱落とは、タイミング信号に逆極性の雑
音が重畳したものと見なすことができ、雑音の混入が生
ずる条件下では必ずと言ってよいほどタイミング信号脱
落という現象も生じている。しかしながら、従来はこの
ように・雑音の混入のみについ゛C様々な雑音除去回路
により補償していた一方、タイミング信号の脱落につい
ては、何の補償も行なっていなかった。
Figure 2-B is the timing signal input from the timing signal input terminal 1, 8 is the true timing signal, 9 is the mixed noise, 10 is the omission of the timing signal, and Figure 2-B is the timing signal. This is a timing signal output from the signal output terminal 7. As described above, it is possible to remove the noise contained in the timing signal by using the conventional noise removal circuit. However, as shown in FIG. 2, there is no compensation for timing signal dropout. FIG. 2 - Human timing signal dropout 10
It also appears as a dropout in the output signal in Figure B. Originally,
Timing signal dropout can be regarded as the superimposition of noise of opposite polarity on the timing signal, and under conditions where noise mixing occurs, the phenomenon of timing signal dropout almost always occurs. However, while in the past, only the incorporation of noise has been compensated for using various noise removal circuits, no compensation has been made for the dropout of the timing signal.

具体例として、従来の携帯用テレビジョン受像機の水平
同期回路例を第6図に示す。11は複合映像信号入力端
子、12は複合映像信号から複合同期信号を分離する同
期分離回路、16は複合同期信号から水平同期信号を分
離する水平同期信号分離回路、14は水平同期信号分離
回路出力に含まれる雑音を除去する雑音除去回路、15
は水平AFO回路、16は水平AFO回路出力端子であ
る。
As a specific example, an example of a horizontal synchronization circuit of a conventional portable television receiver is shown in FIG. 11 is a composite video signal input terminal, 12 is a synchronization separation circuit that separates the composite synchronization signal from the composite video signal, 16 is a horizontal synchronization signal separation circuit that separates the horizontal synchronization signal from the composite synchronization signal, and 14 is the output of the horizontal synchronization signal separation circuit. Noise removal circuit for removing noise included in 15
1 is a horizontal AFO circuit, and 16 is a horizontal AFO circuit output terminal.

携帯用テレビジョン受像機は、静止した状態で使用する
場合よりも、むしろ電車、車等の移動体内で使用する場
合が多く、設置型のテレビジョン受像機に比べると、電
界強度急変、?T75波11波音1f音が頻繁に起こっ
ている。そのため携帯用テレビジョン受像機の水平同期
信号分離回路で得られた水平同期信号は、設置型のテレ
ビジョン受像機に比べ雑音を含んでいたり、あるいは脱
落することが非常に生じやすくなっている。しかも、雑
音の混入する期間、水平同期信号の脱落する期間も携;
j″”t′I用テレビジョン受像機では短期間の場合か
ら長期間の場合まで、広範囲に及んでいる。
Portable television receivers are often used in moving bodies such as trains and cars rather than in a stationary state, and compared to stationary television receivers, they are more susceptible to sudden changes in electric field strength. T75 wave 11 wave sound 1f sound is occurring frequently. Therefore, the horizontal synchronizing signal obtained by the horizontal synchronizing signal separation circuit of a portable television receiver contains noise or is much more likely to drop out than that of a stationary television receiver. Moreover, there are also periods when noise is mixed in and periods when the horizontal synchronization signal is dropped;
Television receivers for j''''t'I have a wide range of uses, from short-term to long-term use.

第6図に示す水平同期回路では、水平同期信号に混入し
た雑音は、雑音除去回路14によって除去することは可
能であり、この雑音の混入に対しては、水平AFO回路
15は安定に動作するこ七が予想される・しかしながら
・雑音の混入と同様に頻繁に生ずる水平同期信号の脱落
に対しては・何も補償していないため、水平AFO回路
15には何も入力されず、従って水平AFO回路15内
に惜成されている内部発振器は、水平同期信号の周波数
よりも低い周波数で発振し、頻繁に画像が乱れてしまう
という欠点をもっていたQ+7λl+111+渚\、/
1\ス/lp占かにホ1かとので一斗の口約は、タイミ
ング信号が脱落しても、タイミング信号脱落前の状態を
維持した内部タイミング信号を発生させる回路を提供す
るものである〇以下実施例に基づいて本発明の詳細な説
明する。
In the horizontal synchronization circuit shown in FIG. 6, the noise mixed into the horizontal synchronization signal can be removed by the noise removal circuit 14, and the horizontal AFO circuit 15 operates stably against this noise. However, since there is no compensation for horizontal synchronization signal dropout, which occurs frequently as well as noise incorporation, nothing is input to the horizontal AFO circuit 15, and therefore the horizontal synchronization signal is The internal oscillator that is left in the AFO circuit 15 has the drawback that it oscillates at a frequency lower than the frequency of the horizontal synchronizing signal, and the image is frequently distorted.
1\S/lp The promise of Kazuto is to provide a circuit that generates an internal timing signal that maintains the state before the timing signal was dropped even if the timing signal was dropped. The present invention will be described in detail below based on Examples.

第4図は本発明のタイミング信号抽出回路のブロック図
であり、1はタイミング信号入力端子、14はタイミン
グ信号に混入した雑音を除去する雑音除去回路、17は
水晶振動子等で栂成され、タイミング信号の周波数の整
数倍の周波数で発振する固定発振器・18は固定発振器
17の出力信号を分周し、タイミング信号と同じ周波数
の信号を出力するリセット可能な分周回路、19は分周
回路18の信号出力端子である。また、第5図は第4図
に示すブロック図の各部の波形図である・第5図−Cは
、タイミング信号出力端子1より入力したタイミング信
号であり、8は真のタイミング信号、9は混入した雑音
、10はタイミング信号の脱落を表わしており、この信
号を雑音除去回路14に入力すると、既に述べたように
、屑1音9が除去され、タイミング信号脱落10は何も
補償されない第5jJ−Dの信号が得られる。一方、分
周回路1Bは、固定発振器17の出力信号を分周し、タ
イミング信号と同じ周波数の信号を出力するため・雑音
除去回路14からのりセント信号を入力しなくても、タ
イミング信号と同じ周波数の信号を出力するものである
。従って、第5図−りの雑音除去後のタイミング信号で
分周回路18をリセットし、タイミング信号と分周回路
18の出力信号との同期をとると、雑音による分周回路
18のリセット誤動作が防止できるだけでなく、タイミ
ング信号が脱落しても分周回路18はタイミング信号と
同じ周波数の信号を出力するため、タイミング信号脱落
前の状態を維持した、第5図−Eに示す内部タイミング
信号20を出力することができるのである。
FIG. 4 is a block diagram of the timing signal extraction circuit of the present invention, in which 1 is a timing signal input terminal, 14 is a noise removal circuit for removing noise mixed in the timing signal, 17 is composed of a crystal oscillator, etc. A fixed oscillator that oscillates at a frequency that is an integral multiple of the frequency of the timing signal. 18 is a resettable frequency divider circuit that divides the output signal of the fixed oscillator 17 and outputs a signal with the same frequency as the timing signal. 19 is a frequency divider circuit. 18 signal output terminals. Also, FIG. 5 is a waveform diagram of each part of the block diagram shown in FIG. 4. FIG. 5-C is a timing signal input from the timing signal output terminal 1, 8 is a true timing signal, and 9 is The mixed noise 10 represents a dropout of the timing signal, and when this signal is input to the noise removal circuit 14, as already mentioned, the noise 19 is removed, and the dropout 10 of the timing signal is the 1st noise that is not compensated for at all. A signal of 5jJ-D is obtained. On the other hand, the frequency dividing circuit 1B frequency-divides the output signal of the fixed oscillator 17 and outputs a signal with the same frequency as the timing signal. It outputs a frequency signal. Therefore, by resetting the frequency dividing circuit 18 with the timing signal after noise removal as shown in FIG. Not only can this be prevented, but even if the timing signal is dropped, the frequency divider circuit 18 outputs a signal with the same frequency as the timing signal, so the internal timing signal 20 shown in FIG. can be output.

次に、本回路の具体的な実施例として、携帯用テレビジ
ョン受像機の水平同期回路を第6図に示す。11は複合
映像信号入力端子、12は複合映像信号から複合同期信
号を分離する同期分離回路、13は複合同期信号から水
平同期信号を分離する水平同期信号分離回路、14は水
平同期信号脱落1を回路出力に含まれている雑音を除去
する雑音除去回路、17は水晶振動子等で構成され水平
同期信号の周波数の整数倍の周波数で発振する固定発l
I硬器、18は固定発振器17の出力信号を分周し、水
平同期信号と同じ周波数の信号を出力するりセント可能
な分周回路、15は水平AFO回路、16は水平AFO
回路出力端子である・第6図に示す水平同期回路では、
水平同期信号に混入した雑音は、第6図の水平同期回路
と同様に、雑音除去回路14によって除去することが可
能であり、この雑音除去後の水平同期信号で分周回路1
8をリセットすることにより、雑音によるリセット誤動
作がなく、また水平同期信号と分周回路18の出力信号
との同期をとることができる。
Next, as a specific example of this circuit, a horizontal synchronization circuit for a portable television receiver is shown in FIG. 11 is a composite video signal input terminal, 12 is a synchronization separation circuit that separates the composite synchronization signal from the composite video signal, 13 is a horizontal synchronization signal separation circuit that separates the horizontal synchronization signal from the composite synchronization signal, and 14 is a horizontal synchronization signal dropout 1. A noise removal circuit 17 removes noise contained in the circuit output, and 17 is a fixed oscillation circuit composed of a crystal oscillator, etc., which oscillates at a frequency that is an integral multiple of the frequency of the horizontal synchronization signal.
18 is a frequency dividing circuit that can divide the output signal of the fixed oscillator 17 and output a signal of the same frequency as the horizontal synchronization signal, 15 is a horizontal AFO circuit, and 16 is a horizontal AFO circuit.
In the horizontal synchronous circuit shown in Figure 6, which is the circuit output terminal,
The noise mixed in the horizontal synchronization signal can be removed by the noise removal circuit 14, similar to the horizontal synchronization circuit shown in FIG.
By resetting 8, there will be no reset malfunction due to noise, and the horizontal synchronizing signal and the output signal of the frequency dividing circuit 18 can be synchronized.

従って、第3図の水平向M回路と同様に、雑音の混入に
対しては水平AFO回路15は安定に動作し、画面は安
定することが予想される。更に、分周回路18は固定発
振器17の出力信号を分周し、水平同期信号と同じ周波
数の信号を出力するものであるから、水平同期信号脱落
時には、脱落前の状態を維持して内部水平同期信号を出
力することができ、従って、水平同期信号脱落時におい
ても、常に水平A1!′C回路15には水平同期信号と
同期した分周回路18の出力信号が入力されることとな
り、水平同期信号脱落についても水平AFO回路15は
安定に動作し・画面は安定である。以上の如く、本発明
の回路を携帯用テレビジョン受像機の水平同期回路に実
施すると、従来の携帯用テレビジョン受像機に比べ・よ
り安定な画面を得ることができる。
Therefore, similar to the horizontal M circuit shown in FIG. 3, it is expected that the horizontal AFO circuit 15 will operate stably against the introduction of noise, and the screen will be stable. Furthermore, since the frequency divider circuit 18 divides the output signal of the fixed oscillator 17 and outputs a signal with the same frequency as the horizontal synchronization signal, when the horizontal synchronization signal is dropped, the state before the drop is maintained and the internal horizontal A synchronization signal can be output, so even when the horizontal synchronization signal is dropped, the horizontal A1! The output signal of the frequency dividing circuit 18 synchronized with the horizontal synchronizing signal is inputted to the 'C circuit 15, and even if the horizontal synchronizing signal is dropped, the horizontal AFO circuit 15 operates stably and the screen is stable. As described above, when the circuit of the present invention is implemented in the horizontal synchronization circuit of a portable television receiver, a more stable screen can be obtained than in the conventional portable television receiver.

尚、本発明の回路において、固定発振器の発振周波数が
温度ドリフト等によって変化した場合・タイミング信号
脱落時に発生する内部タイミング信号の周波数は、タイ
ミング信号の周波数と一致しないものになる。しかし、
携帯テレビジョン受像機の水平同期回路を例にとると、
水平同期信号脱落時に発生する内部水平同期信号の周波
数が、水平同期信号の周波数と多少ずれたとしても、第
6図の回路構成にずれば、水平同期信号脱落時の水平A
FO回路内の内部発振周波数のドリフトは、第3図の従
来の回路構成の様に、全く水平AFO回路に入力されな
い場合に比べ、小さく、また再び水平同期信号を入力し
た時の応答性も良くなる。
In the circuit of the present invention, if the oscillation frequency of the fixed oscillator changes due to temperature drift or the like, the frequency of the internal timing signal generated when the timing signal drops does not match the frequency of the timing signal. but,
Taking the horizontal synchronization circuit of a mobile television receiver as an example,
Even if the frequency of the internal horizontal synchronization signal generated when the horizontal synchronization signal is dropped is slightly different from the frequency of the horizontal synchronization signal, if the circuit configuration shown in Figure 6 is used, the horizontal A when the horizontal synchronization signal is dropped
The drift of the internal oscillation frequency within the FO circuit is smaller than when no input is input to the horizontal AFO circuit, as in the conventional circuit configuration shown in Figure 3, and the response when the horizontal synchronization signal is input again is also good. Become.

従って、固定発堝器の発振周波数が温度ドリフ1・等に
よって変化した場合でも、本発明の回路は有効であり、
意義が大きい。
Therefore, even if the oscillation frequency of the fixed oscillator changes due to temperature drift 1, etc., the circuit of the present invention is effective.
It has great significance.

以上のように、本発明によれば、雑音を含み、劣化しや
すい入力タイミング信号から、タイミング信号のみを抽
出する回路において、雑音を除去するだけでなく、タイ
ミング信号脱落時にも、脱落前の状態を維持した内部タ
イミング信号を発生させることができ、タイミング信号
抽出回路と[2て、特に携帯用テレビジョン受像機の水
平同期回路に最適の回路を提供することができる。
As described above, according to the present invention, in a circuit that extracts only a timing signal from an input timing signal that includes noise and is prone to deterioration, it is possible to not only remove noise, but also maintain the state before the timing signal is dropped even when the timing signal is dropped. It is possible to generate an internal timing signal that maintains the same, and it is possible to provide a timing signal extraction circuit and a circuit that is particularly suitable for a horizontal synchronization circuit of a portable television receiver.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は雑音除去回路の従来例、第2図は第1図の回路
の波形図、第3図は従来の水平同期回路の一例を示した
図、第4図は本発明のタイミング信号抽出回路のブロッ
ク図、第5図は第4図の各部の波形図、第6図は本発明
を採用した水平同期回路の実施例を示した図である。 1はタイミング信号入力端子、2は低域フィルタ、3は
抵抗、4はコンデンサ、5はコンパレータ、6は波形成
形回路、7はタイミング信号出力端子、8は真のタイミ
ング信号、9は雑音・10はタイミング信号脱落、11
は複合映像信号入力端子、12は同期分離回路、13は
水平同期信号分離回路、14は雑音除去回路、15は水
平AFC回路、16は水平AFO回路出力端子、1ノは
固定発振器、18は分周回路、19は分周回路の信号出
力端子、20は内部タイミング信号である。 以上 出願人 株式会社諏訪精工舎 第1図 第2図
Figure 1 is a conventional example of a noise removal circuit, Figure 2 is a waveform diagram of the circuit in Figure 1, Figure 3 is a diagram showing an example of a conventional horizontal synchronization circuit, and Figure 4 is a timing signal extraction method of the present invention. FIG. 5 is a block diagram of the circuit, FIG. 5 is a waveform diagram of each part of FIG. 4, and FIG. 6 is a diagram showing an embodiment of a horizontal synchronization circuit employing the present invention. 1 is a timing signal input terminal, 2 is a low-pass filter, 3 is a resistor, 4 is a capacitor, 5 is a comparator, 6 is a waveform shaping circuit, 7 is a timing signal output terminal, 8 is a true timing signal, 9 is a noise, 10 is timing signal dropout, 11
is a composite video signal input terminal, 12 is a synchronization separation circuit, 13 is a horizontal synchronization signal separation circuit, 14 is a noise removal circuit, 15 is a horizontal AFC circuit, 16 is a horizontal AFO circuit output terminal, 1 is a fixed oscillator, and 18 is a separation circuit. 19 is a signal output terminal of the frequency dividing circuit, and 20 is an internal timing signal. Applicant: Suwa Seikosha Co., Ltd. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 入力タイミング信号の周波数の整数倍の周波数で発振す
る固定発振器と、該固定発振器の出力信号を分周し、入
力タイミング信号と同じ周波数の信号を出力するリセッ
ト可能な分周回路と、入力タイミング信号に含まれる雑
音を除去する雑音除去回路により構成され、前記分周回
路は前記雑音除去回路の出力信号でリセットされ、入力
タイミング信号と゛前記分周回路の出力信号と同期をと
る手段を有することを特徴とするタイミング信号抽出回
路。
A fixed oscillator that oscillates at a frequency that is an integral multiple of the frequency of an input timing signal, a resettable frequency divider circuit that divides the output signal of the fixed oscillator and outputs a signal with the same frequency as the input timing signal, and an input timing signal. The frequency dividing circuit is reset by the output signal of the noise eliminating circuit and has means for synchronizing the input timing signal with the output signal of the frequency dividing circuit. Features a timing signal extraction circuit.
JP14531283A 1983-08-09 1983-08-09 Timing signal extracting circuit Pending JPS6037813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14531283A JPS6037813A (en) 1983-08-09 1983-08-09 Timing signal extracting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14531283A JPS6037813A (en) 1983-08-09 1983-08-09 Timing signal extracting circuit

Publications (1)

Publication Number Publication Date
JPS6037813A true JPS6037813A (en) 1985-02-27

Family

ID=15382239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14531283A Pending JPS6037813A (en) 1983-08-09 1983-08-09 Timing signal extracting circuit

Country Status (1)

Country Link
JP (1) JPS6037813A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001183122A (en) * 1999-10-12 2001-07-06 Canon Inc Optical rotational angle detecting device, rotation detecting device, and optical rotational angle detecting method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54120565A (en) * 1978-03-13 1979-09-19 Toshiba Corp Pulse generator
JPS5533568B2 (en) * 1973-12-28 1980-09-01

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5533568B2 (en) * 1973-12-28 1980-09-01
JPS54120565A (en) * 1978-03-13 1979-09-19 Toshiba Corp Pulse generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001183122A (en) * 1999-10-12 2001-07-06 Canon Inc Optical rotational angle detecting device, rotation detecting device, and optical rotational angle detecting method

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