JPS6037781A - Driving method for fet - Google Patents
Driving method for fetInfo
- Publication number
- JPS6037781A JPS6037781A JP14720283A JP14720283A JPS6037781A JP S6037781 A JPS6037781 A JP S6037781A JP 14720283 A JP14720283 A JP 14720283A JP 14720283 A JP14720283 A JP 14720283A JP S6037781 A JPS6037781 A JP S6037781A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- fet
- source
- voltage
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000005669 field effect Effects 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 238000010276 construction Methods 0.000 abstract description 2
- 230000006872 improvement Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
′ｊｇＣ業」ユの利用分野
木５α明は１−（ｆ界ダ’ｒ３ＬＦ’＋リトランジスタ
のワベ１１す１〕−ｆ法に関する。DETAILED DESCRIPTION OF THE INVENTION The application field tree 5α of 'jgC industry' U relates to the 1-(f field d'r3LF'+retransistor wave 11s1)-f method.
従′１１・さ倒の１１５成２−その問題点ｌ１ｌ−Ｖ族
化合物゛１′、導体よりなる♀ニー？界効果型ト５ンジ
スタは、−８ｌを素材２ニする従来のＦＥ′ｒに比べて
僚れ１：高周波特性をｆ′ｉ十ろＦＥ′Ｆとして注１」
されている。中でもＧａＡｓシＢ・リドキーバリアＩｆ
−１−型ＦＥＴ （以下、ＧａＡｓ −ＭＥＳ ＦＥ
Ｔと称す〕は’ｆ’、に速性と低油Ｉυ１ｉ力性の両ン
ｊに６にれており、実用化のＪｉｉ Ｉコ＊ＧａＡｓ・
ＭＥＳ・ＦＥＴ のうち、ヂュアルグ１−ト・ＭｌコＳ
・ＦＥＴは、２つのゲートで独立にソースート１フイン
も
開電流を制御することができ、その高速性をη″かして
、［ＪＨＦ、 ＳＨＦ帯用０チューナや三十す−として
使ワれてきている。Ｅ＋’Ｓ １図はその従）乙のＩ”
Ｅ’ｌ’の＜’Ｊ’ｓ造図、！−模式的な空乏１）７
の１ノζがりを示１−でいる。１１１１図では半絶縁性
ＧａＡｓノ、（板（１）１−に４！ｊｒ活加のｉ型Ｇａ
Ａｓバ”Ｊ ’７７層（２）を介してｎ ７’；９．Ｇ
ａＡｓから成る活性層（３）を形成してＦＥＴがｊ、１
４成されている。ソース１７Ｊ−１極ｍ＋ｃ対し、ドレ
イｙ電！１ｊｉｉ （５）は正、ｌｆ−トＩ″（，１７
４ｉｉ １ｆｉｌ（７）は負の電圧が印加されているＩ
コめ、空乏１ｉ″Ｎ（シ旧弐図のように拡がり、チャネ
ルを流ノー、る電流を・（・ｌＪｉ・：１１することが
できる。しかし本（１す働ｉｌｉにオｊいては、活性層
（３）とバ・ソファ層（２）の界面で、Ｋｉ’ｉ晶ｉ、
：、ｉ−Ｊ、；、７的に不安定な遷移領域（９）ができ
、この部分がチＰンネ１１゜に影響を及ぼすため、ピン
チ１フ７７Ｉ、圧の不！／ト定比、ＮＦの増大などの間
Ｙ″Ｘ１が起こる。まｊこ、ｊｌＩｌｌ 込Ｊ−もソー
ス−ドレイン間に２つのゲートを作る必・３）４ 」−
１その工程がψＩＦシくなり、シングルノｊ゛−トのｌ
ｔ、ｆＥｓ・ＦＥＴに比べ歩留りの低下、特性のばらつ
きを避けられないのが現状である。115 Formation 2 of Sub'11 - Problems l1l - Group V compound '1', ♀ knee made of a conductor? The field effect type transistor has a difference of 1 compared to the conventional FE'r, which uses -8l as the material.
has been done. Among them, GaAs Si B lid key barrier If
-1-type FET (hereinafter referred to as GaAs -MES FE
T] is 'f', and is set at 6 for both speed and low oil Iυ1i strength, and is suitable for practical use.
Among MES/FET, Dualgate/MlcoS
・The FET can independently control the open current of both source and fin with two gates, and by taking advantage of its high speed, it is used as a 0 tuner for the JHF and SHF bands and as a It is coming.E+'S 1 figure is its subordinate)
<'J's construction of E'l'! -Schematic depletion 1)7
It is 1-, which indicates a 1 degree ζ inclination. In Figure 1111, semi-insulating GaAs (I-type Ga with 4!jr activation on plate (1) 1-)
As bar"J' through the 77 layer (2)
An active layer (3) made of aAs is formed to form an FET with j, 1
4 has been completed. For source 17J-1 pole m+c, drain y electric! 1jii (5) is positive, lf-tI″(,17
4ii 1fil(7) is I to which negative voltage is applied
Therefore, the depletion 1i''N(S) can be expanded as shown in Figure 2, and the current flowing through the channel can be . At the interface between the active layer (3) and the bath layer (2), Ki'i crystal i,
:,i-J,;,7 An unstable transition region (9) is created, and this part affects the tip 11°, causing pinch 1f 77I, no pressure! Y″X1 occurs during the constant ratio of /to, increase in NF, etc.It is also necessary to create two gates between the source and drain.
1 The process becomes ψIF, and the single note l
At present, it is unavoidable that the yield is lower and the characteristics vary compared to t, fEs FETs.
発明の目的
本発明は八４１’、Ｓ −ＦＥ１’にＪ５いて１″：Ｊ
ＬれｔこＮＦ持性を得ることができるＦＥｒの駆動方法
を提供することを「１的とする。Object of the Invention The present invention is directed to 841', S-FE1', J5 and 1'':J.
One objective is to provide a method for driving an FEr that can obtain LETNF characteristics.
発明の］Ｒ成
本発明の１’ＩＣ？ｉ’−効果型トラ、−７ジスタの駆
動方法によると、導１１１゛性を有する半導体ツメ７仮
十二に形成されｔこ″１江界効果摩１ ｌうごノジスタ
のｎｌ［記３１（導体基板とソース’Ｉ’ｌ−ｊ １．
＋ｉ！ ｉ：’ｄにｆ？＋圧を加えてチトネＩｌｚ電流
を制御することを１、〒徴とする。[of the invention] 1'IC of the present invention? According to the driving method of the i'-effect type transistor and the -7 transistor, the semiconductor claw 7 having conductivity is formed on the 7 temporary 12, and the nl of the Conductor substrate and source 'I'l-j 1.
+i! i:'d to f? The first characteristic is to control the chitone Ilz current by applying + pressure.
実施例のｊ’、１１ｊ明
り、下、本発明の１１１０・）１方Ｄｅを具体的なりこ
雄側に基づいて１；ｌΔ明Ａ−る。Example j', 11j light, lower, 1110 of the present invention.) One side De is based on the specific Rikoo side 1;
Ｃ１）２図は本発明によるＦＪＥＴのβｆ’、 １ｆｔ
ｆ１ｆｔ上空乏層の拡がりを植式的に示す。１１４−型
ＧａΔＳ半導体Ｊ４（”、Ｌｉ （Ｉｆｆｉ上にｉ 型
ＧａＡｓバ”）ファ層（１）を介し２てｎ型（ｙａ Ａ
５活）゛■ミ１ｉ （１２が戦費されＦＥＴが１１１
７成されている。ソース１１イイｍ（１３ニ対シ、ドｌ
ｙ イｙ ＦＥｒ極（１４）に正、ゲート市： Ｊ＋ｉ
ｉｉ ＯＱに負、さらに基（反オーミ・ツク電極面にｆ
ｌの電圧か印加さね、でいる。空乏；１゛・ｊ（Ｊ力は
（Ｎに示ずようにｊシ、かり、ゲートＩｊイ’ｔｋ ｏ
ｉ ｉ６ ヨ（Ｊ ノ、”’； 板Ａ−Ｅ ”Ｊ ’）
ｉ’：１： ｌ１ｎ（、（ｌｆｉ） ニ加える電圧を
ニノン化さ１Ｊろことにより、）ｊ１！立にト□レイン
・ソース間市、ｂＩＥを徂１イ（・４Ｉする：１かでき
ろ。ｔ ｆこ、界面の不安定な領域か？；・４乏層ｆｒ
ｔ）内に入って１．１．ＦうＴこめ、ＮＦの向上か［；
］メ１．る。C1) Figure 2 shows βf', 1ft of FJET according to the present invention.
The spread of the depletion layer above f1ft is schematically shown. 114-type GaΔS semiconductor J4 (", Li (i-type GaAs buffer on Iffi)") 2 n-type (ya A
5 life) ゛■ Mi 1i (12 were war expenses and FET was 111
7 has been completed. Source 11 good m (13 ni vs. shi, do l
y y Positive to FEr pole (14), gate city: J+i
ii Negative to OQ, and further base (f to anti-ohmic electrode surface)
A voltage of 1 is applied. Depletion; 1゛・j (J force is (as shown in N)
i i6 YO (J ノ, ``'; Board A-E ``J ')
i': 1: l1n (, (lfi) By changing the applied voltage to 1J) j1! Between the train and the source, change the bIE to 1 (・Do 4I: Can you do it? t f Is this an unstable region at the interface?; ・4 depletion layer fr
t) Go inside 1.1. Is it an improvement in NF and NF [;
] Me1. Ru.
本実施例ではＳｉ添加■仕Ｇ；ＩＡＳ（２ＸＩ０１８ｃ
ｍ−３）半導体基板ｕＵ Ｊ−に気相成長？、ノ：に３
１−リｉ ＫＶＧａＡｓ（り１ｘｌＯ”ｃｍ ３）２１
Ｊｍ、 ｎ ７ｑすＧａＡｓ （Ｉ Ｘ １０ ”ｎｎ
”＞（１，８７７１１１の Ｉ萱ソ 〕 ァ ｆｉｌ
ＦＩ＋）、活性Ｊｉ’ｉ （ｌのを順に成Ｉ：：＜シ
１こ。ソース行ら（、じ：（１］、トしイン？ｉ、ｊ’
、 （：ｍ （目）、 ノ占（ｆｉ Ａ”ｆｌ ”）
り １，１）シ’＋ＩＪ’Ｎ にＡｕＧｃ／Ａ、ｕ を
、テ・＼２′ｊ後、ト、へ処理により合金化しでオー
三ツクを完全にした。Ｉｆ−ト１１？極（１！’Ａ Ｉ
：ｉＡ ’； ５： ：）パ、γ１１でドリフトより形
成しｔこ。グーｔ− ４．−、ｊ １ ／ＩＪＺ Ｘ．
す°′ー１ー幅２０１１７ｎ、ソース・トレイン間１’
／Ａ ５ ７１７Ｉ＋としｔこ１・王Ｔ （７） ’ｉ
、テ＋’ｌユ１：ｌｌと（２て、Ｉ ＤＳＳ ＝ ５
ｔｎ． Ａ ％ ｙｙ＋＋ −１ ｉｌ（１ ｔｒｒ．
ｓＡｒ７７＋＋、ＶＴ二２５ポル１−、基板オーニ・ツ
ク７ｔ，（ 、ｒ：：４ｉ７］）らの］ンタクタ：ノス
としＣ２ ０ ｔｎｓ ／ｙｎｍ を１Ｃ？ｆこ。”！
． ｆ−ＮＦ ｉ１＋’ｉは基４ｉ ｆ’ｊ’ｌ ｊＦ
ｉ，圧を０ １ｊし１こ時に対し、■ボルトのバイアス
ｌ’Ｊ’ｊ圧を加えた時、５ｄＢの減少が見られ、界面
の不安定１′］：か特，ｉ４ｉ−に影響を及ぼさなくな
つｔこ事を示している。In this example, Si addition G; IAS (2XI018c
m-3) Vapor phase growth on semiconductor substrate uU J-? ,ノ:ni3
1-ri KVGaAs (ri 1xlO”cm 3) 21
Jm, n 7qsGaAs (I X 10”nn
”>(1,877111 I萱SO) fil
I, j'
, (:m (eyes), ノ divination (fi A"fl")
1,1) AuGc/A,u was added to SI'+IJ'N, and after Te. If 11? Pole (1!'A I
:iA'; 5: :) Formed by drift at γ11. Goo T-4. −, j 1 /IJZ X.
°'-1-width 20117n, source-train distance 1'
/A 5 717I + Toshi tko 1・O T (7) 'i
, te+'lyu1:ll and (2te, I DSS = 5
tn. A % yy++ -1 il (1 trr.
sAr77++, VT225pol1-, boardOnitsuk7t, ( , r::4i7]) et al.: Assuming that C20 tns /ynm is 1C? F-ko. ”!
．． f-NF i1+'i is the group 4i f'j'l jF
i, pressure is 0, 1j and 1, when a bias l'J'j pressure of This shows that there is no longer any impact.
なお、上記実ｒＩＬ例番とおいて半導体材料はＧａＡｓ
として説明しｔこが、これはＩｎｚ−ｘＧａ）（Ａｓ
＋ Ｇａ１−ｙＡ％ＡＳ。In addition, in the above actual rIL example number, the semiconductor material is GaAs.
This is explained as Inz-xGa)(As
+ Ga1-yA%AS.
ＩｎＰなどのＩＩＩ −Ｖ族化合物半導体材料でも同様
の効弔がｉ’．ｌられる。Similar effects can be seen in III-V compound semiconductor materials such as InP. I will be beaten.
発明の詳細
な説明のように本発明の′ｉｉ’，１界効栗型トランジ
スタの１゛区！ｂ１１方法によると、導電性）１（：板
とソース間に電圧を印加して空乏１ｎを基板側から拡げ
てチャネル電流をグー！〜電圧と独立して制ｒ１１する
ｊこめ、づＤセスの容ｋ・）化が「ＩＪ能になり．ＮＦ
特件の優れｔコＦＥＴを作成するこ吉ができるものであ
る。As detailed in the detailed description of the invention, the ``ii'' of the present invention, the 1st section of the 1-field effect chestnut-type transistor! According to the b11 method, the conductivity) 1 (: Apply voltage between the plate and the source to expand the depletion 1n from the substrate side and increase the channel current!~ Control r11 independently of the voltage. Yok・）Nation becomes “IJ Noh.NF
This is what Kokichi can do by creating an excellent t-co FET.
第１図は従来のＦＥＴの４１４Ｙ造と（蓮式的な空乏層
の拡がりの説明図、第２図は本発明によるＦＴ汀のｌ駆
動方法のー；１コ施例雄側乏層の拡がりの説明図である
。
θ（１ 、、、 ｎ４−型ＧａＡｓ半導体基板、（Ｉｔ
） − ｉ 型ＧａＡｓバ・リファ層、（１２ ・ｎ
型ＧａＡｓ活性層、０：Ｃ − ソー スｒＵ 極、（
１４）・・・ドレイン？′ｌ！石れ（１４２−ダ“−ト
市，５（瓶、（１（塾・基（反オーミックＳＵ； 、ｆ
ＶｔＥ、０７）・・空乏１１９、（１［・・界面の不安
定な領域
代理人 へ Ａ＼ 二＜） 弘
第１図
第２図Figure 1 is an explanatory diagram of the conventional FET 414Y structure and the expansion of the depletion layer in a lotus-like manner. θ(1, , n4-type GaAs semiconductor substrate, (It
) − i-type GaAs barrier layer, (12 ・n
type GaAs active layer, 0:C-source rU pole, (
14)...Drain? 'l! Stone (142-Dato City, 5 (bottle, (1) cram school, group (anti-ohmic SU; , f
VtE, 07)... Depletion 119, (1 [... to the unstable region agent at the interface A\2<) Hiro 1 Figure 2
Claims (1)
成されｆ、ｍ電：界′ｊＩＪ果型トうンジスタの前記半
導体基板とソースｆ’！”＋’、 （１・１１間に７ｉ
、ｊ：圧を加えてチＰシネル１ぽ流を制作する電界効Ｌ
ｕ型１へろヲジスタのｒＵ＜動方法。1. The semiconductor substrate and the source of the IJ transistor are formed in the semiconductor substrate and the source f'! "+', (7i between 1st and 11th
, j: Field effect L that creates ChiP sinel 1 flow by applying pressure
rU< movement method of U type 1 gearshifter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14720283A JPS6037781A (en) | 1983-08-10 | 1983-08-10 | Driving method for fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14720283A JPS6037781A (en) | 1983-08-10 | 1983-08-10 | Driving method for fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037781A true JPS6037781A (en) | 1985-02-27 |
Family
ID=15424864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14720283A Pending JPS6037781A (en) | 1983-08-10 | 1983-08-10 | Driving method for fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037781A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5814258A (en) * | 1995-12-28 | 1998-09-29 | Fuji Photo Film Co., Ltd. | Method for forming multilayer sheet or multilayer film |
| US6203742B1 (en) | 1997-08-22 | 2001-03-20 | Fuji Photo Film Co., Ltd. | Method for forming multilayer sheets and extrusion die therefor |
-
1983
- 1983-08-10 JP JP14720283A patent/JPS6037781A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5814258A (en) * | 1995-12-28 | 1998-09-29 | Fuji Photo Film Co., Ltd. | Method for forming multilayer sheet or multilayer film |
| US6203742B1 (en) | 1997-08-22 | 2001-03-20 | Fuji Photo Film Co., Ltd. | Method for forming multilayer sheets and extrusion die therefor |
| US6461138B2 (en) | 1997-08-22 | 2002-10-08 | Fuji Photo Film Co., Ltd. | Device for forming multilayer sheets and extrusion die therefor |
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