JPS6037760Y2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor memory device in which a plurality of memory cells are integrated on the same semiconductor substrate.

The development of semiconductor memory devices has been remarkable, and MOS type semiconductor memory devices in particular have replaced magnetic memories and are now used as the main memory devices of most computers.

In addition, small bits have become the commercial standard for semiconductor memory devices (mainly RAM (Random Access Memory)), and this density will continue to increase, making the commercialization of random bits almost far away. are related.

By the way, semiconductor memory devices centered on MO3 type RAM are constructed by arranging attached circuits such as decoders around a memory cell array, and the conventional idea of increasing the number of bits is to make the memory cell array larger. The idea was to increase the size of the attached circuits placed around it.

However, if the size is larger than Bobbit, the wiring such as bit lines, word lines, and power source lines that drive the memory cells that run through the memory cell array becomes complicated, and along with this, the connections with peripheral circuits are also complicated. Therefore, it is difficult to improve the degree of integration using conventional thinking.

The present invention is a novel invention that attempts to break out of the technical impasse described above, and its purpose is to provide a semiconductor integrated circuit that can improve the degree of integration without complicating the wiring structure. .

The purpose of the above is to integrate a plurality of memory cells on the same semiconductor substrate in a semiconductor memory device, in which signal lines or power lines, etc. of each memory cell are led out from the left and right sides. A first memory column in which memory cell blocks provided with terminal portions are arranged vertically, and a second memory column in which the terminal portions are arranged horizontally opposite to the first memory column; A plurality of two memory columns are arranged in a horizontally integrated manner alternately on the same semiconductor substrate, and a common path line arranged in parallel between the first and second memory columns is arranged on both sides of the pass line. This is achieved by providing a semiconductor memory device characterized in that the terminal portions are connected to each other.

Examples will be described in detail below.

FIG. 1 is a block diagram of a semiconductor memory device that is the basis of the present invention.

In the figure, 1 is a memory cell block.

As shown in FIG. 2, each memory cell block includes, for example, three MO3 type transistors TR□.

3-transistor memory cell 2 consisting of TR2 and TR3
are arranged in a matrix as shown in FIG. A read word line 7, a write word line 8 and a power supply line 9 are led out.

A plurality of memory cell blocks 1 configured in this manner are stacked vertically to form memory columns A and B, as shown in FIG.

Parallel to memory columns A and B, a group of pass lines, 10,
11, 12, and 13 are provided.

The pass line groups 10 and 11 include a refresh and read/write column selection circuit (hereinafter abbreviated as RRC circuit) 14
The pass line groups 12 and 13 are derived from the buffer amplifier 15 in the row direction.

Each pass line constituting each pass line group is connected by a conductor 16 to terminals at predetermined positions of terminal portions 3 and 4 of each memory cell block.

Further, a power supply pass line 17 arranged in parallel with the pass line group is also connected to a predetermined terminal of the terminal section 4.

In FIG. 1, 18 is a row decoder, 19 is a column decoder, and 20 is an input/output circuit.

In this way, if the memory cell array is divided into several blocks, terminals are provided on the left and right sides of each memory cell block, and the parts of these memory cell blocks that do not have terminals are lined up to form a memory block row, the memory cell Each group of pass lines provided between block rows hardly intersects with each other, which simplifies the process.

The present invention further simplifies the wiring structure of the semiconductor memory device shown in FIG.

An embodiment of the present invention will be described below with reference to FIGS. 4 to 6.

That is, as shown in FIG. 4, the memory cells 2 are arranged in a matrix like in FIG. 3, and a terminal portion 21 is provided at the left end of the memory cell 2, and a terminal portion 22 is provided at the right end of the memory cell 2.

Then, read and write word lines are led out to the terminal section 21, and write/read digit lines and power supply lines are led out to the terminal section 22, thereby forming a memory cell block 23.

Another memory cell block 23' has memory cells 2 arranged in a matrix, as shown in FIG. .

Then, read and write word lines are led out to the terminal section 21', and write/read digit lines and power supply lines are led out to the terminal section 22', and the arrangement of the terminal sections is exactly opposite to the left and right sides of the memory cell block 23.

As shown in FIG. 6, a plurality of memory cell blocks 23 are arranged vertically to form first memory columns C and E, and a plurality of memory blocks 23' are arranged vertically to form a second memory column. This memory column is arranged between the first memory columns C and E, and the first memory column and the second memory column whose terminal portions are arranged with the left and right sides reversed are arranged alternately. Arrange them horizontally.

By arranging the memory cell blocks in this way, the path line groups between each memory column will not have a mix of row-direction and column-direction path lines, as shown in Figure 1, and the wiring structure will be further simplified. be done.

As explained in detail above, the present invention consists of memory cells arranged vertically in memory cell blocks with terminals provided on the sides, and the arrangement of the terminals of adjacent memory columns is reversed left and right. Because of this configuration, one pass line can be shared by the left and right memory columns that sandwich it, making the wiring structure extremely simple.For this reason, even if the density of memory cells is increased, the complexity of the wiring can be reduced. The design impasse was resolved.

In addition, although the present invention has been explained about a random access memory using 3M0S transistor cells, it is also possible to use 4-transistor or 1-transistor type M0S memory cells.
The memory cell may be an OS memory cell, a bipolar transistor memory cell, or a static type memory cell based on the basic flip-flop type.

Of course, a read-only type memory cell may also be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor memory device that is the basis of the present invention, FIG. 2 is a circuit diagram of a memory cell, and FIGS. 3 to 5 are layout diagrams of different types of memory cell blocks. FIG. 6 is a block diagram of an embodiment of a semiconductor memory device. In the figure, 1 is a memory cell block, 2 is a memory cell block, 3 and 4 are terminal portions, 10 to 13 are a group of pass lines, and 16 is a conductor.

Claims (1)

[Scope of utility model registration request] In a semiconductor memory device in which a plurality of memory cells are integrated on the same semiconductor substrate, terminal portions are provided on the left and right sides of the plurality of memory cells from which signal lines, power supply lines, etc. of each memory cell are led out. A first memory column in which memory cell blocks arranged vertically and the terminal portion constitute a second memory column arranged horizontally opposite to the first memory column, and the first and second memory A plurality of rows are integrated and arranged on the same semiconductor substrate alternately in the horizontal direction, and terminal portions located on both sides of the pass line are connected to a common pass line arranged in parallel between the eleventh and second memory columns. A semiconductor memory device characterized by being connected.