JPS6037595A - Text graphic display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention uses a 2-star scan type display device to display characters.

This invention relates to a method for displaying text such as symbols and graphics.

Conventional display systems of this type display text such as five characters and graphics in personal computers and video game devices, but the memory for displaying text and the memory for displaying graphics are either separate or shared. . If the text display memory and the graphic display memory are provided separately, the text display and the graphic display can be displayed simultaneously on the same screen, but since the memory is provided separately, the memory capacity is large. Furthermore, when the text display memory and the graphic display memory are shared, the memory capacity becomes smaller, but there is a drawback that text and graphics cannot be displayed at a ratio of about 5 screens.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a text/graphic display method that can simultaneously display text and graphics on a single screen by sharing text display memory and graphic display memory. be.

The text-graphic display system of the present invention includes a first storage means for storing text data and graphic data, a second storage means for generating characters and symbols corresponding to the text data, and a horizontal synchronization counter. a third storage means for storing horizontal display area designation data; a first coincidence circuit for obtaining a coincidence signal between this content and the content of the horizontal synchronization counter; a vertical synchronization counter; and a vertical display. a fourth storage means for storing area designation data; a second coincidence circuit for obtaining a coincidence signal between the contents of the area designation data and the contents of the vertical synchronization counter; and a fifth storage means for storing quadrant designation data. , a predetermined area separated by a predetermined horizontal position and a predetermined vertical position is displayed as text by the outputs of the first and second matching circuits, the horizontal synchronization counter, the vertical synchronization counter, and the fifth storage means. and means for graphically displaying the area.

In the present invention, the display screen is divided into a text display area and a graphic display area, and in the text display area, data read from the text/graphic data memory indicates a character code, and this character code is stored in the character generator memory. Text such as characters is displayed in the text area by reading out character data from and inputting it to the display device. In the graphic display area, the data read from the text/graphic data memory becomes graphic data, and by inputting this to the display device, a graphic display is performed in the graphic area. In the present invention, a text display area is defined as an arbitrary quadrant among four quadrants obtained by dividing a text display area and a graphic display area at arbitrary positions in the horizontal direction (X direction) and vertical direction (Y direction) of the display screen. The remaining part is used as the graphic display area. Furthermore, the entire display screen can be made into a text area or, conversely, a graphics area.

FIG. 1 shows an embodiment of the present invention. Reference numeral 1 denotes a text/graphic data memory for storing graphic data and text data, and uses a RAM. 2 is a character generator memory, ROM (or RA
M) is used. 3 is a horizontal synchronization counter, 4 is a vertical synchronization counter, 5 is a switching circuit, 6, 7.8 are registers, 9.
10 is a matching circuit 10 is a text/graphic switching control circuit, 12 is a switching circuit, 13 is a text color designation register, and 14 is a graphic color designation register.

15 is a switching circuit, 16 is a parallel-serial conversion circuit,
17 is a data bus, and 19 is an address bus.

20 is a read/write signal.

Text data and graphic data are written into the text/graphic data memory 1 at predetermined addresses via the data bus 17, and the signals of the horizontal synchronization counter 3 and vertical synchronization counter 4 are switched during the screen display period. Through the circuit 5, the address of the text/graphic data memory I is read out, and the data is input to the character generator memory 2 and the switching circuit 12.

Specifying the text area and graphics area is 6, 7
．． There are 8 registers, register 6 stores the vertical boundary coordinates, register 7 stores the horizontal boundary coordinates, and 2-bit register 8 indicates which quadrant of the four screen quadrants the text area is in. show. Horizontal synchronization counter 3
A coincidence circuit 9 checks whether the contents of the register and the contents of the register match, and sends the coincidence signal to the text/graphic switching control circuit 11. The contents of the vertical synchronization counter 4 and the register 6 (D match are detected by the match circuit 10, and the match signal is also sent to the text/graphic switching control circuit 11.

FIG. 2 is a specific example of the control circuit 11, where 21°22 is the free lag 7Rozzo, 23.24 is the HXOR gate, and 25
is an AND gate, and the flip 7g6-tube 22 is set during the horizontal blanking period by the signal shown in FIG. 3(a) of the horizontal synchronization counter 3.
It is reset by the output of the coincidence circuit 9 and obtains the output shown in FIG. Figure 3 (
Obtain the output shown in C).

EXOR when the lower bit of register 8 is 0#.

The output of the gate 24 is shown in FIG. 3(b), and when it is 11#, the output of the flip-flop 22 is inverted and the output of the gate 24 is
The output will be +d) in Figure 3. When the upper bit of the register 8 is “0#”, the output of the FXOR gate 23 becomes as shown in FIG. 3(C), and when it is “1”, the output of the EXOR gate 23
The output is shown in FIG. 3(e). Therefore AND gate 25
The output of register 8 is shown in Figure 3 (f
), in gas “10” (h), “1”
1” becomes (i).

The output of the AND gate 25 in FIG. 2 is the control circuit 1 in FIG.
1 output, and when this output is 1'', it indicates a text state, and the switching circuit 12 is connected to the character generator R.
The output of OM2 is sent to the parallel-serial conversion circuit 16. Further, the data in the text color designation register 13 is sent to the parallel-serial conversion circuit 16 through the switching circuit 15.

This circuit 16 outputs a serial signal of the color specified by the text color specification register 13. When the output of the control circuit 11 is @0'', it indicates a graphic state, and the switching circuit 1
2 sends the output of the text/graphic data memory 1 to the parallel-serial conversion circuit 16. Further, the data in the graphic color designation register 14 is passed through the switching circuit 15 and sent to the parallel-serial conversion circuit 16. Conversion circuit 1
6 outputs a serial signal of the color designated by the graphic color designation register 14.

At the timing shown in Figure 3), only part 26 is a text area and the remaining 27.28°29 is a graphics area, as shown in Figure 4. Similarly, in Figure 3 (27 at gl)
, 28 in case of (h), and 29 in case of (i).

According to the invention, in any horizontal and vertical position.

The text display area and graphic display area can be specified, and there is no need to have separate text display memory and graphic display memory, so memory usage can be reduced.
The effect is particularly large in low-cost video games and personal computers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an entire embodiment of the present invention, FIG. 2 is a circuit diagram showing the text/graphic switching control circuit in FIG. 1, FIG. 3 is a timing diagram showing the operation of FIG. 2, and FIG. FIG. 4 is a display diagram showing the display area in the embodiment of the present invention. 1...Text-graphic data memory,
2...Character generator memory, 3.
...Horizontal synchronization counter, 4...Vertical synchronization counter, 5゜12.15...Switching circuit, 6,
7, 8, 13.14...Register, 9.10.
... Matching circuit, 11... Text/graphic switching control circuit, 16... Parallel-serial conversion circuit, 17... Data bus, 9-19... ...address bus, 21, 22, old flip-flop, 23, 24, EXOR gate, 25, AND gate. 10- -V 匈Ya currency α and

Claims (1)

[Scope of Claims] A first storage means for storing text data and graphic data, a second storage means for generating characters and symbols corresponding to the text data, a horizontal synchronization counter, and a horizontal display area. a third storage means for storing designated data; a first matching circuit for obtaining a matching signal between the content and the content of the horizontal synchronization counter; a vertical synchronization counter; and a third storage means for storing vertical display area designation data. 4 memory means. a second matching circuit that obtains a matching signal between the content and the content of the vertical synchronization counter; and a fifth matching circuit that stores quadrant designation data.
A predetermined area separated by a predetermined horizontal position and a predetermined vertical position is stored as a text by the outputs of the storage means, the first and second matching circuits, the horizontal synchronization counter, the vertical synchronization counter, and the fifth storage means. and means for displaying the remaining area as a graphic display.