JPS6036146B2 - Error generating circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error generating device that generates pseudo-errors that occur in digital communications or the like.

Errors that occur in digital communications or digital recording on magnetic tape include random errors and burst errors.

Among them, the Gilbert model of a single Markov process is known as a burst error generation model. A state transition diagram of this model is shown in Figure 1. In FIG. 1, G represents the state of enemy od, B represents the state of Shigeru d (or Bu dai), and P, Q, p, and q are state transition probabilities, respectively. Here, P1Q=1, p1Q=1, and the probability of not making an error in state B is h. This Gilbert model is said to closely match burst errors that occur in digital communications or magnetic tape. Conventionally, error generating circuits that generate random errors are known, but no error generating circuit that takes the Gilbert model into consideration has been found.

An object of the present invention is to provide an error generation circuit that can generate a pseudo error signal that closely matches the errors that occur in digital communications or magnetic tape as described above.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of an error generation circuit according to an embodiment of the present invention. In the figure, 1 is a clock generation circuit, 2 is an M-sequence generation circuit (pseudo-random pattern generation circuit), and 3 is a clock generation circuit.
4 is a shift register, 4 is a memory circuit, 5 is a latch circuit, 6 is a counter, 7 is a comparator, and 8 is an output terminal. Next, the operation will be explained.

The clock signal from the clock generating circuit 1 drives the M-sequence generating circuit 2 to generate a pseudo-random pattern.

A pseudorandom pattern can be generated, for example, in the circuit shown in FIG. In FIG. 3, 9 is an input terminal, 21 is a 31-stage shift register, and 22 is EXCLUSI.
In the VEOR circuit, 10 is an output terminal, and the sequence lengths in the circuit of FIG. 3 are 2147, 483, and 647.
The pseudo-random pattern generated by the M-sequence generation circuit 2 is
The shift register 3 serves as a read address for the memory circuit 4, and the data read from the memory circuit 4 is latched by the latch circuit 5. On the other hand, counter 6
The clocks are counted, and the output of the clock is compared with the output of the latch circuit 5 by a comparator 7. When the two values match, the output of the comparator 7 becomes "1" level. Then, after one clock time, it becomes the "0" level, and at this falling edge, data is taken into the latch circuit 5 and the counter 6 is reset. In this way, an error output is sent to the output terminal 8. Here, the data stored in the memory circuit 4 uses run distribution based on the Gilbert model.

The run distribution U(1bi) is a distribution of the frequency at which K error-free bits occur consecutively after an error occurs, and is given by the following equation from P, h, and p. U(1bi)=A・J
K+(11A)LKHere, A, J, and L are each A=Upper 3 J-L J:Q+hq+Zo's ten dream qzo+4h(p one rule L:Q+h
q-zonu tenmu q〆10 is p-Q2.

This distribution is as shown in FIG.

The memory circuit includes a 256 x 8 bit ROM (ReadO
nlyMemory), P=4×10-7
, p=2×10-2, and h=0.5, the run distribution is approximated by a frequency distribution as follows. By storing this frequency in the ROM and reading it out at a random address from the M-sequence generation circuit 2, a burst error can be obtained.

Approximation errors due to frequency distribution can be reduced by using a ROM with a capacity of IK x 8 bits or more, but
In the above case, 256×8 bits is sufficiently practical.
It goes without saying that the frequency distribution changes by changing P, p, and h. Furthermore, even if P, p, and h have the same value, the order in which errors occur can be easily changed by changing the memory address where the frequency distribution is stored. In addition, although the comparator 7 is used in Fig. 2, if a counter with a LoadLnput terminal is used, the boro output when subtracting the clock can be used instead of the comparator 7 output. can.

It is also possible to store the complement in the memory circuit 4 and use the carry output produced by counting the clocks. Further, in the above embodiment, in both state B and state G, the counter 6
Although the same clocks are counted in the above example, the counting in the case of state G is repeated once as well.

Therefore, the counter 6 requires five 4-bit binary counters. Therefore, when sending error output to N data circuits or tracks, clock generation circuit 1
, M-sequence generation circuit 2, shift register 3, and memory circuit 4 can of course be used in common, but the counter 6
Only 5×N pieces of hardware are required. In order to save this time, it is preferable to use a plurality of clocks as shown in FIG. In the block diagram of FIG. 5, 11 is a frequency dividing circuit, 12 is a selection circuit, 13 is an input terminal for selection control, and 14 is an output terminal. FIG. 5 shows a case where there are two clocks; in state G, the frequency-divided clock is selected, and in state B, the original clock is selected. Input terminal 1
3 can be controlled by adding a flag indicating whether the state is G or B to the data from the memory circuit 4. It goes without saying that in the case of state G, there may be a plurality of clocks depending on the distribution. As described above, according to the error generating device of the present invention, by storing data using run distribution in a memory circuit and giving pseudorandom data as its read address, errors that actually occur can be detected with a simple configuration. This has the effect of providing a good match.

[Brief explanation of the drawing]

FIG. 1 is a state transition diagram of the Gilbert model, FIG. 2 is a block diagram of an error generation circuit according to an embodiment of the present invention, and FIG.
4 is a diagram showing an example of the M-sequence generation circuit of FIG. 2, FIG. 4 is a diagram showing a run distribution based on the Gilbert model, and FIG. 5 is a block diagram of a clock selection circuit in another embodiment of the present invention. In the figure, 1 is a clock generation circuit, 2 is an M-sequence generation circuit (pseudo-random pattern generation circuit), 3 is a shift register, 4 is a memory circuit, 5 is a latch circuit, 6 is a counter, 7 is a comparator, and 11 is a frequency divider. The circuit 12 is a clock selection circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A clock generation circuit, a pseudo-random pattern generation circuit, a memory circuit in which the pseudo-random pattern from the pseudo-random pattern generation circuit is used as a read address, and a numerical value read from the memory circuit. 1. An error generating circuit comprising: a counter circuit that counts clocks up to the maximum; and a gate circuit that generates an error of one clock time each time the counter circuit finishes counting. 2. The counter circuit divides the frequency of the clock from the clock generation circuit using a frequency dividing circuit, and selects and counts a plurality of frequency-divided clocks and the original clock based on a value read from the memory circuit. An error generating circuit according to claim 1, characterized in that: 3. The error generating circuit according to claim 1 or 2, wherein the memory circuit stores data using run distribution.