JPS57197912A - Time random number generator - Google Patents

Time random number generator

Info

Publication number
JPS57197912A
JPS57197912A JP56082738A JP8273881A JPS57197912A JP S57197912 A JPS57197912 A JP S57197912A JP 56082738 A JP56082738 A JP 56082738A JP 8273881 A JP8273881 A JP 8273881A JP S57197912 A JPS57197912 A JP S57197912A
Authority
JP
Japan
Prior art keywords
random number
signal
timing
inputted
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56082738A
Other languages
Japanese (ja)
Inventor
Hiroshige Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP56082738A priority Critical patent/JPS57197912A/en
Publication of JPS57197912A publication Critical patent/JPS57197912A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

PURPOSE:To easily obtain a random signal by delaying a timing signal in accordance with the output of a random number generating circuit. CONSTITUTION:When a start signal t3 is inputted, a timing generating circuit 1 generates timing signals t2 and t1. Every time the timing signal t2 is inputted, a random number generating circuit 2 generates and sends n-bit random numbers ar0-arn-1 to a counter 3a. The counter 3a and a gate 36 form a delay circuit; every time the timing signal t1 is inputted, a random number is set and when a clock signal phi is counted down until the contents reach 0, an output tr is generated. The delay time from the input of the timing signal t1 to the generation of the output tr varies with the random number, so a random number is obtained.
JP56082738A 1981-05-29 1981-05-29 Time random number generator Pending JPS57197912A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56082738A JPS57197912A (en) 1981-05-29 1981-05-29 Time random number generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56082738A JPS57197912A (en) 1981-05-29 1981-05-29 Time random number generator

Publications (1)

Publication Number Publication Date
JPS57197912A true JPS57197912A (en) 1982-12-04

Family

ID=13782750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56082738A Pending JPS57197912A (en) 1981-05-29 1981-05-29 Time random number generator

Country Status (1)

Country Link
JP (1) JPS57197912A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55121757A (en) * 1979-03-14 1980-09-19 Mitsubishi Electric Corp Error generating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55121757A (en) * 1979-03-14 1980-09-19 Mitsubishi Electric Corp Error generating circuit

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