JPS57174958A - Pseudo error pulse inserting circuit - Google Patents

Pseudo error pulse inserting circuit

Info

Publication number
JPS57174958A
JPS57174958A JP6094981A JP6094981A JPS57174958A JP S57174958 A JPS57174958 A JP S57174958A JP 6094981 A JP6094981 A JP 6094981A JP 6094981 A JP6094981 A JP 6094981A JP S57174958 A JPS57174958 A JP S57174958A
Authority
JP
Japan
Prior art keywords
pseudo random
data
random pattern
pseudo
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6094981A
Other languages
Japanese (ja)
Inventor
Takahiro Suemitsu
Takashi Yanagisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6094981A priority Critical patent/JPS57174958A/en
Publication of JPS57174958A publication Critical patent/JPS57174958A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To achieve adjustment and test only with a transmission and reception data processing section, by inserting a pseudo random pulse having no correlation to data. CONSTITUTION:After a clock signal is frequency-divided at a frequency divider 2, a pseudo random pattern generator 3 is driven. A pseudo random pattern for input data series is picked up from outputs T0-Tn-1 of each stage of an N stage pseudo random pattern generator 3. The pseudo random pattern is inserted to a dta train via an exclusive logical sum 5. As a result, the polarity of data of the same time slot as the pseudo error pulse is inverted. This inverted part becomes the data error. The data error rate is determined by adjusting the frequency dividing ratio of the frequency divider 2.
JP6094981A 1981-04-21 1981-04-21 Pseudo error pulse inserting circuit Pending JPS57174958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6094981A JPS57174958A (en) 1981-04-21 1981-04-21 Pseudo error pulse inserting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6094981A JPS57174958A (en) 1981-04-21 1981-04-21 Pseudo error pulse inserting circuit

Publications (1)

Publication Number Publication Date
JPS57174958A true JPS57174958A (en) 1982-10-27

Family

ID=13157147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6094981A Pending JPS57174958A (en) 1981-04-21 1981-04-21 Pseudo error pulse inserting circuit

Country Status (1)

Country Link
JP (1) JPS57174958A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000028709A1 (en) * 1998-11-11 2000-05-18 Kabushiki Kaisha Kenwood Dummy error addition circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178679A (en) * 1974-12-28 1976-07-08 Takeda Riken Ind Co Ltd
JPS55121757A (en) * 1979-03-14 1980-09-19 Mitsubishi Electric Corp Error generating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178679A (en) * 1974-12-28 1976-07-08 Takeda Riken Ind Co Ltd
JPS55121757A (en) * 1979-03-14 1980-09-19 Mitsubishi Electric Corp Error generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000028709A1 (en) * 1998-11-11 2000-05-18 Kabushiki Kaisha Kenwood Dummy error addition circuit
US6772378B1 (en) 1998-11-11 2004-08-03 Kabushiki Kaisha Kenwood Dummy error addition circuit

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