JPS6035987A - Controller of motor - Google Patents

Abstract

PURPOSE:To accurately perform a PLL control in a wide range with a simple configuration by utilizing a counter in a microcomputer and controlling a regulator by the microcomputer. CONSTITUTION:The first counter 3A generates a reference frequency signal FS in accordance with a motor speed command from ten keys 1, and the second counter 3B generates a speed control signal FV synchronously with a feedback signal FG from an encoder 12. A phase comparator 5 outputs a phase comparison signal PC between the signals FS and FG. The signals FV and PC are added by an adder 8, converted by a comparator 9 to a pulse width modulation signal, and supplied to a driver 10. A microcomputer 3 varies the electronic volumes 13-16 when the phase difference is not locked, and regulates them.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a motor control device used in a copying machine, etc., and in particular, the invention relates to a control device for a motor used in a copying machine, etc. The present invention relates to a PLL speed control device suitable for continuously controlling a PLL speed control device.

[Prior art and its problems]

Conventionally, this type of device consists of hardware, and in order to continuously change the speed of the motor, a frequency divider is used to divide the reference frequency or the feedback frequency from the encoder of the drive motor. Furthermore, since the control range is wide, it is necessary to adjust and switch each element such as a filter, which has the disadvantage of increasing the size of the device.

[Purpose of the invention]

This invention was made to eliminate the above-mentioned drawbacks, and aims to miniaturize the device by using a microcomputer, and to perform high-precision, wide-range PLL speed control using the microcomputer. .

〔Example〕

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this figure, 1 is a numeric keypad that specifies the speed of the motor, 2 is an oscillator that drives the counter inside the microcomputer, and 3 is a microcomputer (hereinafter referred to as microcomputer) that controls the speed. 3
The first counter 3A counts the clock of the oscillator 2 and generates a reference frequency signal FS for phase comparison according to the motor speed specified from the numeric keypad 1. The second counter 3B is synchronized with a feedback signal FG from an encoder, which will be described later, and generates a speed control signal FV of constant width pulses in accordance with motor speed designation. 4 is the output line, 5
A phase comparator generates a phase comparison signal PC from the reference frequency signal FS outputted from the output line 6 of the microcomputer 3 and the feedback signal FG, and outputs it to the output line 7. 8 is an addition circuit for the phase comparison signal PC and the speed control signal FV, 9 is a comparator that performs pulse width modulation (PWM), 10 is a driver that drives the motor, 11 is a motor, and 12 is the motor 1
A feedback signal FG is generated by an encoder that detects the rotation of 1, and is input to the microcomputer 3 and the phase comparator 5. 13-16
is an electronic volume, and 17 is a capacitor. Also, 1
8 is the FV gain control signal, 19 is the PC gain control signal, 2o
is a filter control signal, and 21 is a threshold level control signal.

Incidentally, continuous magnification change of the motor 11 can be realized by continuously changing the scanning speed of the optical system when the drum speed is constant. When the frequency of the feedback signal FG of the encoder 12 of the motor 11 for driving the optical system is 1 KHz (period T = 1 ms) during full-scale copying, and the magnification is changed in steps of 1%, the period T changes every 0.01 m5. do. In order to invert the output port every time the first counter 3A counts up, the oscillator 2 is set to T (100KH).
z) and set a count value corresponding to the magnification in the first counter 3A, the reference frequency signal FS is generated.
is creating.

Next, an outline of the operation of the embodiment shown in FIG. 1 will be explained.

The adder circuit 8 receives the speed control signal F output from the microcomputer 3.
V and the phase comparison signal PC from the phase comparator 5 are added, and the output is integrated by a filter consisting of an electronic volume 15 and a capacitor 17, and then P is determined by the threshold level determined by the electronic volume 16 of the comparator 9.
WM, the motor 11 is driven by the driver 10,
It is controlled to have a constant phase difference from the reference frequency signal FS according to the motor speed command from the numeric keypad 1.

Furthermore, a predetermined iC1 according to the specified magnification
The microcomputer 3 sets the values of the electronic volumes 13 to 16 to control the addition gain ratio, filter characteristics, and threshold level of the phase comparison signal PC and the speed control signal FV. The threshold level is also controlled by the lock signal of the phase comparator 5.

The phase comparison and speed control method will be explained with reference to the flowchart of FIG. 2 and the waveform diagram of FIG. 3. In addition, the second
In the figure, (1), (2), . . . represent steps.

Input the speed setting (magnification) of the motor 11 using the numeric keypad 1 (1). If there is a change in the set value (2), the set value (data) is set in the first counter 3A (3) and a countdown is started.

Here, after the countdown of the first counter 3A is completed, an interrupt signal is generated, the set value is automatically reset, and the countdown is repeated. This generates the reference frequency signal FS. This reference frequency signal FS is then applied to the phase comparator 5. Furthermore, the values of the electronic volumes 13 to 16 are set to values corresponding to the magnification (4).

Next, the speed control signal FV will be described. An FG interrupt is entered at the fall of the feedback signal FG from the encoder 12 of the motor 11, and after saving the register (11), the speed control signal FV is reset (12), and 1/2 FS of the reference frequency signal FS corresponding to the multiplication factor is generated. The timer value becomes 2nd counter 3
Set to B and start (13), the phase difference is O~2
If it is π (14), the process returns after the register is restored (18). If the phase difference is not 0 to 2π (14), but 2π or more (15), lower the threshold level 16), otherwise increase the threshold level 17), and after returning the register (18), Return. After the countdown of the second counter 3B is completed, an FV interrupt occurs, and after saving the register (21), the speed control signal FV is set (22), and the speed control ill signal FV shown in Fig. 3 is generated. After that, the register is restored (23) and the process returns.

The phase comparison signal PC has a phase difference of O~2 as shown in FIG.
When π, the phase comparison signal PC is repeatedly set and reset at the falling edge of the reference frequency signal FS and the feedback signal FG, and when the phase of the feedback signal FG is 2π or more, the phase comparison signal PC is set. After detecting that the feedback signal FG falls twice during one period of the reference frequency signal FS, the above-described operation with a phase difference of 0 to 2π is repeated.

Conversely, when the phase of the feedback signal FG advances, that is, when the phase difference becomes 0 or less, the phase comparison signal PC maintains the reset state, and the reference frequency signal FS increases during one cycle of the feedback signal FC. After detecting that the falling edge has occurred twice,
The above-mentioned operation with a phase difference of O to 2π is repeated.

Furthermore, when the phase difference is O to 2π, the phase comparator 5
When the feedback signal FG is delayed by a phase difference of 2π or more, it outputs a 2-bit lock signal of 01, and when the phase difference of the feedback signal FG is 0 or less, it outputs a 2-bit lock signal of 10. , the microcomputer 3 reads this and controls it in the FG interrupt routine.

In the above embodiment, the reference clock for the counter 3A is generated by the external oscillator 2, but it is also possible to use the oscillator in the microcomputer 3 internally as the timer reference clock, and the drive for the motor 11 can be controlled by PWM. This is done at the DC level, but it may also be done at the DC level. Also,
In order to adjust the characteristics of the filter, the capacitor 17 may be switched instead of the electronic volume 15.

〔Effect of the invention〕

As described in detail below, according to the present invention, a counter inside a microcomputer is used, each adjustment part is set to a value according to a specified magnification, and each adjustment part is set so that the phase difference is not locked. Since it is controlled by a microcomputer, highly accurate PLL speed control can be performed over a wide range with a simple configuration. Furthermore, by introducing a microcomputer, external peripheral equipment can be made smaller, which has the advantage that the entire device can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of FIG. 1, and FIG. 3 is a waveform diagram of the same main part. In the figure, 1 is a numeric keypad, 2 is an oscillator, 3 is a microcomputer, 3A
is a counter, 4 and 6 are output lines, 5 is a phase comparator, 7 is an output line, 8 is an addition circuit, 9 is a comparator, 10 is a driver, 11 is a motor, 12 is an encoder, 13 to 16 are electronic volumes, 17 18 is a capacitor, 18 is an FV gain control signal, 19 is a PC gain control signal, 20 is a filter control signal, and 21 is a threshold level control signal.

Claims (1)

[Claims] an input means for inputting a desired rotational speed of the motor; a means for generating a reference frequency signal by generating an internal interrupt signal by a first counter whose count value is set in accordance with the input from the input means; and a means for generating a reference frequency signal from the input means. a second counter that generates a speed control signal with a constant pulse width in response to the input of the motor; and an external interrupt signal based on a feedback signal from an encoder that detects the reference frequency signal and the rotation speed of the motor. means for detecting a phase difference and outputting a phase comparison signal; means for controlling the motor to the desired rotation speed using the phase comparison signal and the speed control signal; and an adjusting portion included in the controlling means. 1. A motor control device comprising: means for adjusting using the 111 force of a microcomputer; and means for controlling the adjusting means when the phase difference is not locked by the microcomputer.