JPS63154087A - Controller for motor - Google Patents

Abstract

PURPOSE:To optimize the ON-OFF ratio of a PWM drive waveform at all times, and to turn a motor smoothly by selecting the optimum driving voltage of the motor from among a plurality of voltage supply means according to the speed of the motor. CONSTITUTION:A phase comparator 5 compares a feedback signal FG from an encodor 11 and a reference frequency signal FS, and outputs a phase comparison signal PC. An adding circuit 8 adds a speed control signal FV output from a microcomputer 3 to the phase comparison signal PC. A comparator 9 converts an output from the adder 8 into a PWM signal by a threshold level determined by an electronic volume 16, and transmits the PWM signal to a driver 10. On the other hand, a select signal generating circuit 23 selects any of power supplies 28-31 driving the motor 11 according to magnification information selected by a ten key 1.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a DC motor control device.

[Conventional technology]

Conventionally, when constant speed control of a direct current (DC) motor used in a copying machine is performed by phase (PLL) control, a drive voltage is supplied by pulse width control (PWM). P.W.
Since the period of M is constant, the average voltage to be supplied to the motor is determined according to changes in the on-off duty ratio corresponding to changes in the speed of the DC motor.

However, if the speed variable range of the motor is large, the on-off duty ratio may be controlled at an unbalanced position, so optimizing fast speed control makes slow speed control unstable. Moreover, in the opposite case, there is a problem in that high speed control becomes unstable.

[Problem that the invention seeks to solve]

Therefore, the purpose of the present invention is to solve such problems,
An object of the present invention is to provide a motor control device that can optimize the pulse waveform for driving when the speed of the motor to be controlled has a wide variable range.

[Means for solving problems]

In order to achieve such an object, the present invention provides a detection means for detecting the speed of a motor, a voltage supply means for generating mutually different voltages and capable of supplying the voltages to the motor, and a detection means for detecting the speed of the motor. a selection means for selectively selecting a voltage supply means having an appropriate supply voltage from among the plurality of voltage supply means according to the selected speed; and a detection means for detecting the supply voltage of the selected voltage supply means. The motor is characterized by comprising a control means for variably setting the speed of the motor by controlling the pulse width according to the detected speed.

[Effect]

The present invention selectively selects the optimum motor drive voltage according to the motor speed from among a plurality of voltage supply means using the selection means, and controls the pulse width of this voltage to control the motor speed. When the speed of the controlled motor has a wide variable range, the pulse waveform for driving can be set to an optimal waveform.

(Example〕 FIG. 1 shows an example of a circuit configuration in an embodiment of the present invention.

In FIG. 1, numeral 1 is a numeric keypad for specifying the speed of the motor, and numeral 2 is an oscillator that drives an internal counter of the microcomputer 3. 3 is a microcomputer (hereinafter referred to as microcomputer) that performs speed control;
has a first counter 3A and a second counter 3B.

This first counter 3^ counts the clock of the oscillator 2 and generates a reference frequency signal FS for phase comparison according to the motor speed designation from the numeric keypad 1.

The second counter 3B is synchronized with a feedback signal FG from an encoder, which will be described later, and generates a speed control signal FV of constant width pulses in accordance with motor speed designation.

4 is an output line for the signal FV, and 5 is a phase comparator.

The phase comparator 5 creates a phase comparison signal pc from the reference frequency signal FS outputted from the output line 6 of the microcomputer 3 and the feedback signal FG, and outputs it to the output line 7. 8 is an addition circuit for the phase comparison signal pc and the speed control signal FV, and 9 is a comparator for performing pulse width modulation (PWM).

IO is a driver that drives the motor, and 11 is a motor.

Reference numeral 12 denotes an encoder that detects the rotation of the motor 11. The encoder 11 generates a feedback signal FC and inputs it to the microcomputer 3 and the phase comparator 5. 13 to 16 are electronic volumes, and 17 is a capacitor. Further, 18 is an FV gain control signal, 19 is a PC gain control signal, 20 is a filter control signal, and 21 is a threshold level control signal.

Incidentally, continuous magnification change of the motor 11 can be realized by continuously changing the scanning speed of the optical system when the drum speed is constant. When the frequency of the feedback signal FG of the encoder 12 of the motor 11 for driving the optical system is set to lKH2 (period 7 = lIIIs) during full-scale copying, and the magnification is changed in increments of 1%, the period T changes in increments of 0.01 m5. do. In order to invert the output port each time the first counter 3^ repeats counting up, the oscillator 2 is set to T (too
The reference frequency signal FS is generated by oscillating at a frequency (ttttz) and setting a count value corresponding to the magnification in the first counter 38.

28.29, 30.31 are drive power sources for the motor 11, 23
is a selection signal generation circuit for selecting a driving power source.

Next, an outline of the operation of the embodiment shown in FIG. 1 will be explained.

The adder circuit 8 receives the speed control signal F output from the microcomputer 3.
V and the phase comparison signal PC from the phase comparator 5 are added. The output is integrated by a filter consisting of a multiplex volume 15 and a capacitor 17, and then PWMed by a threshold level determined by an electronic volume 16 of the comparator 9.

Then, the motor 11 is driven by the driver 10 and controlled to have a constant phase difference from the reference frequency signal FS according to the motor speed command from the numeric keypad 1.

Further, the microcomputer 3 sets the values of the electronic volumes 13 to 16 to predetermined values according to the specified magnification, and controls the addition gain ratio, filter characteristics, and threshold level of the phase comparison signal pc and the speed control signal FV. . The threshold level is also controlled by the lock signal of the phase comparator 5.

At the same time, depending on the magnification information selected by the numeric keypad 1, the above-mentioned power supply selection signal is sent from the microcomputer 3 to the output line 2.
Power supplies 28 and 29 that drive the motor 11 by the 1 selection signal generation circuit 23 which is input from 2 to the selection signal generation circuit 23.
．． Output a selection signal to select one of 30.31,
The motor 11 is driven by the output voltage of the selected power source.

The phase comparison and speed control method will be explained with reference to the flowchart of FIG. 2 and the waveform diagram of FIG. 3. In addition, the second
In the figure, (1), (2), . . . represent steps.

Input the speed setting (magnification) of the motor 11 from the numeric keypad 1 (1), if there is a change in the setting value (2), set the setting value (data) in the first counter 3^ (3), and start the countdown. let Here, after the countdown of the first counter 3A is completed, an interrupt signal is generated, the set value is automatically reset, and the countdown is repeated.

This generates the reference frequency signal FS. This reference frequency signal FS is then applied to the phase comparator 5. Furthermore, the values of the electronic volumes 13 to 16 are set to values corresponding to the magnification (4).

Next, the data of the power supply selection signal is set in the memory in accordance with the magnification and outputted to a predetermined output port (5).

Naturally, the values of the electronic volumes 13 to 16 and the power source selection signal data influence each other and are selected.

Generally, in a copying machine, the speed of the optical system motor is faster as the reduction ratio increases, and as the enlargement ratio increases, the speed of the optical system motor becomes slower. Therefore, for example, if a magnification of 50% to 142% is selectable, a speed of 50% is about three times as fast as a speed of 142%.

FIG. 4 shows the S-T curve of the DC motor.

For example, when using a DC motor with a rated voltage of 20V,
If a speed of 50% is driven near the rated voltage, a speed of 142% results in a driving voltage of about several volts. FIG. 5 shows a PWM waveform for driving the motor when the driving voltage is constant. Figure 5-1 shows the PWM waveform at 142% speed, and Figure 5-2 shows the PWM waveform at 50% speed.
The WM waveform is shown. FIG. 6 shows a PWM waveform when the drive voltage according to the present invention is selected depending on the rotation speed. No. 8-1
The figure shows a PWM waveform at 50% speed, and FIG. 6-2 shows a PWM waveform at 142% speed.

Next, the speed control signal FV will be described. An FG interrupt is entered at the fall of the feedback signal FG from the encoder 1z of the motor 11, and after saving the register (11), the speed control signal FV is reset (12). Set the timer value that is 2FS to the second counter 3B and start it (13), and the phase difference will be 0 to 2FS.
If it is 2π (14), return after the register is restored (!8).

If the phase difference is not between 0 and 2π (14), and if it is 2π or more (15), then the threshold level should be lowered (16).
If not, please increase the threshold level17
), and after the register is restored (18), return.

After the countdown of the second counter 3B is completed, an FV interrupt occurs, and after saving the register (21), the speed control signal FV is set (22), and the speed control signal FV shown in FIG. 3 is generated. , restore the register (2
3), Return.

The phase comparison signal PC has a phase difference of 0 to 2 as shown in FIG.
When π, the phase comparison signal PC is repeatedly set and reset at the falling edge of the reference frequency signal FS and feedback signal FG. If the phase of the feedback signal FG is delayed by 2π or more, the phase comparison signal pc remains set and the reference frequency signal F
It is detected that the feedback signal F6 falls twice during one cycle of S. After this, the above-described operation with a phase difference of O to 2π is repeated.

Conversely, when the phase of the feedback signal FG advances, that is, when the phase difference becomes O or less, the phase comparison signal pc maintains the reset state, and the reference frequency signal FS is After detecting that the falling edge has occurred twice, the above-mentioned operation with a phase difference of O to 2π is repeated.

Furthermore, when the phase difference is O to 2π, the phase comparator 5
It outputs a 2-bit lock signal of "00", "01" when the feedback signal F6 is delayed by a phase difference of 2π or more, and "lO" when the phase difference of the feedback signal FG is less than O. , the microcomputer 3 reads this and controls it in the FG interrupt routine.

In the above embodiment, the reference clock for the first counter 3^ is generated by the external oscillator 2, but it is also possible to use the oscillator in the microcomputer 3 internally as the timer reference clock.

〔Effect of the invention〕

As explained above, according to the present invention, the DC motor
When constant speed control is performed using L control and the drive is converted to PWM, PWM I! ! Since the on-off ratio of the motor waveform is always controlled at the optimum level, the motor rotates more smoothly, and uneven rotation can be prevented, especially when rotating at a constant speed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a configuration example of an embodiment of the present invention, Fig. 2 is a flowchart explaining the operation of Fig. 1, and Fig. 4 is an explanation showing the characteristics of the rotation speed and torque of the DC motor in the embodiment of the present invention. It is a diagram. 1...numeric keypad, 2...oscillator, 3...e microcomputer, 3^...counter, 4.6...output line, 5...° phase comparator, 7...output line, 8... Addition circuit, 9... Comparator, IO... Driver, 11... Motor, 12... Encoder, 13-16... Electronic volume, 17... Capacitor, 18... FV gain control signal, 19... PC gain control signal, 20... Filter control signal, 21... Threshold level control signal, 22...
Power supply selection signal, 23...Selection signal generator, 24-27...Selection signal, 28-31...Motor drive power supply. (r, pm)! (kg<m) Akira Honyo Jitsubishi line/)DC motor/)! ＋・Member showing notes, Mingzu No. 4 tel

Claims (1)

[Scope of Claims] Detection means for detecting the speed of the motor; Voltage supply means for generating mutually different voltages and capable of supplying the voltages to the motor; Depending on the speed detected by the detection means, a selection means for selectively selecting a voltage supply means having a suitable supply voltage from among the plurality of voltage supply means; and a selection means for controlling the supply voltage of the selected voltage supply means at the speed detected by the detection means. A control device for a motor, comprising: control means for variably setting the speed of the motor by controlling pulse width accordingly.