JPS6035981A - Controller of motor - Google Patents

Abstract

PURPOSE:To perform a PLL control by a simple configuration by utilizing a counter in a microcomputer. CONSTITUTION:The first counter 3A generates a reference frequency signal FS in accordance with a motor speed command from ten keys 1, and the second counter 3B generates a speed control signal FV of the prescribed width pulse in accordance with the motor speed command synchronously with the signal FG from an encoder 12. A phase comparator 5 outputs a phase comparison signal PC from the signal FG outputted from the output line 6 of the microcomputer 3 and the signal FG. The signal PC and FV are added by an adder 8, and converted by a comparator 9 into a pulse width modulation signal, and supplied to a driver 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a motor control device used in a copying machine, etc., and in particular, the invention relates to a control device for a motor used in a copying machine, etc. The present invention relates to a PLL speed control device suitable for continuously controlling a PLL speed control device.

[Prior art and its problems]

Conventionally, this type of device consists of hardware, and in order to continuously change the speed of the motor, a frequency divider is used to divide the reference frequency or the feedback frequency from the encoder of the drive motor. This is done by switching between the two, which has the disadvantage of increasing the size of the device.

[Purpose of the invention]

This invention was made in order to eliminate the above-mentioned drawbacks, and aims to reduce the size of the device by using a microcomputer, and to perform high-precision, wide-range PLL speed control using a microcomputer. shall be.

〔Example〕

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this figure, 1 is a numeric keypad that specifies the speed of the motor, 2 is an oscillator that drives the counter inside the microcomputer, and 3 is a microcomputer (hereinafter referred to as microcomputer) that controls the speed. 3
This first counter 3A counts the clock of the oscillator 2 and generates a reference frequency signal FS for phase comparison in accordance with the motor speed designation from the numeric keypad 1. The second counter 3B is synchronized with a feedback signal FG from an encoder, which will be described later, and generates a speed control signal FV of constant width pulses in accordance with motor speed designation. 4 is the output line, 5
A phase comparator generates a phase comparison signal PC from the reference frequency signal FS outputted from the output line 6 of the microcomputer 3 and the feedback signal FG, and outputs it to the output line 7. 8 is an addition circuit for the phase comparison signal PC and the speed control signal FV, 9 is a comparator that performs pulse width modulation (PWM), 10 is a driver that drives the motor, 11 is a motor, and 12 is the motor 1
A feedback signal FG is generated by an encoder that detects the rotation of 1, and is input to the microcomputer 3 and the phase comparator 5. 13-16
is an electronic volume, and 17 is a capacitor.

Incidentally, continuous magnification change of the motor 11 can be realized by continuously changing the scanning speed of the optical system when the drum speed is constant. When copying at the same size, the frequency of the feedback signal FG of the encoder 12 of the motor 11 for driving the optical system is IKHz (period T = 1 ms), and when the magnification is changed in steps of 1%, one period T changes every 0,01 m5. do. Each time the first counter 3A counts up, it repeats constant oscillation with a period T, so the oscillator 2 is
The reference frequency signal FS is generated by oscillating at a frequency of 0KH2) and setting a count value corresponding to the magnification in the first counter 3A.

Next, an outline of the operation of the embodiment shown in FIG. 1 will be explained.

The adder circuit 8 receives the speed control signal F output from the microcomputer 3.
V and the phase comparison signal PC from the phase comparator 5 are added, and the output is integrated by a filter consisting of an electronic volume 15 and a capacitor 17, and then P is determined by the threshold level determined by the electronic volume 16 of the comparator 9.
WM, the motor 11 is driven by the driver 10,
It is controlled to have a constant phase difference from the reference frequency signal FS according to the motor speed command from the numeric keypad 1.

The phase comparison and speed control method will be explained with reference to the flowchart of FIG. 2 and the waveform diagram of FIG. 3. In addition, the second
In the figure, (1), (2), etc. represent steps.

Input the speed setting (magnification) of the motor 11 using the numeric keypad 1 (1). If there is a change in the set value (2), the set value (data) is set in the first counter 3A (3) and a countdown is started.

Here, after the countdown of the first counter 3A is completed, an interrupt signal is generated, the set value is automatically reset, and the countdown is repeated. This generates the reference frequency signal FS. This reference frequency signal FS is then applied to the phase comparator 5.

Next, the speed control signal FV will be described. An FG interrupt is entered at the fall of the feedback signal FG from the encoder 12 of the motor 11, and after saving the register (11), the speed control signal FV is reset (12), and 1/2 FS of the reference frequency signal FS corresponding to the multiplication factor is generated. The timer value becomes 2nd counter 3
Set it to B to start (13), and after the register is restored (14), return. After the countdown of the second counter 3B is completed, an FV interrupt occurs, and after saving the register (21), the speed control signal FV is set (22), and the speed control signal FV shown in FIG. 3 is generated. , the register is restored (23).

The phase comparison signal PC has a phase difference θ~2 as shown in FIG.
When π, the phase comparison signal PC is sectored and reset repeatedly at the falling edge of the reference frequency signal FS and feedback signal FG, and if the phase of the feedback signal FG is delayed by 2π or more, the phase comparison signal PC remains set. After detecting that the feedback signal FG has fallen twice during one period of the reference frequency signal FS, the above-described operation with a phase difference of 0 to 2π is repeated. Conversely, if the phase of the feedback signal FG advances, that is, if the phase difference becomes less than O, the phase comparison signal After detecting that the falling edge has occurred twice, the above-mentioned operation with a phase difference of O to 2π is repeated.

Furthermore, when the phase difference is O to 2π, the phase comparator 5
"o o '" is output, and the feedback signal FG has a phase difference of 2π
When the delay is more than 0, a 2-bit lock signal is output, and when the phase difference of the feedback signal FG is less than 0, a 2-bit lock signal of '10' is output. is under control.

In the above embodiment, the reference clock for the first counter 3A is generated by the external oscillator 2, but it is also possible to use the oscillator in the microcomputer 3 internally as the timer reference clock, and the drive for the motor 11 can also be Although this is done using PWM, it may also be done at a DC level.

〔Effect of the invention〕

As described above in detail, the present invention can perform PLL speed control with a simple configuration by using a counter inside a microcomputer. Furthermore, by introducing a microcomputer, external peripheral equipment can be made smaller, which has the advantage that the entire device can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a flowchart 1 for explaining the operation of FIG. 1, and FIG. 3 is a waveform diagram of the main part. In the figure, 1 is a numeric keypad, 2 is an oscillator, 3 is a microcomputer, 3A
is the first counter, 4.6 is the output line, 5 is the phase comparator, 7
is the 1-11 force line, 8 is the adder circuit, 9 is the comparator, 1
0 is a driver, 11 is a motor, 12 is an encoder, 13
~16 is an electronic volume, and 17 is a capacitor. Figure 2

Claims (1)

[Claims] an input means for inputting a desired rotational speed of the motor; a means for generating a reference frequency signal by generating an internal interrupt signal by a first counter whose count value is set in accordance with the input from the input means; and a means for generating a reference frequency signal from the input means. a second counter that generates a speed control signal with a constant pulse width in response to the input of the motor; and an external interrupt signal based on a feedback signal from an encoder that detects the reference frequency signal and the rotation speed of the motor. A motor control device comprising: means for detecting a phase difference and outputting a phase comparison signal; and means for controlling the motor to the desired rotation speed using the phase comparison signal and the speed control signal. .