JPS6035982A - Controller of motor - Google Patents

Abstract

PURPOSE:To perform a PLL control by a simple configuration by utilizing a counter in a microcomputer. CONSTITUTION:The first counter 3A generates a reference frequency signal FS in accordance with a motor speed command from ten keys 1, and the second counter 3B generates a speed control signal FV of the prescribed width pulse in accordance with the motor speed command synchronously with the signal FG from an encoder 10. A microcomputer 3 outputs a phase comparison signal PC between the signals FS and FG and a speed control signal FV. The signals PC and FV are added by an adder 6, converted by a comparator 7 to a pulse width modulation signal, and supplied to a driver 8.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a motor control device used in a copying machine, etc., and in particular, the invention relates to a control device for a motor used in a copying machine, etc. The present invention relates to a PLL speed control device suitable for continuously controlling a PLL speed control device.

[Prior art and its problems]

Conventionally, this type of device consists of hardware, and in order to continuously change the speed of the motor, a frequency divider is used to divide the reference frequency or the feedback frequency from the encoder of the drive motor. This is done by switching between the two, which has the disadvantage of increasing the size of the device.

[Purpose of the invention]

This invention was made to eliminate the above-mentioned drawbacks, and aims to miniaturize the device by using a microcomputer, and to perform high-precision, wide-range PLL speed control using the microcomputer. .

〔Example〕

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this figure, 1 is a numeric keypad that specifies the speed of the motor, 2 is an oscillator that drives the counter inside the microcomputer, and 3 is a microcomputer (hereinafter referred to as microcomputer) that controls the speed. 3
This first counter 3A has clocks 1.B of the oscillator 2. The reference frequency signal FS for phase comparison is generated in accordance with the motor speed designation from the numeric keypad 1. The second counter 3B is synchronized with a feedback signal FG from an encoder, which will be described later, and generates a speed control signal FV of constant width pulses in accordance with motor speed designation. 4 and 5 are output lines; 6 is an addition circuit for the phase comparison signal PC and the speed control signal FV; 7 is a comparator that performs pulse width modulation (PWM); 8 is a driver that drives the motor; 9 is a motor;
An encoder detects the rotation of the motor 9, generates a feedback signal FG, and inputs it to the microcomputer 3. 11 to 14 are electronic volumes, and 15 is a capacitor.

Incidentally, the continuous magnification change of the motor 9 can be realized by continuously changing the scanning speed of the optical system when the drum speed is constant. When copying at the same size, the frequency of the feedback signal FG of the encoder 10 of the motor 9 for driving the optical system is set to 1.
KHz (period T=l m s), and when the magnification is changed in steps of 1%, the period T changes every 0.01 ms. Each time the first counter 3A counts up, it repeats constant oscillation with a period T, so the oscillator 2 is
The reference frequency signal FS is generated by oscillating at a frequency of 00KH2) and setting a count value corresponding to the magnification in the first counter 3A.

Next, an outline of the operation of the embodiment shown in FIG. 1 will be explained.

The adder circuit 6 receives the speed control signal F output from the microcomputer 3.
V and the phase comparison signal PC are added, and the output is integrated by a filter consisting of an electronic volume 13 and a capacitor 15, and then PWMed by the threshold level determined by the electronic volume 14 of the comparator 7, and the motor 9 is driven by the driver 8. However, it is controlled to have a constant phase difference from the reference frequency signal FS according to the motor speed command from the numeric keypad 1.

The phase comparison and speed control method will be explained in accordance with flowchart 1 in FIG. 2 and the waveform diagram in FIG. 3. In FIG. 2, (1), (2), . . . represent steps.

Input the speed setting (magnification) of the motor 9 using the numeric keypad 1 (1). If there is a change in the set value (2), the set value (data) is set in the first counter 3A (3) and a countdown is started. Here, after the countdown of the first counter 3A is completed, an interrupt signal is generated, the set value is automatically reset, and the countdown is repeated.

This generates the reference frequency signal FS.

Next, the speed control signal FV will be described. An FG interrupt is entered at the fall of the feedback signal FG from the encoder 10 of the motor 9, and after saving the register (31), the speed control signal F
To reset V32), set the timer value that is 1/2 FS of the reference frequency signal FS corresponding to the magnification to the second counter 3B.
Set it to start (33), and set i2 counter 3.
After the countdown of B is completed, an FV interrupt occurs, and after saving the register (51), the speed control signal FV is set (52), and the speed control signal FV shown in FIG.
After generating, the register is restored (53).

The phase comparison signal PC has a phase difference of O~2 as shown in FIG.
When π, the phase comparison signal PC is repeatedly set and reset at the falling edge of the reference frequency signal FS and feedback signal FG, and if the phase of the feedback signal FG is delayed by 2π or more, the phase comparison signal PC remains set. After detecting that the feedback signal FG has fallen twice during one period of the reference frequency signal FS, the above-described operation with a phase difference of 0 to 2π is repeated. Conversely, when the phase of the feedback signal FG advances, that is, when the phase difference becomes less than O, the phase comparison signal PC maintains the reset state and the reference frequency signal FS is After detecting that the falling edge has occurred twice, the operation for the phase difference θ to 2π described above is repeated.

This will be further explained based on FIG.

The phase comparison signal PC has a phase difference of 0 to 2 as shown in FIG.
In the state of π, the FS is always enabled and the FG input counter l is in the state, so the FS interrupt signal causes (11), (
12), (13), and (19) to P of microcomputer 3.
Set the CC boat20), clear the counter that counts the number of FG interrupts16), then raise the counter that counts the number of FS interrupts17), and enable interrupts at the same time as register restoration. Deeds (
18), Return. Through this series of steps, FG
Allow G-inclusive signals.

Next, similarly to -L statement, FG permission, FS input counter = 1
Since the state is 1n;, by the FGG-included signal (34)
, through (35) and (41), reset the PC board 42), clear the counter that counts the number of FS interrupts 38), count up the counter that counts the number of FG interrupts 38), register At the same time as returning, interrupts are enabled (40) and the process returns.

This series of steps enables the FS interrupt signal.

That is, the FGG inclusion signal and the FS interrupt signal are generated alternately.

If the phase difference is 2π or more as shown in Figure 3, FS is initially permitted;
Since the FG input counter is in the state of 0, the same as above (
11), (12), (13), and (19) to the PC.
Set the C boat (20), clear the counter that counts the number of FG interrupts (16), and count up the counter that counts the number of FS interrupts (17).
), interrupts are enabled at the same time as the register is restored (18),
After returning, the FS interrupt signal is input again, so F
When the G input input counter is "0" (13), set the PC port (14) and set the FGG stop flag (15).
), clears the counter that counts the number of FG interrupts (16), increments the counter that counts the number of FS interrupts (17), enables interrupts at the same time as the register is restored (18), and returns. FG is prohibited in this state.

Due to FS input counter #O status (34), (43)
.

(38), (H), and (40), PWM is driven to advance the phase of the motor 9 in the driver 8. When the phase of the feedback signal FG advances and the FGG-included signal is input, and the number of FG interrupts is "0," step (3
4) Reset the PC boat through the judgment in (43) 44) Reset the flag to enable FS and FG interrupts 1-L (45) Steps (39) and (
40) and return. After this, the phase difference mentioned above is 0.
The state 7i1'H of ~2π is repeated.

Conversely, when the phase of the feedback signal FG is advanced, it operates in the same way as when the phase is delayed, FS, and FG, but the relationship between them is switched, and (3El) and (3?).

PWM is driven by the driver 8 to delay the keyer 9 through (21), (22), and (23), and the phase difference is controlled to be O~2π.

In the above embodiment, the external oscillator 2 generates ff1l.
The reference clock for the counter 3A is created, but it is also possible to use the oscillator in the microcomputer 3 as the timer reference clock internally.Moreover, the motor 9 is driven by PWM, but this is done at a DC level. It's okay.

〔Effect of the invention〕

As described in detail, the present invention can perform PLL speed control with a simple configuration by utilizing a counter inside a microcomputer. Furthermore, by introducing a microcomputer, external peripheral equipment can be made smaller, which has the advantage that the entire device can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of FIG. 1, and FIG. 3 is a waveform diagram of the same main part. In the figure, 1 is a numeric keypad, 2 is an oscillator, 3 is a microcomputer, 3A
1 is a first counter, 4 and 5 are output lines, 6 is an adder circuit, 7 is a comparator, 8 is a driver, 9 is a motor, 10 is an encoder, 11 to 14 are electronic volumes, and 15 is a capacitor.

Claims (1)

[Claims] an input means for inputting a desired rotational speed of the motor; a means for generating an internal interrupt signal by a first counter whose count value is set according to the input from the input means to create a reference frequency signal; a second counter that generates a speed control signal with a constant pulse width in response to the input of the motor; and an external interrupt signal that is a feedback signal from an encoder that detects the reference frequency signal and the rotational speed of the motor to detect the phase difference. Control of a motor, comprising: a microcomputer equipped with means for outputting a phase comparison signal; and means for controlling the motor to the desired rotation speed using the phase comparison signal and the speed control signal. Device.