JPS6035978A - Controller of motor - Google Patents

Abstract

PURPOSE:To perform accurate and wide PLL control by controlling a motor by a pulse width modulation signal calculated from a phase error signal between a feedback signal from an encoder and a reference frequency signal. CONSTITUTION:The first counter generates a reference frequency signal FS in accordance with a motor speed command from ten keys 1, and the second counter 2B forms a pulse width modulation (PWM) signal from a phase error signal between a reference frequency signal FS and a feedback signal FG from an encoder 19. A microcomputer 2 outputs a forward ON signal 3, a reverse ON signal 4 and a PWM signal 5. Drivers 11, 13, 15, 17 are controlled ON or OFF by these signals, and supply a drive voltage to a motor 18.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a motor control device, and is suitable for use in, for example, a copying machine that continuously controls the speed of a scanning optical system to continuously change magnification. This invention relates to a motor control device.

[Prior art and its problems]

Conventionally, in this type of control device, particularly in PLL control, the characteristics of the PLL control have been influenced by the characteristics of the low-pass filter.

Further, in a control device that synchronizes with various target speeds, it is necessary to switch the low-pass filter.

Furthermore, when controlling the motor with PWM (pulse width modulation), an adder that adds the PLL signal and the speed control loop signal;
In addition, an integrator was required to integrate the added output.

[Purpose of the invention]

The present invention was made in order to eliminate the drawbacks of the above-mentioned conventional example, and provides a motor control device that is capable of miniaturizing the device and performing high-precision, wide-range PLL speed control using a microcomputer. The purpose is to

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention.

In this figure, 1 is a numeric keypad for specifying the speed of the motor, and 2 is a microcomputer (hereinafter referred to as microcomputer) for speed control, which has an interrupt function and is equipped with a first counter 2A and a second counter 2B. 1 counter 2A counts an internal clock and generates a reference frequency signal FS (which also indicates frequency; hereinafter the same) for phase comparison according to the motor speed designation from numeric keypad 1. The second counter 2B uses an internal clock to count to generate a PWM signal from the phase error signal. 3 is forward on signal, 4
is the reverse ON signal, 5 is the PWM signal that drives the motor, and 6 is the reverse ON signal.
, 8 is an AND circuit, 7.9 is a NOT circuit, 10, 12 .
14.16 is the PW, 19 is an encoder for detecting the rotation of the motor 18, and FG is a feedback signal from the encoder 19.

Next, an overview of the operation of the embodiment shown in FIG. 1 will be explained. The AND circuit 6 is heard by the forward ON signal 3, passes the PWM signal 5 output from the microcomputer 2, amplifies it with the amplifier 10, and drives the driver 11. Also, forward on signal 3
is inverted by the knot circuit 7, amplified by the amplifier 12, and drives the driver 13. As a result, the PWM signal 5 is applied to the motor 18, and the motor 18 is controlled so that the phase difference between the reference frequency signal FS according to the motor speed command and the feedback signal FG from the encoder 19 is constant.

Note that at this time (while moving forward), the reverse movement ON signal 4 is output from the AND circuit 8. Do not open the knot circuit 9. Further, while moving backward, the operation is similar to that while moving forward.

Next, the phase comparison and the control method of the PWM signal 5 will be explained in a second manner.
The explanation will be made according to the flowcharts shown in FIGS. (a) and (b) and the waveform diagram shown in FIG. Note that (1), (2), . . . in FIGS. 2(a) and 2(b) indicate each step.

Here, the principle of creating the PWM signal 5 will be explained with reference to FIG.

The reference frequency signal FS is a signal with a constant frequency determined by input from the numeric keypad 1. Since the feedback signal FG is a signal from the encoder 19 of the motor 18, it is generated only after the motor 18 rotates. If the speed of the motor 18 matches the reference frequency signal FS (it is considered a match when the phase difference is between 0 and 2π), the reference frequency signal FS and the feedback signal F
The phase difference ΔP with G is between 0 and 2π. This phase difference ΔP is detected by the first counter 2A counting the internal clock of the microcomputer 2.

And the on time Van in the PWM signal 5 is Von=ΔP
XK+C gets caught. Here, K is a constant, and C is a constant depending on the magnification.

Then, the pulse width (off time) of the PWM signal 5 is PWM=-F S -Van, and this calculation is performed in the microcomputer 2 and output.
The motor 18 is controlled to be synchronized with the reference frequency signal FS.

Next, phase comparison will be explained with reference to FIG. 2(a). Input the speed setting (magnification) of the motor 18 using the numeric keypad 1 (1
). If there is a change in the set value (2), set the set value in the i l counter 2A (3) and start a countdown. After the first counter 2A finishes counting, an interrupt signal is generated and the set value is automatically reset.
Counting is repeated to generate a reference frequency signal FS.

Furthermore, a bias value suitable for the speed of the motor 18 is set (4).

The phase error signal PC has a phase difference of O~2 as shown in FIG.
When π, the phase error signal PC is set at the falling edge of the reference frequency signal FS and feedback signal FG.

If the phase of the feedback signal FG is delayed due to repeated resets, the phase error signal PC maintains the set state, and the falling edge of the feedback signal FG is 2 times during one period of the reference frequency signal FS.
After detecting that the phase difference has come (for example, at time t), the above-described operation with a phase difference of O to 2π is repeated. Also, conversely, the feedback signal F
When the phase of G advances, the phase error signal PC maintains the reset state, and after detecting that the reference frequency signal FS falls twice during one cycle of the feedback signal FG, the phase difference O~ It repeats 2π operations.

This will be further explained based on FIG. 2(a).

As shown in Fig. 3, when the phase difference between the reference frequency signal FS and the phase error signal PC is 0 to 2π, the phase error signal PC is output by the FS interrupt signal as shown in Fig. 2(a). After determining whether the interrupt is allowed or not, (11), (+2), (
+3), (18), (19), FGG force counter is 1'
If it is not ', that is, at this point it is more than 2, it will rise at the rising edge set of (20); refrag the refrag, and clear the FG input/input counter that counts the number of interrupts of the feedback signal FG15). Next, the FSS input counter that counts the number of FS interrupts increases to 1.
6), After register return (17), After enabling interrupts,
Return.

Next, as shown in FIG. 2(b), the FGG-included signal causes the feedback signal F to change from the falling edge of the quasi-frequency signal FS to
The time until the falling edge of G is read using the first counter 2A for creating the reference frequency signal FS (31).

Next, the second counter 2B for PWM output is started and reset to output the off time of the motor 18 (32). To judge whether the motor has started up to the target speed, if there are two FG interrupts during the FS period, it is determined that the motor has started up.) (33), if it has already started up,
Determine whether FG is prohibited and the FSS input counter is “O'' or L'' (34), (35), (42), (43)
, In the motor on time calculation [2], the on time ton of the motor 18 is calculated (44). After that, clear the FSS input counter that counts the number of FS interrupts.
), then the FG input input counter counts up the number of FGG inputs 39), the motor off time to
ff (17 FS-ton) and set the count value of the motor off time t off in the second counter 2B L (4
0), and after the register is restored (41), returns.

Furthermore, when counting up to the count value of the second counter 2B, a PWM timer interrupt occurs, and after saving the register (51
), the second counter 2B is stopped and the output is set so that the motor is turned off (52), and this state continues until an FG interrupt occurs.

When the phase difference is in the range of O to 2π, such a process is repeated and the phase difference is controlled to be constant. Thereafter, the register is restored (53) and the process returns.

Next, in the range of the phase difference of 2π or more in Fig. 3, Fig. 2 (a)
As shown in FIG.
3), (18), (19), Clear the FG input/input counter 15), Count up the FSS input counter that counts the number of FS interrupts 16), After returning the register,
Enable interrupts (17) and return.

Since the phase is delayed by 2π or more, the FS interrupt shown in FIG. 2(a) is generated again before the FG interrupt, and since the FGG force counter is "0°", FS is prohibited (12).

It is determined whether the FGG force counter is O'' (13),
Set the FGG stop flag (14), clear the FGG force counter (15), count up the FS input counter (16), restore the register (17), and return.

Next, an FG interrupt occurs, and as shown in Fig. 2(b), the count value of the current FG interrupt from the previous second FS interrupt is read (31), and the second counter 2B, which is a PWM timer, is
is started and reset to output the off time of the motor 18 (32). At this time, the phase difference is from the first fall of the reference frequency signal FS to the current feedback signal FG.
until the fall of . After that, it is necessary to judge whether the motor has risen to the target speed (33), and it is judged whether FG is prohibited (34).Since the FGG stop flag was set first, what is the FSS input counter 0°? Pass the judgment (4
6), go to the motor on time calculation [3] (45), and calculate the on time to increase the speed of the motor 18.
n is calculated to become longer, the FSS input counter is cleared38), the FG input/input counter is counted up38), the motor off time toff is determined, and the count value is set in the second counter 2B4o), and after the register is restored. (41), interrupts are enabled and the process returns.

As the speed of the motor 18 becomes faster (the phase of the FG advances), an FG interrupt is input, and the number of FS interrupts becomes "0".
At this time, the FS goes through the judgment of whether FG@stops (34) and the judgment of whether the FSS input counter is 0゛° (46).
, reset the flag to enable FG interrupts 1=L(
47), motor on time calculation [2] (48), and motor on time t to return the phase difference to the range of O to 2π.
on is calculated, and then (39) and (40
), and returns through steps (41).

j Also, conversely, when the phase of FG advances (phase difference is less than O)
reads the count value from the previous FS interrupt to the current FG interrupt using the FG interrupt signal as shown in FIG. 2(b) (31), and starts the second counter 2B, which is a PWM timer. It is reset to output the off time of the motor 18 (32).

After that, it is determined whether the motor has risen to the target speed (33), it is determined whether FG is prohibited (34), and it is determined whether the FSS input counter is "°0°" or "1'' (35).

(42), (43), motor on time (2)
Go to (44), the motor on time ton is calculated, and F
Clear the S input counter 38) and count up the FG input input counter that counts the number of FGG inputs 39
), (40), and (41) to return.

Since the phase has advanced (the phase difference is less than O), the FG interrupt shown in Figure 2 (b) is entered again before the FS interrupt, and the count value at the current FG interrupt is read from the previous FS interrupt ( 31
), FG input counter is “0°”, so FG is not prohibited (34), and FSS input counter is “0°”.
“ is determined (35), FS prohibition flag, FG
Permission flutter 36), motor on time calculation [
F
Clear the G input power output 38), increase the FG input input counter count 39), motor off time to of
fff is detected, and the second counter 2B displays that one fff
After setting j (40) and restoring the register (41), return.

As the speed of the motor 18 becomes slower (the phase of the FG becomes slower), an FS interrupt is input, and the number of FGG interrupts becomes "0°°".
In this case, the flag is reset to enable FG and FS interrupts after passing through the judgment (12) as shown in FIG. 22), after register return (17)
, return.

In addition, motor on time calculation (4) shown in Fig. 2(b) (
49) is a routine that calculates the output from when the motor stops until it reaches the target speed, and sets a rising flag when FG interrupt occurs twice during FS.

〔Effect of the invention〕

As explained in detail above, the present invention creates a reference frequency signal with the first counter in the microcomputer, creates a phase error signal with the reference frequency signal and a feedback signal from the encoder that also detects the rotational speed of the motor, and further, Since the motor is controlled by creating a pulse width modulation signal by calculation from the phase error signal, the motor can be easily controlled to a constant speed according to the set value, regardless of the characteristics of the PLL low-pass filter. can do. Moreover, by introducing a microcomputer, there is an advantage that the number of external peripheral circuits can be extremely reduced and the overall size can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
), (b) are flowcharts for explaining the operation in Figure 1, and Figure 3.
The figure is also a waveform diagram of the main part. In the figure, 1 is a numeric keypad, 2 is a microcomputer, 2A is a first counter, 2B is a second counter, 3 is a forward ON signal, 4 is a reverse ON signal, 5 is a PWM signal, 6°8 is an AND circuit, 7.
9 is the knot circuit -10゜12.14.16 is the amplifier, 1
1, 13, 15° 17 is a driver, 18 is a motor, 19
is an encoder.

Claims (1)

[Claims] an input means for inputting a desired rotational speed of the motor; a means for generating a reference frequency signal by generating an internal interrupt signal using a first counter whose count value is set according to the input from the input means; and said reference frequency signal. and means for detecting a phase difference using an external interrupt signal based on a feedback signal from an encoder that detects the rotational speed of the motor and creating a phase error signal, and calculating a pulse width modulation signal from the phase error signal and the reference frequency signal. and means for outputting the pulse width modulation signal, and further comprising means for controlling the motor to the desired rotation speed using the pulse width modulation signal. Characteristic motor control device.