JPS62281783A - Speed control unit for motor - Google Patents

Abstract

PURPOSE:To prevent the overshoot produced at the beginning of a motor start-up, by energizing a phase comparison means when the cycle of a rotation feedback signal after the start-up of motor reaches the predetermined value. CONSTITUTION:A phase comparator 5 forms a phase comparison signal PC based on a reference frequency signal FS and a feedback signal FG. An addition circuit 8 adds a speed control signal FV and the phase comparison signal PC and gives them to a driver 10 modulated in pulse width by a comparator 9. When a monitor 11 is started, the phase comparison signal PC is set to a high level and the rotating speed is radically raised from zero. The high level period tg of the feedback signal FG is monitored by an event timer ETM. With the following expression the phase comparison signal PC is turned back to a low level: tg<=ts+tO where ts: time representing 1/2 of one cycle of the reference frequency signal FS; tO: preset constant.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed control device for an electric motor equipped with a phase-locked loop.

More specifically, the present invention relates to a speed control device that improves the rotation start-up characteristics when starting an electric motor.

[Prior Art] For example, a control device for driving a moving optical system of a copying machine is known as a device that controls the rotational speed of an electric motor using a phase-locked loop.

FIG. 5 shows an example of a conventionally known speed control device with a phase-locked loop. This figure shows a circuit for controlling eight dynamic optical system motors of a copying machine, where 1 is a ten-key key for specifying the speed of the motor, and 2 is an oscillator that drives a counter inside a microcomputer.

3 is a micro combinator which performs speed control;
It has a counter 3A and a second counter 3B. This first counter 3A counts the clock of the oscillator 2 and generates a reference frequency signal FS for phase comparison according to the motor speed specified from the numeric keypad 1. Further, the second counter 3B is synchronized with a feedback signal FG from an encoder, which will be described later, and generates a speed control signal FV having a constant width in accordance with motor speed designation.

4 is an output line. 5 is a phase comparator, which outputs a reference frequency signal F to the output line 6 of the microcomputer 3.
A phase comparison signal pc is formed based on S and the feedback signal FG, and is output to the output line 7. 8 is an adder circuit that adds the phase comparison signal pc and the speed control signal FV, 9 is a comparator that outputs a pulse width modulation (pwM) signal, 10 is a driver that drives an optical system drive motor, and 11 is an optical system drive It is a motor for An encoder 12 detects the rotation of the motor 11, generates a feedback signal FG, and sends it to the microcomputer 3 and the phase comparator 5. 13-16
is an electronic volume, and 17 is a capacitor. Also, 1
8 is the FV gain control signal, 19 is the PC gain control signal, 20
is a filter control signal, and 21 is a threshold level control signal.

Next, the general operation shown in FIG. 5 will be explained.

Adder circuit 8 adds speed control signal FV output from microcomputer 3 and phase comparison signal pc output from phase comparator 5. After the output is integrated by a filter consisting of an electronic volume 15 and a capacitor 17, it is PW)J modulated by a threshold value determined by an electronic volume 16 of a comparator 9, and a motor 11 is driven by a driver 10. In this way, the reference frequency signal FS according to the motor speed command from the numeric keypad 1 and the feedback signal FG are controlled to have a constant phase difference.

Further, the microcomputer 3 sets predetermined values of the electronic volumes 13 to 16 according to the copying magnification, thereby generating the phase comparison signal PC and the speed control signal FV.
The addition gain ratio, filter characteristics, and threshold level are controlled. Further, the threshold value is also controlled by the lock signal of the phase comparator 5.

The speed control method in the apparatus shown in FIG. 5 will be explained with reference to the flowchart shown in FIG. 6 and the waveform diagram shown in FIG. 7. Note that SL, S2, . . . shown in FIG. 6 represent control steps.

First, the speed setting (magnification) of the motor 11 is input using the numeric keypad 1 (step 51). If there is a change in the set value (step S2), the set value (data) is set in the first counter 3A (step S3), and a countdown is started. After the first counter 3A finishes counting down, an interrupt signal is generated, the set value is automatically reset, and the countdown is repeated. This generates the reference frequency signal FS. This reference frequency signal FS is then applied to the phase comparator 5. moreover,
The electronic volumes 13 to 16 are set to values corresponding to the magnification (step S4).

Next, the speed control signal FV will be described. encoder 1
FG interrupt is entered at the fall of the feedback signal FG sent from 2, and after saving the register (step 511), the speed control signal FV is reset (step 512), and the reference frequency signal FS corresponding to the magnification becomes 172FS. Set the timer value to 2nd counter 3 [1 and start it (
Step 513). Then, if the phase difference is O~2π (step 514), after the register is restored (step 518
), return. Further, if the phase difference is not O~2π (step 514) but 2π or more (step 51
5), step 516) to lower the threshold. If not, increase the threshold (step 517);
After the register is restored (step 518), the process returns. After the countdown of the second counter 3B is completed, an FV interrupt occurs, and after saving the register (step S21
), the speed control signal FV is generated by setting the speed control signal FV (step 522). Thereafter, the register is restored (step 523) and the process returns.

As shown in FIG. 7, the phase comparison signal pc has a phase difference of 0 to
When 2π, the phase comparison signal pc is repeatedly set and reset at the falling edge of the reference frequency signal FS and feedback signal FG. In addition, when the phase of the feedback signal FG is delayed by 2π or more, the phase comparison signal pc maintains the set state, and the fall of the feedback signal FG is delayed by 2π during one period of the reference frequency signal FS.
After detecting that the phase difference has come, the above-described operation with a phase difference of O to 2π is repeated. Conversely, if the phase of the feedback signal FG advances,
In other words, when the phase difference becomes O or less, the phase comparison signal pc maintains the reset state, and after detecting that the reference frequency signal FS falls twice during one cycle of the feedback signal FG, The operation with a phase difference of 0 to 2π is repeated.

Further, the speed control signal FV is reset in response to the fall of the encoder pulse (feedback signal FG) of the motor 11, and is set after 172 cycles of the reference frequency signal FS.

Then, the phase comparator 5 outputs 0 when the phase difference is 0 to 2π.
When the feedback signal FG is delayed by a phase difference of 2rt or more, a 2-bit lock signal of ``01'' is output, and when the phase difference of the feedback signal FG is 0 or less, a 2-bit lock signal of 10'' is output.

Then read this with microcomputer 3 and F
Controls the G interrupt routine.

[Problems to be Solved by the Invention] However, in the above-mentioned phase lock control method, in order to increase the synchronization pull-in force, if the phase of the feedback signal FG is delayed by 2π or more with respect to the reference frequency signal FS, the phase comparison signal is After increasing the motor speed by keeping the PC in the set state (high level) and detecting that the falling edge of the feedback signal FG has occurred twice during one period of the reference frequency signal FS, the normal PWM speed is increased. Control (control of phase difference O~2π) was performed (see FIG. 7).

In other words, the falling edge of the feedback signal FG occurs twice during one period of the reference frequency signal FS.
As shown in the figure, the frequency of the feedback signal FG becomes higher than the frequency of the reference frequency signal FS, which means that the motor rotation speed exceeds the target value.

Therefore, when such a control method is applied to, for example, the moving optical system of a copying machine, the rotational speed exceeds the target value when the motor is started (starting), causing a so-called overshoot, and the leading edge of the copied image is There were times when "shake" occurred.

SUMMARY OF THE INVENTION Therefore, in view of the above-mentioned points, an object of the present invention is to provide a speed control device configured to prevent overshoot that occurs when starting a motor and to quickly obtain a desired rotational speed.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a phase comparison means for detecting a phase difference between a reference signal and a rotational feedback signal, and the speed of the electric motor is determined based on the phase difference. In a device for controlling a motor, a timer means sends out a determination output when the cycle of the rotational feedback signal reaches a predetermined value after starting the motor, and control activates the phase comparison means in response to the determination output. and means.

[Operation] Before the frequency of the rotational feedback signal corresponding to the rotational speed of the motor reaches the frequency of the reference signal (or when it reaches the same frequency), the phase comparison means sends out a signal for speed control.

[Example] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is an overall configuration diagram of a speed control device according to the present invention. Here, in a device that includes a phase comparison means A that detects a phase difference between a reference signal and a rotational feedback signal, and controls the speed of an electric motor based on the phase difference, the period of the rotational feedback signal after starting the electric motor is set to a predetermined period. It comprises timer means B which sends out a judgment output when the value has been reached, and control means C which energizes the phase comparison means in response to the judgment output.

FIG. 2 is a block diagram showing an embodiment of a speed control device to which the present invention is applied. The difference between this embodiment and the conventional example shown in FIG. 5 is that a microcomputer CPU including an event timer ETM is newly provided and a control procedure according to the flowchart shown in FIG. 3 is executed. Therefore, the other components shown in this figure are the same as those shown in FIG. 5, and are given the same reference numerals as in FIG. 5.

FIG. 4 is a waveform diagram showing the operation of the embodiment shown in FIG. 2, and shows the relationship between each signal and the rotational speed of the electric motor.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 to 4.

First, when the motor 11 is started (step S1), the phase comparison signal PS is set to a high level and its rotational speed is rapidly increased from zero (step S2).

Then, the high level period tg of the feedback signal FG gradually becomes shorter, so this period t4 is set as the event timer ET.
M is constantly monitored, and when it reaches 7g≦ts+to, the phase comparison signal PC is returned to low level (step 53, S4
). Here, ts is 17 of one period of the reference frequency signal FS.
The time representing 2 is a predetermined constant (10 may be 0).

Therefore, the speed increase of the motor 11 is stopped before the frequency of the feedback signal FG reaches the frequency of the reference frequency signal FS, and overshoot can be suppressed. This means that
This becomes clear by comparing FIG. 4 and FIG. 8.

Once the motor rotation speed does not reach the target value, the sixth
Speed control similar to that described in connection with the figure is performed (step S5).

[Effects of the Invention] As described above, according to the present invention, since the structure is such that the increase and deceleration is performed while monitoring the cycle of the feedback signal generated when the motor is started, unnecessary overshoot can be removed and the speed can be increased quickly. The target rotation speed can be achieved.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of a speed control device according to the present invention, Fig. 2 is a block diagram showing an embodiment of a speed control device to which the present invention is applied, and Fig. 3 is an embodiment shown in Fig. 2. 4 is a waveform diagram showing the operation of FIG. 2, FIG. 5 is a block diagram showing an example of a conventionally known motor control circuit, and FIG. 6 is the control in FIG. 5. A flowchart showing the procedure, and FIGS. 7 and 8 are waveform diagrams showing the operation of FIG. 5, respectively. CPU...Microprocessor, ETM...Event timer, FV...Speed control signal, FS...Reference frequency signal, FG...Feedback signal, 5...Phase comparator, 8...Addition Circuit, 9... Comparator, 11... Motor, 12... Encoder, 22... Integrating circuit. Figure 1

Claims (1)

[Scope of Claims] A device comprising phase comparison means for detecting a phase difference between a reference signal and a rotational feedback signal, and controlling the speed of an electric motor based on the phase difference, further comprising: a period of the rotational feedback signal after starting the electric motor; 1. A speed control device for an electric motor, comprising: timer means for transmitting a determination output when the determination output reaches a predetermined value; and control means for energizing the phase comparison means in response to the determination output.