JP3045353B2 - Voltage control device for vehicle generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage control device for a vehicle generator, and more particularly to a device for gradually changing an exciting current corresponding to a change in an electric load.

[0002]

2. Description of the Related Art In a conventional vehicle generator, the amount of generated current is insufficient immediately after a load input switch is turned on to supply power to an electric load. When the voltage drop is detected, the exciting current of the generator is increased until the terminal voltage reaches a predetermined reference level, thereby increasing the output current of the generator and supplying power to the electric load. However, according to the above-described power generation control method, there is a problem that the engine speed drops rapidly due to a sudden increase in the engine load immediately after the electric load is applied. That is, when an electric load is applied at a predetermined accelerator opening, the terminal voltage of the battery is reduced due to power supply thereto, the exciting current is rapidly increased, the engine load is rapidly increased, the engine speed is rapidly reduced, and the engine speed is further reduced. Due to inertia, the engine speed drops beyond the equilibrium point (usually called undershoot).

[0003] To solve such a problem, Japanese Patent Laid-Open Publication No.
2-64299 indicates that when an electric load is newly input,
Irrespective of the amount of decrease in the battery terminal voltage, the duty ratio of the exciting current is increased at a constant rate, thereby avoiding a sudden drop in the engine speed due to a sudden increase in the exciting current.

[0004]

However, even in the gradual excitation technique disclosed in the above publication in which the duty ratio of the generator is increased at a constant rate, if the electric load is an intermittent electric load (hereinafter referred to as an intermittent load) that is interrupted at a constant cycle, When the engine torque is small, such as when idling, the engine speed is hunted according to the intermittent operation of the intermittent load, but the occupant feels uncomfortable, although it is smaller than when the gradual excitation is not performed. There was a problem.

If the idle speed is set high in order to reduce hunting, there is a disadvantage in terms of fuel efficiency. The present invention has been made in view of the above problems, and an object of the present invention is to provide a voltage control device for a vehicle generator that can reduce hunting of an engine during intermittent load driving.

[0006]

According to the present invention, there is provided a voltage control apparatus for a vehicle generator, wherein the exciting current of the vehicle generator for supplying electric power to the electric load and the battery in parallel is set to a value corresponding to the required level of the electric load and the battery. And an excitation current corresponding to the magnitude of the electric load after the detection from the excitation current value corresponding to the magnitude of the electric load immediately before the application of the electric load. A gradual excitation control unit that gradually increases the excitation current at a predetermined rate of change of the excitation current immediately after the electric load is applied to the electric load, wherein the gradual excitation control unit includes at least an intermittent operation. An intermittent load input detecting means for detecting the input of an electric load, and an intermittent operation for setting the exciting current increasing rate after the intermittent load is applied to be smaller than the exciting current increasing rate after the non-intermittent operating electric load is applied. It is characterized in that it comprises a time load input control means.

[0007]

The basic control unit controls the exciting current of the vehicle generator which supplies power to the electric load and the battery, and makes the output current of the generator correspond to the fluctuation of the electric load. The gradual excitation control unit gradually increases the excitation current value according to the value of the electric load immediately before the application of the electric load from the excitation current value according to the value of the electric load immediately after the application of the electric load.

Further, the intermittent load input detecting means detects the input of the intermittent operation electric load, and the intermittent load input control means determines the exciting current increase rate after the intermittent load input based on the exciting current increase rate after the non-intermittent operation electric load is applied. Also set smaller.

[0009]

As described above, in the voltage control apparatus for a vehicle generator according to the present invention, the gradual excitation control unit detects the application of the intermittent operation electric load and determines the rate of increase of the excitation current after the application of the intermittent load. Equipped with an intermittent load input control means that sets the excitation current increase rate after the non-intermittent operation electric load is turned on, so that the excitation current gradually increases at the first excitation current increase rate after the non-intermittent operation electric load is turned on. In this way, it is possible to suppress the engine speed from dropping, and to gradually increase the exciting current at a second exciting current increasing rate smaller than the first exciting current increasing rate after the intermittent operation electric load is applied.

That is, according to the present invention, the rate of increase in the exciting current is further reduced after the intermittent load is applied, than after the non-intermittent load is applied, in which the exciting current is gradually increased to suppress the decrease in the engine speed (undershoot). However, an excellent effect that hunting of the engine speed after the intermittent load is input can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a voltage control device for a vehicle generator according to the present invention will be described below with reference to FIG. The generator 2 is a three-phase AC generator with a built-in three-phase full-wave rectifier driven by a vehicle engine (not shown). The lower output terminal is grounded, and the higher output terminal is connected to the + terminal of the battery 3. It is connected. The high output terminal can supply power to the intermittent load 5 through the intermittent load input switch 6 and to the non-intermittent load 51 through the switch 61. Here, the intermittent load 5 is an electric load such as a hazard lamp or a turn signal that blinks in a cycle of several seconds or less, and the non-intermittent loads 51 and 52 are electric loads that operate continuously.

A connection point between the intermittent load 5 and the switch 6 is connected through a diode 7 to an input terminal of a judgment circuit 17 in the voltage control device 1. The generator 2 is provided with a voltage controller 1. The voltage controller 1 has an input terminal for detecting a terminal voltage of the battery 3 and an output terminal connected to one end of the excitation winding 20 of the generator 2. The other end of the excitation winding 20 is connected to a high output end of the generator 2.

The voltage control device 1 has a built-in power supply circuit 19 supplied with power from the battery 3 through the key switch 4. The power supply circuit 19 supplies a predetermined power supply voltage to each unit through a power supply line (not shown). The configuration of the voltage control device 1 will be described below. Voltage-dividing resistors R1, R connected in series with each other between the input terminal of the voltage controller 1 and the ground line.
2 is compared with the reference voltage Vr by the comparator 10, and the output of the comparator 10 is output to the AND circuit 12.
Is input to The AND circuit 12 supplies a logical product output of the output of the comparator 10 and the output of the gradual excitation control unit described later to the base of the power transistor 11 having a common emitter, and the collector of the power transistor 11 is supplied through the output terminal of the voltage controller 1. The exciting current supplied to the exciting winding 20 is interrupted. Here, when the output from the gradual excitation control unit to the AND circuit 12 is at a high level (1), the power transistor 11 is normally opened and closed by the comparator 10 and the divided voltage V
The duty ratio of the power transistor 11 so that s becomes equal to the reference voltage Vr (hereinafter, also simply referred to as duty).
Is determined.

Here, the comparator 10 constitutes a basic control unit according to the present invention, and the voltage control device 1 has a gradual excitation control unit described below. The gradual excitation control unit includes a duty storage circuit 13, a duty addition latch circuit 14, a pulse width generation circuit 15, a latch cycle switching circuit (intermittent load input control means) 16, a determination circuit (intermittent load input detection means) 1.
7. A reference clock circuit 18.

The reference clock circuit 18 includes a duty storage circuit 13, a pulse width generation circuit 15, and a latch cycle switching circuit 1.
6, a clock signal having a predetermined period is input. The duty storage circuit 13 has a function of inputting and storing the duty of the power transistor 11 by detecting the output of the AND circuit 12. The determination circuit 17 is a circuit that determines by comparing the output of the comparator 10 with the output of the pulse width generation circuit 15.

The latch cycle switching circuit 16 includes a judgment circuit 17
Is a circuit for controlling the timing of changing the duty of the clock signal for turning on and off the power transistor 11 based on the output from the CPU. Duty addition latch circuit 14
Latches the duty stored in the duty storage circuit 13 at a predetermined timing, and adds a predetermined amount of duty at the latch timing (duty switching timing) commanded by the latch cycle switching circuit 16 to the latched duty. Is a circuit for latching.

The pulse width generation circuit 15 outputs a pulse signal having an ON time corresponding to the duty (latch duty) latched by the duty addition latch circuit 14 to the AND circuit 12 based on the output of the duty addition latch circuit 14. Hereinafter, the overall operation will be further described. Immediately before the electric load 51 is turned on during the normal operation of the generator 2, the pulse width generation circuit 15 outputs the added duty waveform to the AND circuit 12, and takes the logical product with the output of the comparator 10. As a result, the power transistor 11 is substantially intermittently controlled by the comparator 10. The duty of the AND circuit 12 generated by the intermittent operation of the comparator 10 is periodically input to the duty storage circuit 13 and stored.

The determination circuit 17 detects an intermittent low level (0) of the output of the comparator 10 using the output of the pulse width generation circuit 15 as a timing signal during normal operation, and then turns on the electric load 5. And the output of the comparator 10 is always at the high level (1) due to the decrease in Vs, and the continuous high level (1) of the comparator 10 is detected by the same timing signal as in the normal operation, and the electric load is detected. It is determined that the switch 51 is turned on, and a determination output is output to the latch cycle switching circuit 16.

The latch cycle switching circuit 16 includes a judgment circuit 17
During the continuous high level (1) of the comparator 10 after the application of the electric load, a clock signal (latch cycle switching clock) for specifying a latch cycle, which will be described later, is output based on the determination output. The duty stored in the duty storage circuit 13 is latched by the duty addition latch circuit 14 at a predetermined latch timing. The duty addition latch circuit 14 adds a predetermined duty addition amount α to the latched duty to form an added duty, and outputs the added duty to the pulse width generation circuit 15, and the pulse width generation circuit 15 A high level (1) is output to the AND circuit 12 for a corresponding period, and the power transistor 11 is turned on. Immediately before the application of the electric load, the pulse width generation circuit 15 outputs the added duty waveform to the AND circuit 12, and as a result of taking the logical product with the output of the comparator 10, the power transistor 11 is substantially turned on. It is intermittently controlled by the comparator 10.

In this embodiment, the input of the intermittent operation electric load 5 is detected by the intermittent load input detecting means 17, and the latch cycle switching circuit 16 operates at a latch cycle longer than immediately after the input of the electric load 51 which is a non-intermittent load. And duty addition. That is, the rate of increase of the exciting current is made smaller than immediately after the non-intermittent load 51 is applied, so that the fluctuation of the engine torque due to the operation of the intermittent load 5 can be suppressed and the hunting of the engine speed can be reduced.

The details of each section will be described below. First, the reference clock circuit 18, the determination circuit 17, and the latch cycle switching circuit 16 will be described in detail with reference to FIG. In FIG. 2, reference numeral 18 denotes a reference clock circuit, which includes a reference oscillator 182 oscillating at a predetermined frequency, and a cascade-connected predetermined number of counters 183 for outputting a clock 181 formed by dividing a clock output from the reference oscillator. Consists of The reference clock circuit 18 has an AND circuit 184 for outputting a logical product output 185 of the output of the counter 183 of a predetermined digit.

In the judgment circuit 17, the output of the comparator 10 is input as the input 171, the output of the pulse width generation circuit 15 is input as the input 172, the intermittent load input detection signal is input as the input 173, and the output 174 is latched. This becomes the input 161 of the cycle switching circuit 16. 175 is a D flip-flop that receives signals from the input terminals 171 and 172, 176 is a comparator, 177 is an AND circuit,
178 is a NOT circuit.

The operation of each part of the determination circuit 17 before and after the intermittent load 5 or the electric load 51 is turned on will be described with reference to the timing charts of FIGS. When the intermittent load 5 is turned on from the normal control state, the output of the comparator 10 is always at the high level (1), the input terminal 171 is always at the high level (1), and the state of the output terminal of the pulse width generation circuit 15 immediately after that. Since the input is inverted by the NOT circuit 178, the Q output of the D flip-flop 175 becomes high level (1) at the time when it becomes high level (1) (falling edge of 175CK).

On the other hand, when the intermittent load 5 (switch 6) is turned on, the input terminal 1 of the judgment circuit 17
A voltage is applied to 73 and input to the comparator 176. At this time, the output of the comparator 176 set to the threshold Va lower than the applied voltage is switched from high level (1) to low level (0) by the intermittent load 5, and the flip-flop 175 As a result of taking the logical product of the output Q and the AND circuit 177, the determination circuit 17 inputs a low level (0) to the input terminal 161 of the latch cycle switching circuit 16 through the output terminal 174.

The latch cycle switching circuit 16 includes the NOT circuit 1
64, an AND circuit 165, and an OR circuit 166. The input 161 and the clocks 181 and 188 are inputted.
The output 163 is output. The latch cycle switching circuit 16 outputs the clock 181 as the output 163 when the output 174 of the determination circuit 17 is at the high level (1), and outputs the clock 188 when the output 174 is at the low level (0). That is, immediately after the intermittent load 5 is turned on, the clock 188 (the clock cycle is set longer than 181) is output because of the low level (0).

Similarly, when the electric load (non-intermittent load) 51 is turned on in the normal control state, the input of the comparator 176 remains at the low level (0) as before, and the input voltage at this time is maintained. The output of the comparator 176 set to the threshold value Va higher than the low level also remains at the high level (1), as before. Therefore, as a result of ANDing the output Q of the flip-flop 175 and the AND circuit 177, the determination circuit 17 inputs a high level (1) through the output terminal 174, and the latch inputs the input terminal 161 of the cycle switching circuit 16. As described above, immediately after the non-intermittent load 51 is applied, the intermittent load 5
Clock 181 having a relatively shorter cycle than immediately after
It is output from the output terminal 163 of the latch cycle switching circuit 16.

Next, an embodiment of the duty storage circuit 13, the duty addition latch circuit 14, and the pulse width generation circuit 15 will be described with reference to FIG. Duty storage circuit 1
3, the input 131 is the output of the AND circuit 12, the input 132 is the output 186 of the reference clock circuit 18, and the input 133 is the output 185 of the reference clock circuit 18.
The number of outputs 134 of the duty storage circuit 13 is determined according to the number of bits (resolution). For example, in the case of 5 bits (resolution: 1/2 ⁵ ), there are five outputs. 13
Reference numeral 5 denotes an AND circuit, which serves as a gate for counting the ON time of the power transistor 11 and lowers the frequency-divided output 186 of the reference clock circuit 18 only during the period when the output of the AND circuit 12 is at the high level (1). The value is sent to the digit counter 136, and the counter 136 counts it. Thus, the ON time of the power transistor 11 is counted by the counter 136. Here, as with the output 134 described above, at least five counters are required in the case of 5 bits. In this embodiment, the circuit is configured to count the ON time within one cycle.
It is also possible to count the sum of the ON times for the cycles, or to calculate and output the average value. For example, one or two counters 136 may be added, the number of count bits may be increased by one or two bits, and the upper bits may be output. Reference numeral 137 denotes a NAND circuit. When all the outputs 134 of the respective counters 136 go to a high level (1), an AN circuit
The output of the D circuit 135 is clamped to a low level (0), and the operation of the counter 136 is stopped.

The reset of the counter 136 is performed by inputting the output 185 of the reference clock circuit 18 to the R terminal as a reset input 133. The output 185 is obtained by calculating the logical product of the outputs of a predetermined number of counters 183 so that one pulse is generated every predetermined period (intermittent period of the power transistor 11). The predetermined period is the AN of the reference clock circuit 18.
It is equal to the cycle of the output 185 of the D circuit 184, that is, the output cycle of the most significant digit counter 183 input to the AND circuit 184.

Next, the duty addition latch circuit 14 will be described. The duty addition latch circuit 14 includes a flip-flop 144 provided by the number of digits of the counter 136 of the duty storage circuit 13, and an addition circuit 145 for adding a predetermined value (duty addition amount α) to the output of the flip-flop 144. CK of each flip-flop 144
Terminal input (hereinafter referred to as latch pulse (LP) input)
141 is a clock 181 and each flip-flop 1
The D terminal input 142 of 44 is individually constituted by each digit output of each counter 136 of the duty storage circuit 13. The output of the flip-flop 144 is added with the duty addition amount α by the adding circuit 145, and outputs a predetermined number (the same number as the number of outputs of the duty storage circuit 13) of the outputs 143 as added duty. The number of outputs 143 can be changed according to the binary digit number (bit number) of the added duty.

The operation of the duty addition latch circuit 14 will be described.
Each data of the output 134 of the duty storage circuit 13 is latched for each bit at a period of 41 (= clock 181).
The output of each flip-flop 144 holds the immediately preceding latch data while the LP input 141 is at the high level (1). The addition circuit 145 adds the duty addition amount α to the data latched by each flip-flop 144, that is, the immediately preceding duty, and outputs the added duty 143.

An example of the adding circuit 145 will be described with reference to FIG. The addition circuit 145 has 3 bits (resolution 1/2).
³ = 0.125), and outputs an added duty in which the duty from 0 to 100% is divided into eight stages. The inputs 1451 to 1453 of the adder circuit 145 are individually constituted by the output 142 of the flip-flop 144, and the input 1453 is the flip-flop 144 of the most significant digit.
, The input 1452 receives the output of the flip-flop 144 of the next digit, and the input 1451 receives the output of the flip-flop 144 of the next digit. The input 1451 is inverted by the NOT circuit 1451 and output from the least significant digit through the least significant OR circuit 1458.
31 and the input 1452 is the lower half-adder 145
5 is added to the input 1451, and the added value without carry is output through the OR circuit 1458 of the next digit to the output 1 of the intermediate digit.
432, and the input 1453 is the half-adder 1 of the most significant digit.
455: AND circuit 14 of lower half-adder 1455
The added value which is added to the carry value from 57 and is not carried is output to the most significant digit output 1433 through the most significant digit OR circuit 1458. The half adder 1455 includes an EXOR circuit 1456 and an AND circuit 1457, as is well known. Further, the AND circuit 1 of the most significant half adder 1455
If a carry is output from 457, each OR circuit 145
8 through 3 bit outputs 1431, 1432, 1433
(111), that is, a duty of 100% is output. By doing so, 3-bit inputs 1451, 145
2, 1453 as the duty addition amount α (001 = duty 12.5%).

Note that the most significant digit half adder 1455
The D circuit 1457 becomes high level (1) (a carry signal is generated by the half-adder 1455 of the highest digit) when the 3-bit inputs 1451, 1452, and 1453 of the adder circuit 145 are (111 = 100% duty). In this case, the output of the NOT circuit 1454 and the output of the EXOR circuit 1456 of each half adder 1455 become (000).
The output of the adder circuit 145 is set to (111) instead of (000) by the carry value of.

In this embodiment, the addition circuit 145 is configured to perform addition after latching, but may be configured to add before latching (not shown). If the duty addition amount α is given as a preset value to the counter 136 of the duty storage circuit 13, the addition circuit 145 becomes unnecessary. Next, the pulse width generation circuit 15 will be described.

The inputs 151 and 152 comprise outputs 186 and 186 of the reference clock circuit 18, respectively.
Numeral 54 denotes an output 143 of the duty addition latch circuit 14, and 153 denotes an output of the pulse width generation circuit 15 and A
The signal is sent to the ND circuit 12 and the determination circuit 17. 155 is a counter with preset, 156 is an AND circuit, 157
Is a NAND circuit, and 158 is a NOT circuit. The counter 155 is provided individually for each bit, and the output 143 of the duty addition latch circuit 14, that is, the added duty is input to the preset terminal of the counter 155.
Is individually input as a preset value, and the counter 1
55 designates an input 154 as an output 186 of the reference clock circuit 18.
At the timing, the count UP is started with the preset value as an initial value. The NAND circuit 157 is connected to each counter 1
When all the outputs Q of 55 are at high level (1), A
The output of the ND circuit 156 is clamped to "0" to stop the operation of the counter 155. Therefore, counter 1
Numeral 54 starts counting from a binary value corresponding to the preset added duty, and during this counting period, the NAND circuit 157 operates as the NOT circuit 158.
Outputs a low level (0) to the AND circuit 12 through
The power transistor 11 is turned off. Then, if all the outputs Q of the respective counters 155 become high level (1),
Since the counting is stopped and the outputs of the counter 155 are all clamped to 1, the NAND circuit 157 outputs a high level (1) to the AND circuit 12 through the NOT circuit 158, and the power transistor 11 is turned on. Thereafter, when the AND circuit output 185 outputs a high level (1) from the reference clock circuit 18, the pulse width generation circuit 15
Are preset, all the counters 136 of the duty storage circuit 13 are reset,
Thereafter, the above operation is repeated at the cycle of the AND circuit output 185 until the amount of power generation (duty of the power transistor 11) corresponding to the electric load is reached.

That is, the pulse width generating circuit 15 turns off the power transistor 11 when the count value corresponding to the inputted added duty is preset in the counter 155, and further starts counting from the preset value. When the count value reaches the maximum value, the power transistor 11 is turned on. Preset cycle (cycle of output signal of AND circuit 185)
Is constant, the off period of the power transistor 11 is reduced (the duty is gradually increased).

The duty stored in the duty storage circuit 13
When the duty of the power transistor 11 is gradually increased by adding the duty addition amount α to the power, the power generation amount of the generator 2 gradually increases, and when the potential of the battery 3 rises to a predetermined level, the comparator 10 Is inverted to shut off the power transistor 11 through the AND circuit 12, and
The excitation current is controlled by the intermittent operation of the comparator 10.

The above operation will be described below. When the non-intermittent load 51 is applied, the latch cycle switching circuit 16 outputs CK1 (output 181 of the reference clock circuit 18) as the latch pulse LP. The duty increased by a predetermined duty + α in the cycle of CK1 is output to the pulse width generation circuit 15, and the pulse width generation circuit 15 outputs the input duty pulse to A.
The signal is output to the transistor 11 through the ND circuit 12 and is intermittently controlled. The gradual excitation control for increasing the duty at a constant increasing rate is performed until the comparator 10 is inverted, and thereafter, the transistor 11 is intermittently controlled at the duty at the time when the comparator 10 is inverted. This prevents a sudden increase in the engine load and a sudden decrease in the engine speed due to the sudden increase (see FIG. 7).

When the intermittent load 5 is applied, the latch cycle switching circuit 16 outputs CK2 having a longer cycle than CK1 as the latch pulse LP. The duty addition latch circuit 14 outputs the cycle of the clock CK2 from the duty immediately before the intermittent load 5 is applied. And outputs the duty increased by a predetermined duty + α to the pulse width generation circuit 15.
Outputs the input duty pulse to the transistor 11 through the AND circuit 17, and controls the intermittent output.

Here, since CK2 is longer than CK1, the rate of increase of the duty is correspondingly reduced, and the increase of the engine load is correspondingly reduced. Here, the reason why CK2 is made longer than CK1 to reduce the average rate of increase in duty is that the intermittent load 5 itself is periodically intermittent, so that changes in the engine load and the engine speed are repeated at regular intervals. This is to suppress so-called hunting, which suppresses the occupant from feeling uncomfortable. FIG. 7 shows the on / off state of the intermittent load 5 and the case where the latch pulse LP is CK1 and L
7 shows a change in duty and a change in engine speed when P is CK2. As can be seen, the intermittent load 5
At the time of turning on, the period of the latch pulse LP = CK2 is extended, so that hunting of the engine speed can be reduced.

In the above embodiment, the comparator 10, the AND circuit 12, the pulse width generation circuit 15, the duty addition latch circuit 14, the duty storage circuit 13,
Although the configuration includes the latch cycle switching circuit 16 and the determination circuit 17, it is obvious that some or all of the circuits and the comparator can be provided outside the voltage control device 1. Modifications will be described below. (See another embodiment in FIG. 7) In the above embodiment, the cycle of the latch pulse LP at the time of driving the intermittent load 5 is CK2, but the LP cycle at this time may be infinite. In this case, the duty is fixed to the duty immediately before the intermittent load 5 is applied.

The ON duty (duty) increase amount + α can be increased even when a preset value is given to the duty storage circuit 13.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing one embodiment of a voltage control device according to the present invention;

FIG. 2 is a circuit diagram showing a determination circuit, a latch cycle switching circuit, and a reference clock circuit of FIG. 1;

FIG. 3 is a timing chart showing an increase in duty when an intermittent load is applied in FIG. 1,

FIG. 4 is a timing chart showing an increase in duty when a non-intermittent load is applied in FIG. 1,

FIG. 5 is a circuit diagram showing a duty storage circuit, a duty addition latch circuit, and a pulse width generation circuit of FIG. 1;

FIG. 6 is a circuit diagram showing a part of the duty addition latch circuit of FIG. 5;

FIG. 7 is a timing chart illustrating the effect of the present invention.

[Explanation of symbols]

1 is a voltage control device, 2 is a vehicle generator, 3 is a battery,
5 is an intermittent drive electric load, 10 is a comparator (basic control unit),
12, 13, 14, 15, 16, 17, 18 are gradual excitation control units, 16 is a latch cycle switching circuit (intermittent load input control means), 17 is a judgment circuit (intermittent load input detection means), 5
1 is a non-intermittent operation electric load.

Claims (1)

(57) [Claims] A basic control unit for controlling an exciting current of a vehicular generator that supplies power in parallel to an electric load and a battery to a value corresponding to a required level of the electric load and the battery, and detecting the input of the electric load and A predetermined exciting current change from immediately after the electric load is applied to the exciting current from an exciting current value corresponding to the magnitude of the electric load immediately before the electric load is applied to an exciting current value corresponding to the magnitude of the electric load after the electric load is applied. A voltage control device for a vehicle generator, the voltage control device comprising: a gradual excitation control unit that gradually increases at a rate. The gradual excitation control unit includes at least an intermittent load input detection unit that detects input of an intermittent operation electric load; Intermittent load input control means for setting the excitation current increase rate after the input is smaller than the excitation current increase rate after the non-intermittent operation electric load is input. Machine voltage control device.