JPS6032438B2 - Pulse generation circuit of sample and hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for generating sample pulses and reset pulses in a sample-and-hold speed control system using an external motor equipped with a frequency generator.

A conventional speed control device for this type of motor is shown in FIG.

In Fig. 1, the detection pulses shown in Fig. 2a, obtained through a frequency generator 2 attached to the rotating shaft of the motor 1, are normally processed by a differentiating circuit using a capacitor and a resistor, as shown in Fig. 2b. The waveform is shaped by a waveform shaping circuit 3 equipped with a waveform shaping circuit 3, and is inputted to a monostable multipipulator 4 which oscillates a predetermined pulse width T, to form a rectangular wave as shown in FIG. 2c. A pulse delayed by a time T, as shown in FIG. 2d, is thus obtained. This pulse is applied to a second monostable multipipulator 5 with a pulse width L, and
We get a delayed square wave as shown in . Using this as a reset pulse, it is added to the trapezoidal wave generating circuit 6 to obtain the trapezoidal wave shown in FIG. 2f. This trapezoidal wave is applied to the speed detection circuit 7, and the detection pulse shown in FIG. 2b is added as a sampling pulse. Thus, the speed detection circuit (
The sample-and-hold circuit) 7 detects the voltage at the nascent part of the trapezoidal wave (Fig. 2 f) delayed by one period and detects the voltage at the oblique part (Fig. 2 b).
) By sampling, a detection voltage as shown in FIG. 2g can be detected as a DC-like voltage depending on the speed.
This voltage is compared with a reference voltage in a comparison/amplification circuit 8 to control the motor at a constant speed. However, this method of generating sample pulses and reset pulses has a disadvantage in that two monostable circuits with poor temperature characteristics are continuous.

In order to eliminate the above drawbacks, the present invention uses a reference frequency oscillator with a higher frequency than the signal generated by the frequency generator, a counter with a reset terminal, and a gate circuit to create sample pulses and reset pulses for the speed detection circuit. The purpose is to operate the motor with high stability and precision.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention. 2 is a frequency generator; 101 is a circuit for amplifying and waveform-shaping the signal generated by the frequency generator; 102 is a reference frequency oscillator with a higher frequency than the signal generated by the frequency generator 2; 103 is a circuit for generating signals from the frequency generator 2; The first signal is “
104 is a counter with a reset terminal that releases the reset terminal only during "H" (or "L"), and 104 combines the outputs of the counter with the reset terminal described above to create a sample pulse having a predetermined phase and a required pulse width. 105 is a gate circuit that generates a reset pulse having a certain phase delay and a required pulse width from the sample pulse; 106 is a gate circuit that generates a reset pulse having a predetermined pulse width; 106 is a gate circuit that generates the frequency generator 2 after generating the pair of sample pulses and the reset pulse; Second part
This is a gate circuit that inhibits input pulses to the counter until the pulse signal becomes "H" (or "L").

Rotation signal “H” (or “L”) from frequency generator 2
is applied, the waveform shaping circuit 101 amplifies the waveform, releases the reset of the counter 103 with a reset terminal, reads the reference frequency obtained by the reference frequency oscillator 102, and generates a sample pulse of a predetermined phase and predetermined pulse width in the gate circuit 104. Then, a gate circuit 105 generates a set pulse with a predetermined pulse width delayed by a predetermined time.
After the pair of sample pulses and reset pulses are generated, the gate circuit 106 prohibits pulse generation until the next rotation signal "H" (or "L") arrives. According to such a circuit, speed detection is possible to generate a sample pulse having an accurate phase and pulse width according to the rotation signal generated by the frequency generator 2, and a reset pulse having a more accurate delay time and pulse width than the sample pulse. It is possible to obtain a speed control circuit with a circuit (sample and hold circuit).

Next, FIG. 4 shows a sample-and-hold circuit which is a specific embodiment of the present invention, and the structure and operation thereof will be explained below with reference to the drawings.

2 is a frequency generator, and 9 and 10 are amplifiers and waveform shaping circuits.

This output waveform is shown in FIG. 5a. 102 is a reference frequency oscillator higher than the signal generated by the frequency generator; 11
is a frequency divider that divides down to the optimum frequency for creating sample and reset pulses.

12 is a NOR gate, and 13 is a counter with a reset terminal.
In the L'' state, the reset is released and the output signal of the frequency divider 11 starts counting.

The outputs 0, 02 03 04 of each stage of the counter 13 are as shown by def in FIG. 5, respectively. 14 is an inverter; 15, 16, 17, and 18 are a group of sample pulse generation gates; 15, 16, and 17 are inverters;
8 is a 4-input AND gate.

The output of this gate 18 is the inverted output of the output of the waveform shaping circuit 10, the 02 output of the counter 13, and the 02 output of the counter 13.
This is an AND output of the inverted output of 08 of 3 and the inverted output of 04 of the counter 13, and generates a pulse as shown in FIG. 5k. This is exactly 2 times from the falling edge of the output (Figure 5a) obtained by amplifying and shaping the output of frequency generator 2 to the second output pulse (Figure 5b) after dividing the reference frequency.
This means that pulses corresponding to the period have been generated. Next 17, 19
, 20, 21, and 22 are reset pulse generating gate groups, 17 is an inverter, and 19 to 22 are NAND gates. NAND gate 19 is 0, output of counter 13, 0
The signal shown in FIG. 5g is generated by the inverted output of 3 and 04. On the other hand, the NAND gate 20 has a counter 13
0, 02, 03, 04 outputs generate the signals shown in FIG. 5h. These two signals and a signal obtained by inverting the output of the waveform shaping circuit 10 by the inverter 15 are sent to the NAND gate 2.
A flip-flop composed of 1 and 22 generates the signal shown in FIG. This means that a reset pulse having a delay time of exactly one cycle of the output pulse after the reference signal division than the sample pulse and a pulse width of 10 cycles was obtained. At this time, that is, when the NAND gate 20 generates a pulse (Fig. 5h), the world power sends a positive signal to one input terminal of the NOR gate 12 through the inverter 14, and thereafter the output of the frequency divider 11 is sent to the counter 3. The input is the pulse after waveform shaping of the frequency generator signal (Fig. 5a)
) is inhibited until it reaches the "H" state, making it possible to obtain a pair of sample and reset pulses with accurate pulse width and delay time for one period of the frequency generator signal. The IJ set pulse (FIG. 5i) from the NAND gate 21 created in this way is applied to the gate of the reset transistor 23 in the sample-and-hold circuit shown in block S, and V is applied to the gate of the reset transistor 23 in the sample-and-hold circuit shown in block S.

. (10 potentials) The electric charge of the capacitor 26 charged via the resistor 25 is discharged from the terminal 24. When the sample pulse (FIG. 5k) is applied to the transmission gate 27 at the point when the reset pulse (FIG. 5i) has ended and the capacitor 26 has been gradually charged through the resistor 25, the charge on the capacitor 26 is The potential is transferred to the hold capacitor 28 via the transmission gate 27 and is applied to the gate of the transistor 29, and as a result, the resistor 3
Approximately the potential of the hold capacitor 28 is output between both ends of 0, that is, between the output terminals 31 and 32 (FIG. 5m). In this way, the DC voltage can be extracted in accordance with the speed. In the above embodiment, the pulse width and delay time of the reset pulse are determined as described above, but the pulse width and delay time can be varied by changing the combination of gates for creating each pulse. It is possible to generate a sample pulse and a reset pulse.

As described above, by using the circuit of the present invention, the sample-and-hold speed control device can obtain sample pulses and reset pulses with accurate pulse width and delay time according to the oscillation frequency of the reference frequency oscillator (for example, a crystal oscillator). This has the advantage of improving control accuracy and stability, and improving the performance of the entire device.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional sample-and-hold type speed control device, Fig. 2 is a waveform diagram of each part thereof, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a specific example of the present invention. A circuit diagram showing an embodiment, and FIG. 5 are waveform diagrams of various parts thereof. 2...Frequency generator, 102...Reference frequency oscillator, 9...Amplifier, 10...
・Waveform shaping circuit, 11... Frequency divider, 12... NOR gate, 13... Counter with reset terminal, 14, 15, 16, 17... Inverter, 18... AND gate, 19, 20, 21, 22... NAND gate, S... Sample and hold circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1 A circuit for amplifying and waveform-shaping the signal generated by the frequency generator, a reference frequency oscillator with a higher frequency than the signal generated by the frequency generator, a counter with a reset terminal, and a gate circuit, 1 signal is “L”
” (or “H”), the reset terminal of the counter is released, the reference frequency signal is counted, and the output of the counter is used by a gate circuit to generate a sample pulse having a predetermined phase and a predetermined pulse width; A reset pulse having a certain phase delay from the sample pulse and a required pulse width is generated from the counter output by the gate circuit, and after the pair of sample pulses and the reset pulse are generated, a second pulse from the frequency generator is generated. 1. A pulse generation circuit for a sample-and-hold circuit, characterized in that input pulses to a counter are inhibited by a gate until a pulse signal becomes "L" (or "H").