JPS5827759B2 - Mortanosokudoseigiyosouchi - Google Patents

Description

[Detailed description of the invention] The present invention relates to a motor speed control device.

Generally, this type of device includes means for obtaining a first pulse having a pulse width corresponding to the speed of the motor, and means for obtaining a second pulse having a predetermined pulse width, A speed error signal is obtained by comparing the pulse width with the pulse width of the second pulse, and the speed of the motor is adjusted based on the error signal.]
What it does is known.

A specific example of this is shown in Figure 1. In Figure 1, 1
is an input terminal, into which, for example, pulses from a pulse generator that generates third pulses (one per rotation, etc.) proportional to the rotation of the DC motor are input.

2 is a monostable multi-by-break, which is triggered by a pulse from terminal 1.

3 is a monostable multi-by-break, which is triggered by the output pulse of the monostable multi-by-break 2 written in -, tr-.

Numerals 4 and 5 are NAND game 1, into which the output pulses of the monostable multi-by-breaks 2 and 3 are input.

6 is an inverter, and the output of the Nandt gate 4 is manually input and phase-inverted.

DI and D2 are diodes whose different poles are connected to the same terminal of a capacitor C to form a charging circuit and a discharging circuit for the capacitor.

7 indicates an output terminal.

In such a device, when the above-mentioned pulse shown in FIG. 2A is applied to the terminal 1, the monostable multivibrator 1
A fourth pulse having a pulse width t1 shown in FIGS. 2B and 2C, respectively, is obtained from the output terminals Q and Q of the output terminal 2.

The pulse from the terminal Q is input to the monostable multi-bi break 3, and a second pulse having a pulse width t2 shown in the second diagram E is obtained from the output terminals Q and Q of the mono-stable multi-bi break 3.

The period obtained by adding these pulse widths t1 and t2 corresponds to the pulse interval when the pulse to the input terminal 1 is at the reference speed.

What is shown in FIG. 2 is a case where the speed is faster than the standard one, and the interval between pulses to terminal 1 is shorter than the sum of pulse widths t1 and t2.

In such a case, the Nandt gate 4 to which the pulses shown in Figure 2 and the pulses shown in Figure 2C are applied has both inputs (
(There is no period during which the output becomes H as shown in FIG. 2F.

On the other hand, in the Nant gate 5 to which the respective pulses shown in FIG. 2B and E are applied, there is a period Δt in which both inputs are H, and during this period, the output is L as shown in FIG. 2G.

Since the output of the Nant gate 4 is inverted by the inverter 6, the diode D1 is reverse biased and the capacitor C is not charged, but during the period when the output of the Nant gate 5 is L, the diode D2 is forward biased. Capacitor C is discharged via the diode D2.

When this capacitor C is discharged, the voltage at the terminal 7 gradually decreases, and the speed of the DC motor etc. is controlled to decrease in accordance with the voltage.

The above explanation is for the case where the speed is fast, but when the speed is the same as the reference speed, as shown in FIG. 3 (A-G indicate pulses at the same points as A-G in FIG. 2, respectively), The pulse interval at terminal 1 becomes equal to the sum of t1 and t2, the outputs of Nant gates 4 and 5 become H, diodes DI and D2 are reverse biased, and capacitor C is not charged or discharged (0).

Therefore, there is no change in the voltage at terminal I, and the speed of the DC motor, etc. does not change.

Next, the case where the speed is slow will be explained with reference to FIG.

In FIG. 4, A-G indicates pulses at the same point as A-G in FIG.

When the speed is slow, the pulse interval of terminal 1 is equal to t1 and t.
2, and an L period occurs in the output of the NAND gates 1 and 4 as shown in F. This is inverted by the inverter 6, and the diode D1 is biased in the forward direction. Capacitor C is charged via the capacitor C.

The output of the Nant gate 5 has no L period, and the diode D2 is reverse biased and the capacitor C
is not discharged.

Therefore, the voltage at the terminal 7 increases, and the speed of the DC motor etc. is controlled to increase.

In addition, among the above-mentioned fourth pulses, the period between the trailing edge of one pulse and the leading edge of the next pulse is the pulse width (constant) of the fourth pulse from the period of the third pulse. Therefore, the period depending on the speed of the motor, i.e. the first
This can be said to be a pulse.

In the above example, a Nant gate was used, but it can also be implemented using Nord gates 8 and 9 as shown in FIG.

Also, as shown in Figure 8, Nantes Gate 10 and Noah Gate 11
It can also be implemented using

In such a device, as shown in FIG. 6 (A to G correspond to those in FIGS. 2 to 4, and the case 1.>t2 is shown), the period of the third pulse is When the speed of the motor increases to a range that does not exceed the fourth pulse width t1, the capacitor C is charged in the same manner as in FIG. 4, and the morph is controlled to become even faster.

Further, as shown in FIG. 7 (A to G correspond to those in FIGS. 2 to 4, and indicate the case where t1 < t2), the period of the third pulse is equal to the second pulse. When the motor speed increases to a range that does not exceed the pulse width t2, the capacitor C
After the discharging period Δt2, there is a charging period Δt1, and the average voltage I== of the capacitor C is maintained by the charging.

If the speed of the above motor is slightly lower, the above charging period will be △
Since t1 becomes longer, the speed of the motor does not decrease.

The present invention eliminates the above-mentioned drawbacks, and in order to prevent the abnormal operation shown in FIGS. 6 and 7 from occurring, the period of the third pulse is equal to the pulse width of the fourth pulse and the second pulse. The torque/speed curve or power supply voltage of the motor is set so that the maximum value of the rotational speed of the motor in use is selected within a range exceeding the pulse width of the pulse.

In general, in a monostable multi-bibreak, there is a region in which no trigger is applied for a period from the trailing edge of the pulse.

Therefore, when using a monostable multi-bibreak as a means for obtaining a pulse with a predetermined pulse width, the above-mentioned pulse width t1. t2. It is necessary to select the period of the first pulse or the period of the third pulse by adding the period corresponding to the above region to t3.

As described above, the present invention provides a third
a first monostable multi-pie break for obtaining a fourth pulse having a first constant pulse width based on the third pulse obtained by the means; and after the fourth pulse. a second monostable multi-by-break for obtaining a second pulse having a second constant pulse width with reference to the edge; and a period from the trailing edge of one pulse to the leading edge of the next pulse in the fourth pulse; a first gate circuit to which the output of the first monostable multi-bi break and the output of the second monostable multi-bi break are supplied, in order to compare the pulse widths of the two pulses and obtain an error signal from this comparison; It comprises a second gate circuit and a capacitor that is charged by the output of one of the first gate circuit and the second gate circuit and discharged by the output of the other gate circuit. Where the speed of the motor is controlled by voltage, the maximum rotational speed of the motor in use is within a range in which the third Harusuno period exceeds the pulse width of the fourth pulse and the pulse width of the second pulse. Since the value is selected, the abnormal operation of the motor described above can be prevented.

[Brief explanation of drawings]

FIGS. 1, 5, and 8 are block diagrams for explaining the present invention, and FIGS. 2 to 4, 6, and 7 are timing charts of the above block diagrams.

Claims (1)

[Claims] 1 means for obtaining a third pulse corresponding to the period of rotation of the motor; and a first monostable multiplier for obtaining a fourth pulse having a first constant pulse width based on the third pulse obtained by the means. a vibrator; a second monostable multi-vibrator for obtaining a second pulse having a second constant pulse width with reference to the trailing edge of the fourth pulse; The output of the first monostable multi-bi break and the output of the second monostable multi-bi break are used to compare the period up to the leading edge of the pulse with the pulse width of the second pulse and obtain an error signal from this comparison. is supplied to the first gate circuit and the second gate circuit, and among these first gate circuit and second gate circuit, the negative gate circuit is charged by the output, and the other gate circuit is charged by the output of the negative gate circuit. and a capacitor that is discharged by the output, and the speed of the motor is controlled by the voltage of the capacitor, wherein the period of the third pulse described in - is equal to the pulse width of the fourth pulse and the pulse width of the second pulse. A speed control device for a motor, characterized in that the maximum value of the rotational speed of the motor in use is selected to be within a range exceeding the pulse width.