SU421107A1 - FORMER OF CLUTCH PULSES - Google Patents

Description

one

The invention relates to an imiuls generator and can be used in digital computing devices and automation.

The well-known clock pulse former contains two flip-flops, with the outputs of the first flip-flop via the first and second coincidence circuits, the first OR circuit, the first and second amplifiers are connected to the inputs of two inverters, harterated by the dependence of the duration of the antiphase clock pulses on the trigger frequency which leads to instability of the duration of the output pulses of the driver.

The purpose of the invention is to increase the stability of the duration of the output pulses.

This is achieved by introducing into the device a third, fourth and fifth coincidence circuit, a second OR circuit and a third inverter connected to the remaining units of the device in such a manner: M that short phase and long antiphase pulses are formed with phase overlapping antiphase.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - time diagrams.

The clock pulse generator contains the first trigger 1, the outputs of which through the first circuit 2 match and the second circuit 3

matches, the first circuit OR 4, the first amplifier 5 and the second amplifier 6 are connected to the inputs of the first inverter 7 and the second inverter 8, the second trigger 9, the third match circuit 10, the fourth match circuit 11, the fifth match circuit 12, the second OR circuit 13 and a third inverter 14, the input of which is connected to a terminal 15 connected to a source of trigger pulses, the waveform of which is shown in FIG. 2, a. From the output terminals 16 and 17, clock sequences are removed, the shape of which is shown in FIG. 2, b and 2, b, respectively. FIG. 2, d and FIG. 2, d respectively, the output waveform from the flip-flops 9 and 1 is presented; - the times at which the successive stages of the shaper operation are completed. The output of the inverter 14 is connected to the inputs

the first OR 4 circuit and the second OR 13 circuit and to the input of the first trigger 1. The outputs of the first trigger 1 are additionally connected via the third coincidence circuit 10 and the fourth coincidence circuit 11, as well as the second

the circuit OR 13 with the inputs of the second trigger 9, the outputs of which are connected to the second inputs of the first matching circuit 2 and the second matching circuit 3. One of the outputs of the second trigger is additionally connected to the input

the first trigger 1 through the fifth coincidence circuit 12, the other input of which is connected to the output of the second amplifier 6.

Shaper clock pulses works as follows.

In the initial state (until time ti), the triggers 1 and 9 are off, the trigger signal at terminal 15 is absent, at terminal 16 there is a high voltage level, at terminal 17 it is low. The triggering signal from terminal 15, passing through the third inverter 14, the first circuit OR 4 and the first amplifier 5, removes a high voltage level from the terminal 16 (Fig. 2.6, time instant / i- / 2).

The signal "zero from terminal 16, connecting via the second inverter 8 and the fourth matching circuit 11, prepared by the signal from the inverse output of the nerve trigger 1, turns on the second trigger 9 (time).

The signal "unit from the output of the trigger 9, passed through the second coincidence circuit 3, prepared by the signal from the inverse output of the first trigger 1, and the second amplifier 6, forms a high voltage level on terminal 17 (Fig. 2.0, time).

The signal "unit from the terminal 17, passed through the fifth coincidence circuit 12, prepared by a signal from the output of the second trigger 9, starts the first trigger 1 (Fig. 2, d, time). The signal" zero from the inverse output of the first trigger 1 After passing through the second coincidence circuit 3 and the second amplifier 6, it removes a high voltage level at the terminal 17 (Fig. 2, at, the time of the change / 5-U). The signal "zero from terminal 17, passed through the first inverter 7, the third coincidence circuit 10, prepared by a signal from the output of the trigger 1, and the second circuit OR 13, turns off the second trigger 9 (FIG. 2, g, moment of time

).

The signal "unit from the inverse output of the second trigger 9, passed through the first circuit 2 of coincidence, prepared by the signal from the output of trigger 1, the first circuit" OR 4 and the amplifier 5, forms a high level of voltage on the M.M. 16 (Fig. 2, b, time tj-t).

Iri switching off the trigger signal, the signal “zero from terminal 45, passed through the third inverter 14, is fed simultaneously to the input of the nerve trigger I, disconnecting it, and to the input of the first circuit“ OR 4, confirming the signal “unit on cell 16 before that , as

turns off the first trigger 1 and prohibits the passage of the unit through the first scheme. 2 matches (monetary / d-th). For the device to work properly, it is necessary that the duration of the trigger trigger edge does not exceed the time required for the signal to pass through the element.

Subject invention

The clock pulse driver contains the first trigger, the outputs of which are through the first and second matching circuits, the first ILR1 circuit, the first and second amplifiers are connected to the inputs of the first two inverters, and the second trigger, whose outputs are connected to the second inputs of the first and second matching circuits, which differ For example, in order to increase the stability of the duration of the output pulses,

the third, fourth and fifth coincidence circuits, the second OR circuit and the third inverter, whose input is connected to the source of scans, and the output connected to the inputs of the first and second OR circuits, and to the input of the first trigger, with the outputs of the first trigger additionally connected through the third and fourth joint schemes and the second OR circuit with the inputs of the second trigger, one of the outputs of which is terminally connected

with the input of the first trigger through the fifth coincidence circuit, another input of which is connected to the output of the second amplifier.

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FIG. 2