JPS5850396B2 - signal selection circuit - Google Patents

signal selection circuit

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Publication number
JPS5850396B2
JPS5850396B2 JP9503076A JP9503076A JPS5850396B2 JP S5850396 B2 JPS5850396 B2 JP S5850396B2 JP 9503076 A JP9503076 A JP 9503076A JP 9503076 A JP9503076 A JP 9503076A JP S5850396 B2 JPS5850396 B2 JP S5850396B2
Authority
JP
Japan
Prior art keywords
circuit
signal
output
input terminal
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9503076A
Other languages
Japanese (ja)
Other versions
JPS5319855A (en
Inventor
照雄 法師
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP9503076A priority Critical patent/JPS5850396B2/en
Publication of JPS5319855A publication Critical patent/JPS5319855A/en
Publication of JPS5850396B2 publication Critical patent/JPS5850396B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は、1つの計数器に2つの計数を行なわせる為の
信号選択回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal selection circuit for causing one counter to perform two counts.

例えばテープレコーダ等における途中迄使用されたテー
プのテープ残量を表示するような場合、テープレコーダ
にテープを装着し、テープの駆動を開始した時直ちに現
在位置におけるテープ残量が計数され表示されなければ
ならす、その後テープの走行につれてテープ残量が刻々
変化するのを表示しなければならない。
For example, when displaying the remaining amount of tape on a partially used tape in a tape recorder, etc., the remaining amount of tape at the current position must be counted and displayed immediately when the tape is loaded into the tape recorder and the tape begins to drive. After that, the amount of remaining tape must be displayed as it changes every moment as the tape runs.

上述の如き2つの計数を異る計数器で行うのは得策でな
く、1つの計数器を用い、2つの異る信号を同一の状態
に変換して前記計数器に印加するようにすれば、回路の
簡略化を計ることが出来る。
It is not a good idea to perform the above two counts using different counters, but if one counter is used and two different signals are converted into the same state and applied to the counter, The circuit can be simplified.

本発明は、上述の目的を達成する為に威されたもので、
以下実施例に基き、図面を参照しながら説明する。
The present invention has been made to achieve the above-mentioned objects.
Hereinafter, an explanation will be given based on an example with reference to the drawings.

図は本発明に係る信号選択回路の一実施例を示す回路図
で、1は入力パルスの数を計数する為の計数器、2は該
計数器1に印加される入力パルスを選択する為の信号選
択回路、3は基準信号を発生する発振器、4は周期の変
化するパルスを発生するパルス発生回路、5は前記パル
スの周期に基づくゲート信号を発生するゲート回路、6
は前記信号選択回路2を第1状態もしくは第2状態に切
換える切換え信号を発生する切換信号発生回路で、前記
信号選択回路2は、3人力NAND回路りと、2人力N
AND回路8と、2人力OR回路9と、インバータ10
とから成る。
The figure is a circuit diagram showing an embodiment of the signal selection circuit according to the present invention, in which 1 is a counter for counting the number of input pulses, and 2 is a circuit diagram for selecting the input pulse to be applied to the counter 1. a signal selection circuit; 3 an oscillator that generates a reference signal; 4 a pulse generation circuit that generates a pulse with a changing period; 5 a gate circuit that generates a gate signal based on the period of the pulse;
is a switching signal generation circuit that generates a switching signal for switching the signal selection circuit 2 to the first state or the second state, and the signal selection circuit 2 has a three-manpower NAND circuit and a two-manpower NAND circuit.
AND circuit 8, two-man OR circuit 9, and inverter 10
It consists of

しかして、前記3人力NAND回路7の第1入力端子A
は発振器3に、入力端子Bはゲート回路5に、入力端子
Cはインバータ10を介して切換信号発生回路6にそれ
ぞれ接続される。
Therefore, the first input terminal A of the three-person NAND circuit 7
is connected to the oscillator 3, the input terminal B is connected to the gate circuit 5, and the input terminal C is connected to the switching signal generation circuit 6 via the inverter 10.

又、前記2人力NAND回路8の刃端子Aは切換信号発
生回路6に、入力端子Bはパルス発生回路4に接続され
、前記3人力NAND回路7の出力端子りは2人力OR
回路9の入力端子Aに、前記2人力NAND回路8の出
力端子Cは前記OR回路9の入力端子Bにそれぞれ接続
される。
Further, the blade terminal A of the two-man power NAND circuit 8 is connected to the switching signal generation circuit 6, the input terminal B is connected to the pulse generation circuit 4, and the output terminal of the three-man power NAND circuit 7 is connected to the two-man power OR.
The input terminal A of the circuit 9 is connected to the output terminal C of the two-man power NAND circuit 8, and the output terminal C of the two-man power NAND circuit 8 is connected to the input terminal B of the OR circuit 9.

更に前記2人力OR回路9の出力端子Cは計数器1の入
力端子に接続される。
Furthermore, the output terminal C of the two-person OR circuit 9 is connected to the input terminal of the counter 1.

いま、初期値設定の計数を行なわんとすれば、切換信号
発生回路6より「L」信号が発生し、信号選択回路2は
第1状態の初期値設定状態となる。
If counting is to be performed for initial value setting, the switching signal generation circuit 6 generates an "L" signal, and the signal selection circuit 2 enters the first initial value setting state.

前記切換信号発生回路6は計数器を内蔵し、パルス発生
回路4の出力パルスを計数して最初の数パルスの間のみ
rLJ信号を発生し、その後は「H」信号を発生するよ
うに構成されている。
The switching signal generation circuit 6 has a built-in counter and is configured to count the output pulses of the pulse generation circuit 4 and generate the rLJ signal only during the first few pulses, and thereafter generate the "H" signal. ing.

前記切換信号発生回路よりrLJ信号が発生すると、イ
ンバータ10を介して3人力NAND回路Tの入力端子
GにrHJ信号が印加される。
When the rLJ signal is generated from the switching signal generation circuit, the rHJ signal is applied to the input terminal G of the three-man power NAND circuit T via the inverter 10.

又、゛ゲート回路5は、パルス発生回路4の出力パルス
の周期に応じたゲート信号を発生し、発振器3は、一定
周波数の繰り返しパルスを発生する。
Further, the gate circuit 5 generates a gate signal according to the period of the output pulse of the pulse generating circuit 4, and the oscillator 3 generates a repetitive pulse of a constant frequency.

前記パルス発生回路4の出力パルスの周期は、被検出物
(テープレコーダの場合はテープ)の位置により異り、
従ってゲート信号の「H」期間も前記被検出物の位置に
より異る。
The period of the output pulse of the pulse generating circuit 4 varies depending on the position of the detected object (tape in the case of a tape recorder),
Therefore, the "H" period of the gate signal also differs depending on the position of the object to be detected.

その為、ゲート信号のゲート期間に対応する前記発振器
3の繰り返しパルスの数も異る。
Therefore, the number of repetitive pulses of the oscillator 3 corresponding to the gate period of the gate signal also differs.

被検出物をセットし、前記パルス発生回路4から第1の
パルスが発生されると、第2のパルスが発生する迄の期
間にゲート回路5のゲート信号が所定期間「H」となり
、3人力NAND回路1の入力端子BにrHJ信号が印
加される。
When the object to be detected is set and the first pulse is generated from the pulse generating circuit 4, the gate signal of the gate circuit 5 becomes "H" for a predetermined period until the second pulse is generated, and the three-man power The rHJ signal is applied to the input terminal B of the NAND circuit 1.

従って、前記3人力NAND回路Iの入力端子B及びC
に「H」信号が印加された状態となるから、入力端子A
に「H」信号が入った時のみ前記3人力NAND回路7
は「L」信号を発生する。
Therefore, input terminals B and C of the three-person NAND circuit I
Since the “H” signal is applied to the input terminal A
The three-person NAND circuit 7 is activated only when the “H” signal is input to
generates an "L" signal.

その時、2人力NAND回路8の入力端子AにはrLJ
信号が印加され続けるので、入力端子Bにパルス発生回
路4の「H」もしくはrLJのどちらの出力信号が印加
されても2人力NAND回路8の出力端子CにはrHJ
信号が発生し続ける。
At that time, the input terminal A of the two-person NAND circuit 8 has rLJ.
Since the signal continues to be applied, no matter which output signal "H" or rLJ of the pulse generation circuit 4 is applied to the input terminal B, the output terminal C of the two-man power NAND circuit 8 receives rHJ.
The signal continues to occur.

その為OR回路9の出力端子Cには、該OR回路9の入
力端子Aにl’−HJ信号が印加された時のみrHJ信
号が発生し、該rHJ信号が印加される毎に計数器1は
歩進する。
Therefore, the rHJ signal is generated at the output terminal C of the OR circuit 9 only when the l'-HJ signal is applied to the input terminal A of the OR circuit 9, and each time the rHJ signal is applied, the counter 1 advances.

前記OR回路9の出力信号が「H」となる回数は、ゲー
ト回路5の出力信号がrHJである期間に前記発振器3
から発生するパルスの個数と等しい。
The number of times the output signal of the OR circuit 9 becomes "H" is the number of times the output signal of the oscillator 3 becomes "H" during the period when the output signal of the gate circuit 5 is rHJ.
is equal to the number of pulses generated from .

従って計数器1は被検出物の位置に応じた数を計数する
ことが出来、例えばテープレコーダの場合には、テープ
の残量に関係する数が計数される。
Therefore, the counter 1 can count a number depending on the position of the object to be detected. For example, in the case of a tape recorder, a number related to the remaining amount of tape is counted.

上述の如き計数はパルス発生回路4から切換信号発生回
路6に印加されるパルスが所定数(例えば4個)に達す
る迄繰り返し行なわれ、正確な値が計数される。
The above-mentioned counting is repeated until the number of pulses applied from the pulse generating circuit 4 to the switching signal generating circuit 6 reaches a predetermined number (for example, four), and an accurate value is counted.

初期値設定が完了すると、切換信号発生回路6の出力信
号が、内蔵する計数器の作用により自動的に「H」とな
り、信号選択回路2は第2状態のパルス計数状態となる
When the initial value setting is completed, the output signal of the switching signal generation circuit 6 automatically becomes "H" due to the action of the built-in counter, and the signal selection circuit 2 enters the second pulse counting state.

従ってインバータ10を介して3人力NAND回路7の
入力端子CにはrLJ信号が印加され、入力端子A及び
Bに印加される信号にかかわらず前記3人力NAND回
路Iはその出力端子りに「H」信号を導出する。
Therefore, the rLJ signal is applied to the input terminal C of the three-man power NAND circuit 7 via the inverter 10, and the three-man power NAND circuit I outputs "H" to its output terminal regardless of the signals applied to the input terminals A and B. ” Derive the signal.

一方、2人力NAND回路8の入力端子Aには前記切換
信号発生回路6から「H」信号が印加され続けるので、
パルス発生回路4からパルスが発生して入力端子Bに「
H」信号が印加される毎に前記入力NAND回路8の出
力端子CにrLJ信号が発生する。
On the other hand, since the "H" signal continues to be applied from the switching signal generation circuit 6 to the input terminal A of the two-man power NAND circuit 8,
A pulse is generated from the pulse generation circuit 4 and sent to the input terminal B.
An rLJ signal is generated at the output terminal C of the input NAND circuit 8 every time the "H" signal is applied.

従って、OR回路9の入力端子AにrHJ信号が印加さ
れ続け、入力端子Bにパルス発生回路4の出力パルスが
発生する毎にrLJ信号が印加されるので、前記OR回
路9の出力端子Cにはパルス発生回路4の出力パルスが
発生する毎にrHJ信号が発生し、計数器1に印加され
て歩進が行なわれる。
Therefore, the rHJ signal continues to be applied to the input terminal A of the OR circuit 9, and the rLJ signal is applied to the input terminal B every time an output pulse of the pulse generation circuit 4 is generated. An rHJ signal is generated every time an output pulse of the pulse generating circuit 4 is generated, and is applied to the counter 1 to perform increment.

その為、前記計数器1は被検出物の動きに伴って先に計
数された初期値にパルスの発生毎に発生する信号を加算
もしくは減算する計数を行う。
Therefore, the counter 1 performs counting by adding or subtracting a signal generated every time a pulse is generated to an initial value counted previously in accordance with the movement of the object to be detected.

以上述べた如く、計数器1の入力信号は、初期値設定状
態、パルス計数状態ともに、本発生に係る信号選択回路
2を用いることにより、同一種類の信号に変換出来るの
で、前記計数回路1を共用することが出来、計数が簡単
に行い得るという利点を有する。
As described above, the input signal of the counter 1 can be converted into the same type of signal in both the initial value setting state and the pulse counting state by using the signal selection circuit 2 related to this generation. It has the advantage that it can be shared and counting can be done easily.

尚実施例においては、テープレコーダの場合を例として
いるが、それに限定されるものではなく、異る2つの信
号を計数する様々な場合に本発明は有効である。
In the embodiment, the case of a tape recorder is taken as an example, but the invention is not limited thereto, and the present invention is effective in various cases where two different signals are counted.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例を示す回路図である。 主な図番の説明、1・・・・・・計数器、l・・・・・
・信号選択回路、3・・・・・・発振器、4・・・・・
・パルス発生回路、5・・・・・・ゲート回路、6・・
・・・・切換信号発生回路、7・・・・・・3人力NA
ND回路、8・・・・・・2人力NAND回路、9・・
・・・・2人力OR回路、10・・・・・・インバータ
The figure is a circuit diagram showing one embodiment of the present invention. Explanation of main figure numbers, 1... Counter, l...
・Signal selection circuit, 3...Oscillator, 4...
・Pulse generation circuit, 5...Gate circuit, 6...
...Switching signal generation circuit, 7...3 manual NA
ND circuit, 8...2-manpower NAND circuit, 9...
...2-person OR circuit, 10...inverter.

Claims (1)

【特許請求の範囲】[Claims] 13人力NAND回路と、2人力NAND回路と、前記
3人力NAND回路の出力信号と2人力NAND回路の
出力信号とを2人力とし、一方入力がrLJであるとき
出力rHJを、かつ両人力が「H」となるとき出力「L
」を発生する論理回路とから成り、前記2人力NAND
回路の第1入力端子及び前記3人力NAND回路の第1
入力端子には、第1状態(「L」もしくは「H」)ある
いは第2状態(「H」もしくは「L」)の信号を出力す
る切換信号発生回路の出力端子が、該出力端子に第1状
態の出力信号が出力されるとき前記2人力NAND回路
の第1入力端子が「L」、前記3人力NAND回路の第
1入力端子がrHJとなり、前記出力端子に第2状態の
出力信号が出力されるとき前記2人力NAND回路の第
1入力端子が「H」、前記3人力NAND回路の第1入
力端子がrLJとなる様に接続さへ前記2人力NAND
回路の第2入力端子には、検出値に応じて周期の変化す
るパルスを発生するパルス発生回路の出力端子が接続さ
れ、前記3人力NAND回路の第2入力端子には、前記
パルス発生回路の出力に接続されその出力パルスの周期
に応じたゲート信号を作成するゲート回路の出力端子が
接続され、前記3人力NAND回路の第3入力端子には
、一定周期のパルス信号を出力する発振器の出力端子が
接続され、前記論理回路の出力端子には、計数器が接続
された構成であり、前記切換信号発生回路の出力信号が
第1状態のとき、ゲート信号の存在期間中、発振器から
のパルス信号を計数回路に印加し、前記切換信号発生回
路の出力信号が第2状態のとき、パルス発生回路の出力
信号を計数回路に印加する様にしたことを特徴とする信
号選択回路。
13 A human-powered NAND circuit, a two-human powered NAND circuit, the output signal of the three-human powered NAND circuit, and the output signal of the two-human powered NAND circuit are two-human powered, and when the input is rLJ, the output rHJ is When the output becomes “H”, the output “L”
” and a logic circuit that generates
a first input terminal of the circuit and a first input terminal of the three-way NAND circuit;
An output terminal of a switching signal generation circuit that outputs a signal in a first state ("L" or "H") or a second state ("H" or "L") is connected to the input terminal. When the state output signal is output, the first input terminal of the two-man power NAND circuit becomes "L", the first input terminal of the three-man power NAND circuit becomes rHJ, and the second state output signal is output to the output terminal. When the two-man power NAND circuit is connected, the first input terminal of the two-man power NAND circuit is "H" and the first input terminal of the three-man power NAND circuit is rLJ.
The second input terminal of the circuit is connected to the output terminal of a pulse generation circuit that generates a pulse whose period changes according to the detected value, and the second input terminal of the three-man power NAND circuit is connected to the output terminal of the pulse generation circuit. The output terminal of a gate circuit that is connected to the output and creates a gate signal according to the period of the output pulse is connected, and the third input terminal of the three-man power NAND circuit is connected to the output terminal of an oscillator that outputs a pulse signal of a constant period. and a counter is connected to the output terminal of the logic circuit, and when the output signal of the switching signal generation circuit is in a first state, a pulse from the oscillator is generated during the existence period of the gate signal. A signal selection circuit, characterized in that a signal is applied to a counting circuit, and when the output signal of the switching signal generation circuit is in a second state, the output signal of the pulse generation circuit is applied to the counting circuit.
JP9503076A 1976-08-06 1976-08-06 signal selection circuit Expired JPS5850396B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9503076A JPS5850396B2 (en) 1976-08-06 1976-08-06 signal selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9503076A JPS5850396B2 (en) 1976-08-06 1976-08-06 signal selection circuit

Publications (2)

Publication Number Publication Date
JPS5319855A JPS5319855A (en) 1978-02-23
JPS5850396B2 true JPS5850396B2 (en) 1983-11-10

Family

ID=14126683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9503076A Expired JPS5850396B2 (en) 1976-08-06 1976-08-06 signal selection circuit

Country Status (1)

Country Link
JP (1) JPS5850396B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215594Y2 (en) * 1983-10-04 1987-04-20
JPS6215593Y2 (en) * 1983-10-04 1987-04-20
JPS6215592Y2 (en) * 1983-10-04 1987-04-20

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215594Y2 (en) * 1983-10-04 1987-04-20
JPS6215593Y2 (en) * 1983-10-04 1987-04-20
JPS6215592Y2 (en) * 1983-10-04 1987-04-20

Also Published As

Publication number Publication date
JPS5319855A (en) 1978-02-23

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