JPS6032280B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, particularly SOS (Silicon
The present invention relates to a synchronous static memory device using MOS transistors with an onSaphire structure.

A static type memory device in which memory cells are constructed from flip-flops has a configuration as shown in FIG. In the figure, MC is a 1-bit memory cell, and in this example, p-channel MOSFETQ and n-channel MOSFET
C-MOS consisting of OSFETQ2, and p channel M
A flip-flop is constructed by cross-connecting C-MOS2 consisting of an OSFETQ3 and an n-channel MOSFETQ4.

This memory cell MC is an n-channel M that becomes a gate circuit.
It is connected to bit lines B, , B via OSFETs Q5 and Q6. This FETQ5 is controlled on/off by a signal RD from a row decoder. Bit lines B and B2 are selected by n-channel MOSFETs Q7 and Q that receive signal CD from the column decoder, and are connected to output amplifiers A, . In a memory device having such a configuration, B, , B2 are precharged to a constant potential before the memory cell MC is exposed.

In the example of FIG. 1, the precharge FETs Q to Q are turned on at the H level of the inverted signal CE of the chip enable signal, and the bit line B divided by FETs Q7 and Q8 is turned on.
, B2 are precharged with the power supply Vcc. The precharged bit line voltage Vb is equal to the power supply voltage V
q, set the threshold voltage of FETQ9 to Q,2 to V
As TH, Vb=Vcc-VTH, but this voltage V
TH is the relationship between the substrate bias voltage (substrate bias voltage) Vsub and the source of the FET,
It is expressed as VTH (V fence).

FETQ~Q,. Since the substrate of is normally connected to ground, the substrate bias voltage Vsub is equal to the bit line voltage Vb. Voltage Vb is ETQ9~Q, . It is also the source potential Vs of . In other words, Vb=VSniVCC-V
TH(VSub)...'・}. To give a numerical example, when the substrate concentration is 1.4×1 and 6 cm-3 and the gate oxide thickness is 730A, VTH (Vsub=0) is 0.95V, but if the substrate is grounded and Vsub=Vs, VT
When H increases and Vcc=4.4V, the bit lines B and B2 become approximately 2V. That is, VTH in this case is approximately 2.4V, and the bit line is precharged to a level slightly lower than half of the power supply voltage.・The above is a case where transistors with a normal bulk structure and a sufficiently thick semiconductor layer (substrate or epitaxial layer stacked on top of the substrate) are used, but when these are constructed with SOS-MOSFETs, gate oxidation Since the underlying semiconductor layer is thin, the entire semiconductor layer becomes a depletion layer at the threshold voltage.
VTH stops changing with Vsub.

Therefore, when using SOS-MOSFET, if bit lines B, & are precharged under the same conditions as above,
The bit line voltage Vb is VCC-VTH (VSu
b co.

)=3.45V becomes.

Generally, the access time of a RAM (random access memory) is such that the level of bit lines B and B2 is
Since it is defined by the longer time until it changes to either the "L" level or the "H" level depending on the storage state of C, as in this example, "H" = 4.4V, " L”=0
．． When the precharged bit line voltage Vb is 3.45V in the case of 4V, the memory cell MC becomes “L”.
The read time in this state becomes longer, and the access time ends up getting worse. In such a memory, it is preferable for the bit line Vb to be set to an intermediate value between the H level and the L level, or slightly biased toward the L level side, in order to minimize access time. The present invention has been made in view of the above points, and includes a synchronous static memory device formed of MOS transistors having an SOS structure, which includes a series connection circuit of a plurality of transistors that are turned on by an inverted signal of a chip enable signal. The present invention provides a semiconductor memory device in which access time is improved by connecting a bit line to a precharge power supply via a precharge power supply. An embodiment of the present invention will be described below with reference to FIG.

The main difference between this embodiment and FIG. 1 is that the MOSFETQ
n-channel MOS between 9~Q, 2 and the power supply.
FETQ9~Q. 2 are connected in series. These FETs Q9 to Q', 2 are also on/off controlled by the inverted signal CE of the chip enable signal at the same time as Q9 to Q, 2.
Note that all FETs in this example have an SOS mechanism. Since FETQ'9 has the same V... as FETQ9, these FETQs are turned on simultaneously by signal CE.
, bit line B by the power supply VQ through the Q'9 pair,
The precharge potential Vb of Vb-VCC-2・VTH(
VSubni.

)=2.5V. This value is “H” = 4.4 “L” =
Since it is close to the intermediate value 2.0 of 0.4, bit line B, (
The portion up to Q7) is precharged to a desirable voltage in order to reduce the access time. This means that
FETQ,o,Q',. vs. FETQ, . ,Q′,. The same applies to the pair of FETs Q, 2, Q', 2, and the rest of the bit line B and all of the bit line B5 are precharged to 2.5V at the same time. In addition, in the example, 2
The case where a bit line is precharged using an SOS-MOSFET in a step value array configuration has been illustrated, but considering the VTH value of the single MOSFET and the value of the power supply voltage V,
It is also possible to precharge three or more stages of SOS-MOSFETs connected in series. With the semiconductor memory device of the present invention described above, when configuring a synchronous static memory device using SOS-MOSFETs, the bit line (or digit line), which is the information transmission path of the memory cell, can be precharged to an optimal value. access time can be improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional synchronous static memory device, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. MC...Memory cell, B, . B2... Bit line, Q ~ Q, 2, Q also ~ Q', 2... MO for pre-charge
SFET. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a synchronous static memory device formed of MOS transistors with an SOS structure, the bit line is connected to a precharge power supply through a series connection circuit of several transistors that are turned on by an inverted signal of a chip enable signal. A semiconductor memory device characterized by: