JPH10223776A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is small in number of signal lines and causes no data disturbance even if a gate voltage which drives a transistor is kept low enough. SOLUTION: Data are given to a write data node 5n, a drive voltage -Vp is applied to a word node 7n, a write MOS transistor 6 is turned on, data are written in the gate G3 of a storage MOS transistor 3, and the storage MOS transistor 3 is turned on or off corresponding to the above data. When data are read out, a drive voltage Vn is applied to the word node 7n to turn a read- out MOS transistor 4 on. At this point, when the storage MOS transistor 3 is turned on corresponding to data inputted into the gate G3 , a reference potential VDD of a reference potential node 1n is fed to a read-out data node 2n . Or, when the storage MOS transistor 3 is turned off corresponding to data, a reference potential VDD is not supplied to the read-out data node 2n .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device suitable for high integration and high speed operation.

[0002]

2. Description of the Related Art This type of semiconductor memory device includes a large number of memory cells, each of which is a unit for storing information.
One example of this memory cell is shown in FIG.
37).

In the memory cell shown in FIG. 8, data (1 or 0) is supplied to a write data signal line 101, and a write transistor 103 is turned on through a write word signal line 102. Is written to the storage capacitor 104 via the write transistor 103, and the storage transistor 105 is turned on or off according to this data.

To read data written in the storage capacitor 104, a write data signal line 101
Are grounded, the read data signal line 106 is charged to a high potential, and the read transistor 108 is turned on through the read word signal line 107. At this time, if the storage transistor 105 is turned on in accordance with the data of the storage capacitor 104, the charge of the read data signal line 106 is discharged to the write data signal line 101 via the storage transistor 105 and the read transistor 108, This read data signal line 106
Potential drops. If the storage transistor 105 is turned off in accordance with data, the charge of the read data signal line 106 is not discharged, and the high potential of the read data signal line 106 is maintained. Therefore, when the read transistor 108 is turned on and the potential of the read data signal line 106 is detected, the storage capacitor 104
Can be read.

FIG. 9 shows another example of a conventional memory cell (see Japanese Patent Application Laid-Open No. 6-151759). In this memory cell, the threshold value Vth2 of the second transistor 111
The threshold value Vth3 of the third transistor 112 is set higher than that of the third transistor 112 (Vth2 <Vth3).
By setting the voltage Vo to Vth2 <Vo <Vth3 to turn on only the second transistor 111, or by setting this voltage Vo to Vth2 <Vth3 <Vo,
The second and third transistors 111 and 112 are both turned on.

Data (1 or 0) is transferred to data node 114
And the voltage Vo of the word node 113 is set to Vth2 <V
By setting th3 <Vo, the second and third transistors 11
When both 1 and 112 are turned on, this data is written to the gate of the first transistor 115 via the second and third transistors 111 and 112, and the first transistor 115 is turned on or off according to this data.

To read the data at the gate of the first transistor 115, only the second transistor 111 is turned on by setting the voltage Vo at the word node 113 to Vth2 <Vo <Vth3. At this time, since the first transistor 115 is turned on or off according to the data, the voltage VDD of the power supply node 116 becomes the first and second voltages.
Data node 11 via transistors 115 and 111
4 or not. Therefore, if the voltage of data node 114 is detected, data has been read.

FIG. 10 shows another example of a conventional memory cell (see Japanese Patent Application Laid-Open No. 7-45716). Here, the threshold value Vth21 of the write transistor 121 is higher than the threshold value Vth22 of the read transistor 122 (Vth21> Vth22), and the voltage Vo of the word signal line 123 is set to Vth22 <Vo <Vth21. ,
By turning on only the read transistor 122 or setting this voltage Vo to Vth22 <Vth21 <Vo, both the transistors 121 and 122 are turned on.

The data (1 or 0) is transmitted to the data signal line 124.
And the voltage Vo of the word signal line 123 is Vth2 <V
When th3 <Vo is set and each of the transistors 121 and 122 is turned on, this data is written to the storage capacitor 125 via the write transistor 121, and
The amplification transistor 126 is turned on or off according to this data.

In order to read the data of the storage capacitor 125, the voltage Vo of the word signal line 123 is set to Vth2 <V
By setting o <Vth3, only the read transistor 122 is turned on. At this time, since the amplification transistor 126 is turned on or off according to the data, the voltage VDD of the power supply node 127 is
26 and the data signal line 124 via the read transistor 122 or not.
Therefore, if the voltage of the data signal line 124 is detected, the data has been read.

[0011]

However, in the conventional memory cell of FIG. 8, the write data signal lines 101,
Write word signal line 102, read data signal line 1
06 and the read word signal line 107, which required four signal lines, and the number of signal lines in the storage device as a whole became enormous.

Further, in the conventional memory cell shown in FIGS. 9 and 10, although the number of signal lines is reduced, since two high and low thresholds having the same polarity are used, the transistor having the lower threshold is used. When only driving is performed, the gate voltage between these two thresholds must be accurately set, and when the drive voltage of each transistor is reduced, the range between these two thresholds is reduced. In addition, it is difficult to supply an appropriate gate voltage, and there is a problem that each transistor is likely to malfunction and data disturbance is likely to occur.

An object of the present invention is to solve such a problem of the prior art. Even if the number of signal lines is small and the gate voltage for driving the transistor is sufficiently reduced, the data disturbance may occur. It is an object of the present invention to provide a semiconductor memory device which does not cause the problem.

[0014]

In order to solve the above problems, in a semiconductor memory device according to the present invention, a storage switching element and a read switching element are connected in series between a reference potential and a read data node, and inserted. A write switching element that operates complementarily to the read switching element is inserted between the write data node and the gate of the storage switching element, and the gates of the read switching element and the write switching element are connected together to the word node. Depending on the signal
The read switching element and the write switching element are operated complementarily.

Such a configuration is provided for each memory cell of the semiconductor memory device. Here, the read switching element and the write switching element operate complementarily. That is, in response to the positive voltage and the negative voltage of the word node, when one of the read switching element and the write switching element is on, the other is off, and when one is off, the other is on.

When writing data, the read switching element is turned off, the write switching element is turned on, and the data is supplied to the write data node. The data at the write data node is transmitted to the gate of the storage switching element via the write switching element, and is written to this gate. The storage switching element is turned on or off according to this data.

To read data from the gate of the storage switching element, the read switching element is turned on and the write switching element is turned off. At this time, if the storage switching element is turned on according to the data, the reference potential is supplied to the read data node via the storage switching element and the read switching element, and the storage switching element is turned off according to the data. If so, the reference potential is not supplied to the read data node. If the potential of the read data node is detected, the data has been read.

As described above, the read switching element and the write switching element operate complementarily in response to the positive voltage and the negative voltage. For example, the read switching element is turned on when the threshold voltage of the positive voltage is equal to or higher than the threshold value Vthr, and the write switching element is turned on when the threshold voltage of the negative voltage is −V
Turns on at thw or less. Therefore, the drive voltage of the read switching element is set to be equal to or higher than the threshold value Vthr, and the drive voltage of the write switching element is set to -Vthw.
The following can be set. Therefore, it is easy to set these drive voltages, and even if these drive voltages vary, it is unlikely that these switching elements will malfunction.

Although three signal lines must be connected to the read data node, the write data node, and the word node, the reference potential can be shared among many memory cells. , FIG.
As compared with the conventional memory cell, the number of signal lines in the entire storage device can be reduced.

Further, since the read data node and the write data node are used alternately, these nodes can be shared, and in this case, the number of signal lines can be further reduced.

On the other hand, the storage switching element, read switching element, and write switching element are S
If the switching element is formed on an OI structure or each switching element is formed as a thin film transistor, the size of the memory cell in the semiconductor memory device can be reduced, and the integration density can be sufficiently improved.

[0022]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows, as an embodiment of the semiconductor memory device of the present invention, one of a large number of memory cells constituting the semiconductor memory device.

In FIG. 1, an N-channel storage MOS is provided between a reference potential node 1n and a read data node 2n.
The transistor 3 and the N-channel read MOS transistor 4 are connected in series and inserted. The reference potential node 1n is on the reference potential line 1, and supplies the reference potential VDD to the reference potential node 1n and the reference potential line 1. The read data node 2n is on the read data signal line 2, and reads data from the read data node 2n and the read data signal line 2.

The write data node 5n and the storage M
A P-channel write MOS transistor 6 is inserted between the gate G3 of the OS transistor 3. The write data node 5n is on the write data signal line 5, and supplies data to the write data node 5n and the write data signal line 5.

Further, the gates G4 and G6 of the read MOS transistor 4 and the write MOS transistor 6 are both connected to the word node 7n. Word node 7n
Is provided on the word signal line 7 and supplies one of a negative voltage and a positive voltage to the word node 7n and the word signal line 7.

Since the read MOS transistor 4 is an N channel and has a positive threshold voltage Vth4, when a drive voltage Vn higher than the threshold Vth4 is applied to the gate, the transistor 4 is turned on. . For example,
When 5 V is set as the reference potential VDD of the reference potential node 1n, the threshold V
When th4 is set to about 0.6 V to 0.7 V and 3 V is set as the reference potential VDD of the reference potential node 1n,
The threshold value Vth4 of the read MOS transistor 4 is set to 0.5
Since the voltage is set to about V, the drive voltage Vn that is equal to or higher than the threshold value Vth4 is set.

The write MOS transistor 6 is
The transistor 6 is turned on when a drive voltage -Vp equal to or less than the threshold value -Vth6 is applied to the gate because the threshold voltage -Vth6 is a negative voltage. For example, the lower potential of each of the potentials indicating the data (1 or 0) of the write data node 5n is -5V
Is set, the threshold value Vth6 of the write MOS transistor 6 is set to about -0.6 V to -0.7 V. When the lower potential is set to -3 V, the threshold voltage Vth6 of the write MOS transistor 6 is set to Since the threshold value Vth6 is set to about -0.3 V, the driving voltage -Vp below these threshold values Vth6 is set.

Here, comparing the threshold value Vth4 and the drive voltage Vn of the read MOS transistor 4 with the threshold value -Vth6 and the drive voltage -Vp of the write MOS transistor 6, the drive voltage Vn> threshold value Vth4> threshold. Value-Vth6
> Drive voltage-Vp.

Therefore, the gates G4, G4 of the read MOS transistor 4 and the write MOS transistor 6
When either the drive voltage Vn or the drive voltage -Vp is selectively applied to the word node 7n connected to G6, these transistors 4 and 6 are turned on and off complementarily. In addition, since the driving voltage Vn and the driving voltage −Vp have mutually opposite polarities, the setting range of these driving voltages is wide, and it is difficult for the transistors 4 and 6 to malfunction due to variations in these driving voltages.

In such a configuration, when data is written, the data is applied to the write data node 5n, and a driving voltage -Vp (<threshold value Vth6) is applied to the word node 7n, thereby causing the read MOS transistor 4 to operate. At the same time, the write MOS transistor 6 is turned on, the data at the write data node 5n is applied to the gate G3 of the storage MOS transistor 3 via the write MOS transistor 6, and the data is written to the gate G3. The storage MOS transistor 3 is turned on or off according to.

When reading data, a drive voltage Vn (> threshold value Vth4) is applied to the word node 7n to turn on the read MOS transistor 4 and turn off the write MOS transistor 6. At this time, if the storage MOS transistor 3 is turned on in accordance with the data of the gate G3, the reference potential VDD of the reference potential node 1n becomes the storage MOS transistor 3 and the read M
Read data node 2n via OS transistor 4
Supplied to If the storage MOS transistor 3 is turned off according to the data of the gate G3, the connection between the reference potential node 1n and the read data node 2n is cut off,
This reference potential VDD is not supplied to the read data node 2n. Therefore, the drive voltage Vn (> threshold value Vth4) is applied to the word node 7n to read M
If the potential of the read data node 2n is detected when the OS transistor 4 is turned on, the data of the gate G3 of the storage MOS transistor 3 has been read.

The operation of such a memory cell is summarized as follows.
Table 1 below.

[0034]

[Table 1]

As described above, in the device according to the embodiment, the read MOS is read in response to the drive voltages -Vp, Vn having mutually opposite polarities.
The transistor 4 and the write MOS transistor 6 are turned on and off complementarily. These drive voltages −Vp,
Vn has a wide setting range and can be easily set. In addition, malfunctions of the transistors 4 and 6 due to variations in the levels of these drive voltages are unlikely to occur, and data disturbance is suppressed.

Further, when the device of this embodiment is compared with the conventional memory cell of FIG. 8, the number of signal lines in the entire storage device can be reduced. Alternatively, since the read data node 2n and the write data node 5n are used alternately, these nodes can be shared, and in this case, the number of signal lines can be further reduced.

FIG. 2 is a circuit diagram of the semiconductor memory device shown in FIG.
FIG. 3 is a plan view showing one memory cell, and FIG. 3 is a cross-sectional view along AA in FIG.

As apparent from FIGS. 2 and 3, this semiconductor memory device has an SOI structure. The method for forming the SOI structure is not particularly limited, and examples thereof include an ion implantation method, a substrate bonding method (polishing one silicon substrate into a thin film after bonding a silicon substrate), and the like.

Here, the insulating layer 12 is formed on the Si substrate 11.
And a semiconductor layer 13 including a source and a drain of each of the MOS transistors 3, 4, and 6 is formed. A word signal line 7 made of polysilicon (on each of the MOS transistors 4 and 4) is formed on the semiconductor layer 13 via a gate oxide film 14. 6 gates G4, G6
And a short-circuit line 15 also made of polysilicon.
(Including the gate G3 of the MOS transistor 3), a salicide structure 16 is formed thereafter, a short-circuit line 17 is formed, and the gate G of the storage MOS transistor 3 is formed.
3 is written through the short-circuit line 17 to the write MOS transistor 6
Connected to the drain. Storage MOS transistor 3
Are connected to the reference potential signal line 1.

Then, after laminating the interlayer insulating layer 18 and forming the respective contact holes 19, 19, the read data signal line 2 and the write data signal line 5 are formed, and the read data signal line 2 is connected to the contact hole 19. The write data signal line 5 is connected to the source of the write transistor 6 through the contact hole 19 while being connected to the drain of the read MOS transistor 4 through the write transistor 6.

By applying such an SOI structure, the size of the memory cell can be reduced and the integration density thereof can be increased.

FIG. 4 shows a modification of the semiconductor memory device of FIG. Here, the two memory cells 21 and 22 are arranged vertically symmetrically, the read data signal line 2 of each memory cell 21 and 22 is shared, and each memory cell 21 and 22 is shared.
The write data signal lines 5 for 1 and 22 are shared.

FIG. 5 is a plan view showing each of the memory cells 21 and 22 of FIG. 4, FIG. 6 is a sectional view taken along the line BB of FIG.
FIG. 6 is a sectional view taken along the line CC of FIG. 5.

In this semiconductor device, each MOS transistor 3, 4, 6 of each memory cell 21, 22 is formed as a thin film transistor. That is, a semiconductor layer 24 including the source and the drain of each of the MOS transistors 3 and 4 is formed on the surface of the substrate 23, and a short-circuit line 25 made of polysilicon (the source and the drain of the two MOS transistors 6 and the two And two word signal lines 7 (including the gate G4 of the two MOS transistors 4 and the gate G6 of the two MOS transistors 6) also formed of polysilicon. The sources of the read MOS transistors 4 and 4 and the drains of the storage MOS transistors 3 and 3 are shared.

Then, after laminating the interlayer insulating layer 26 and forming the contact holes 27 and 28, the read data signal line 2 and the write data signal line 5 are formed, and the read data signal line 2 is connected to the contact hole 28. The write data signal line 5 is connected to the sources of the write transistors 6 and 6 via the contact holes 27, respectively.

By applying such a thin film transistor, the integration density of memory cells can be increased.

The present invention is not limited to the above embodiment, but can be variously modified. For example, the type of each channel of the storage MOS transistor 3 and the write MOS transistor 6 may be interchanged. Further, the reference potential VDD can be appropriately set within a range including the ground potential.

[0048]

As described above, according to the present invention,
With the complementary operation of the read switching element and the write switching element, data is written or data is read. For this reason, for example, the drive voltage of the read switching element may be set to be equal to or higher than the positive threshold value, and the drive voltage of the write switching element may be set to be equal to or lower than the negative threshold value. Therefore, it is difficult for these switching elements to malfunction.

Although three signal lines must be connected to the read data node, the write data node, and the word node, the reference potential can be shared among many memory cells. , FIG.
As compared with the conventional memory cell, the number of signal lines in the entire storage device can be reduced.

On the other hand, the storage switching element, the read switching element, and the write switching element are S
If the switching element is formed on an OI structure or each switching element is formed as a thin film transistor, the size of the memory cell in the semiconductor memory device can be reduced, and the integration density can be sufficiently improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a memory cell in an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a plan view showing a memory cell in the semiconductor memory device of FIG. 1;

FIG. 3 is a sectional view taken along the line AA in FIG. 2;

FIG. 4 is a circuit diagram showing a modification of the semiconductor memory device of FIG. 1;

FIG. 5 is a plan view showing each memory cell of FIG. 4;

FIG. 6 is a sectional view taken along the line BB of FIG. 5;

FIG. 7 is a sectional view taken along the line CC of FIG. 5;

FIG. 8 is a circuit diagram illustrating an example of a memory cell in a conventional semiconductor device.

FIG. 9 is a circuit diagram showing another example of a memory cell in a conventional semiconductor device.

FIG. 10 is a circuit diagram showing another example of a memory cell in a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference potential signal line 1n Reference potential node 2 Read data signal line 2n Read data node 3 Storage MOS transistor 4 Read MOS transistor 5 Write data signal line 5n Write data node 6 Write MOS transistor 7 Word signal line 7n Word node 11 Si substrate 12 Insulating layer 13, 24 Semiconductor layer 14 Gate oxide film 15, 17, 25 Short-circuit line 16 Salicide structure 18, 26 Interlayer insulating layer 19, 27, 28 Contact hole 21, 22 Memory cell 23 Substrate

Claims (3)

[Claims] 1. A method according to claim 1, further comprising the step of:
A storage switching element and a read switching element are connected in series and inserted. A write switching element that operates complementarily to the read switching element is inserted between the write data node and the gate of the storage switching element. A semiconductor memory device in which each gate of an element is connected together to a word node, and a read switching element and a write switching element are operated complementarily by a signal of the word node. 2. The storage switching element, the read switching element, and the write switching element, each of which includes an SO
2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is formed on an I structure. 3. The semiconductor memory device according to claim 1, wherein the storage switching element, the read switching element, and the write switching element are formed as a thin film transistor.