JP2006324683A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leakage current between the source and the drain in a MOS transistor of a semiconductor memory. <P>SOLUTION: DRAMs are formed on an SOI substrate. The body regions of the transistors Qn1, Qn2, Qp1, Qp2, Qpc, Qe, Qb, Qd, Qm, Qio in a sense amplifier 20, a precharger circuit 23, bit line selector circuits 26A and 26B, a memory cell 27, a dummy cell 28, and a column selector circuit 29 for DRAMs are electrically fixed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) formed on an SOI (Silicon On Insulator) substrate.

  In general, semiconductor memory devices are roughly classified into a volatile memory represented by a RAM and a non-volatile memory represented by a ROM. Volatile memory is further divided into DRAM and static random access memory (SRAM). Nonvolatile memory includes mask ROM, EPROM, flash memory, EEPROM, fuse ROM, and the like.

  In a DRAM, data is stored by storing electric charges in a capacitor of a memory cell, so a refresh operation is necessary. However, since the configuration of the memory cell is simple, a DRAM having a large storage capacity is reduced. Can be manufactured at cost.

  However, since DRAM stores data by accumulating charge in the capacitor, α particles emitted from the package, wiring material, etc. change the amount of charge accumulated in the capacitor, thereby inverting the data. There was a so-called soft error problem.

  Further, DRAMs are desired to be further highly integrated, and in the future, it is expected that DRAMs having a large storage capacity such as 256 Mbits and 1 Gbits will be mass-produced. In order to increase the integration density of DRAMs, it is generally necessary to shorten the gate length. However, since the short channel effect becomes more prominent as the gate length is shortened, there is a limit to shortening the gate length.

  Recently, a semiconductor integrated circuit (LSI) in which a semiconductor element such as a transistor is formed on an SOI substrate in which an insulating layer is embedded in a semiconductor substrate has been developed.

  FIG. 92 is a plan view showing a configuration of a MOS transistor formed on an SOI substrate. 93 is a cross-sectional view of the MOS transistor shown in FIG. 92 taken along line 93-93. 94 is a cross-sectional view of the MOS transistor shown in FIG. 92 cut along line 94-94.

  92 to 94, this MOS transistor includes an n + -type source region 1, an n + -type drain region 2, a p-type body region 3, and a gate electrode 4. Body region 3 is located between source region 1 and drain region 2. When a predetermined potential is applied to the gate electrode 4, a channel is formed in the body region 3.

  This MOS transistor is completely surrounded by the LOCOS oxide film 5 and thereby separated from adjacent elements. The MOS transistor is formed on the SOI substrate 6. The SOI substrate 6 comprises a silicon substrate 7, a buried oxide layer 8 made of SiO2, and an SOI active layer 9. Source region 1, drain region 2 and body region 3 are formed in this SOI active layer 9.

  Since body region 3 is surrounded by LOCOS oxide film 5 and isolated from silicon substrate 7 by buried oxide layer 8, it is in an electrically floating state. When the body region 3 is in a floating state, the breakdown voltage between the source and the drain is reduced to about 3 V by a parasitic bipolar operation, or a leak current is likely to flow between the source and the drain. In addition, when the body region 3 is in a floating state, a kink is generated, and thereby the drain current Id-drain voltage Vd characteristic is disturbed, and the transistor does not operate stably.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor memory device formed on an SOI substrate.

  Another object of the present invention is to provide a DRAM in which soft errors hardly occur.

  Still another object of the present invention is to provide a DRAM having a larger storage capacity.

  Still another object of the present invention is to further increase the data retention time of the memory cell.

  Still another object of the present invention is to increase the breakdown voltage between the source and drain of a MOS transistor in a semiconductor memory device.

  Still another object of the present invention is to reduce the leakage current between the source and drain of a MOS transistor in a semiconductor memory device.

  Still another object of the present invention is to stably operate a MOS transistor in a semiconductor memory device.

  Still another object of the present invention is to minimize an increase in layout area.

  The semiconductor memory device according to claim 1 includes a plurality of word lines arranged along the row direction, a plurality of bit line pairs arranged along the column direction, a plurality of word lines and a plurality of bit line pairs. A plurality of memory cells provided corresponding to any of the intersections, each including storage means for storing data and a first MOS transistor connected between the storage means and one bit line of the corresponding bit line pair Row selecting means for selecting one of the plurality of word lines, column selecting means for selecting one of the plurality of bit line pairs, and a plurality of bit line pairs. Each of which includes a third MOS transistor, a plurality of precharge means for precharging the corresponding bit line pair to a predetermined potential, and a plurality of bit line pairs. But second And a plurality of sense amplifiers for amplifying a potential difference between corresponding bit line pairs, the plurality of word lines, the plurality of bit line pairs, and the plurality of memory cells. The row selection unit, the column selection unit, the plurality of precharge units, and the plurality of sense amplifier units are formed on the SOI substrate. Each of the plurality of first to fourth MOS transistors has a source region, a drain region, and a body region located between the source region and the drain region. Of the plurality of first to fourth MOS transistors, the body region of the MOS transistor having the source region or the drain region connected to any one of the plurality of bit line pairs is electrically fixed.

  According to a second aspect of the semiconductor memory device, in addition to the configuration of the first aspect, the MOS transistor having the fixed body region is the first MOS transistor.

  According to a third aspect of the present invention, in addition to the configuration of the first aspect, the MOS transistor having the fixed body region is the second MOS transistor.

  According to a fourth aspect of the present invention, in addition to the configuration of the first aspect, the MOS transistor having the fixed body region is the third MOS transistor.

  According to a fifth aspect of the present invention, in addition to the configuration of the first aspect, the MOS transistor having the fixed body region is the fourth MOS transistor.

  The semiconductor memory device according to claim 6 is provided with a plurality of bit line pairs, each corresponding to two bit line pairs of the plurality of bit line pairs, and one of the corresponding two bit line pairs. A plurality of sense amplifier means for amplifying the potential difference between the bit line pairs and a plurality of MOSs provided corresponding to the plurality of bit line pairs, each connected between the corresponding bit line pair and the corresponding sense amplifier means A semiconductor memory device comprising a pair of transistors, wherein two bit line pairs are arranged on both sides of the corresponding sense amplifier means, and a plurality of bit line pairs, a plurality of sense amplifier means, and a plurality of MOS transistors A pair is formed on an SOI substrate. A body region located between a source region and a drain region of at least one MOS transistor of the plurality of MOS transistor pairs is electrically fixed.

  In the semiconductor memory device according to claim 1, since the body region of the MOS transistor connected to the bit line pair is fixed, the MOS transistor flows out of the bit line pair through the MOS transistor or to the bit line pair. Leakage current flowing through the is reduced. Further, since the body region of the MOS transistor of any one of the memory cell, the column selection means, the precharge means, and the sense amplifier means is fixed, the charge on the bit line does not leak through any of the MOS transistors. .

  In the semiconductor memory device according to the second aspect, in addition to the operation of the first aspect, the body region of the MOS transistor of the memory cell is fixed, so that the charge of the bit line leaks through the transistor of the memory cell. Absent.

  In the semiconductor memory device according to claim 3, in addition to the operation of claim 1, since the body region of the MOS transistor of the column selection means is fixed, the charge of the bit line does not leak through the transistor. .

  In the semiconductor memory device according to the fourth aspect, in addition to the operation of the first aspect, since the body region of the MOS transistor of the precharge means is fixed, the charge of the bit line does not leak through the transistor.

  In the semiconductor memory device according to claim 5, in addition to the operation of claim 1, since the body region of the MOS transistor of the sense amplifier means is fixed, the charge on the bit line does not leak through the transistor. .

  In the semiconductor memory device according to the sixth aspect, since the body region of the bit line selection MOS transistor in the so-called shared sense amplifier system is fixed, the charge on the bit line does not leak through the transistor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Example 1]
FIG. 2 is a block diagram showing the overall structure of the DRAM according to Embodiment 1 of the present invention. Referring to FIG. 2, DRAM 10 includes a memory cell array 11, a row decoder 12, a column decoder 13, a sense amplifier group 14, an input / output circuit 15, a row and column address buffer 16, and an input buffer 17. An output buffer 18 and a clock generation circuit 19.

  In the memory cell array 11, a plurality of word lines (not shown) are arranged along the row direction, a plurality of bit line pairs (not shown) are arranged along the column direction, and a plurality of memory cells (see FIG. (Not shown) are arranged at these intersections. In response to the row address signal supplied from the address buffer 16, the row decoder 12 selects and drives one of the plurality of word lines. The column decoder 13 selects one of a plurality of bit line pairs in response to the column address signal supplied from the address buffer 16. The sense amplifier group 14 includes a plurality of sense amplifiers. The plurality of sense amplifiers are provided corresponding to the plurality of bit line pairs. Each sense amplifier amplifies the potential difference between its corresponding bit line pair. The input / output circuit 15 supplies the potential of the bit line pair selected by the column decoder 13 to the output buffer 18. The output buffer 18 amplifies the supplied potential and outputs it as output data DQ1 to DQ4. The input buffer 17 amplifies input data DQ1 to DQ4 supplied from the outside. The input / output circuit 15 supplies the input data amplified in the input buffer 17 to the bit line pair selected by the column decoder 13. The address buffer 16 selectively supplies address signals A0 to A11 supplied from the outside to the row decoder 12 and the column decoder 13.

  FIG. 1 is a circuit diagram showing in detail a part of the memory cell array 11, the sense amplifier group 14 and the input / output circuit 15 shown in FIG. Referring to FIG. 1, in memory cell array 11, word lines WL1, WL2,... And bit line pairs BL0, / BL0, BL1, / BL1 are arranged crossing these word lines. Memory cells 27 are arranged at the intersections between the bit lines BL0, / BL0 and the word lines WL1, WL2, respectively.

  One sense amplifier 20 is arranged corresponding to two bit line pairs BL0, / BL0 and BL1, / BL1. The bit line pair BL0, / BL0 is connected to the sense amplifier 20 via the bit line selection circuit 26A, and the bit line pair BL1, / BL1 is connected to the sense amplifier 20 via the bit line selection circuit 26B. The bit line selection circuit 26A connects the bit line pair BL0, / BL0 to the sense amplifier 20 in response to the bit line selection signal BLI0, whereby the sense amplifier 20 amplifies the potential difference between the bit line pair BL0, / BL0. The bit line selection circuit 26B connects the bit line pair BL1, / BL1 to the sense amplifier 20 in response to the bit line selection signal BLI1, whereby the sense amplifier 20 amplifies the potential difference between the bit line pair BL1, / BL1. Therefore, in the first embodiment, a so-called shared sense amplifier system is adopted.

One bit line precharge circuit 23 is provided corresponding to the sense amplifier 20. The precharge circuit 23 has the bit line equalize signal BLEQ bit line pair in response to BL0, / BL0, BL1, precharges the / BL1 to a predetermined potential V _BL.

  One column selection circuit 29 is provided corresponding to one or a plurality of sense amplifiers 20. This column selection circuit 29 connects the bit line pair BL0, / BL0, BL1, / BL1 to the input / output line pair IO, / IO in response to a column selection signal CSL.

A drive line precharge circuit 22 is provided between the sense amplifier drive lines 21A and 21B for driving the sense amplifier 20. The precharge circuit 22 precharges the sense amplifier driving lines 21A and 21B to a predetermined potential V _BL in response to the equalization signal BLEQ. Sense amplifier drive line 21A is connected to the ground node via N channel MOS transistor Qs1 that is rendered conductive in response to control signal S0F. Sense amplifier drive line 21A is also connected to the ground node via N channel MOS transistor Qs2 which is rendered conductive in response to control signal S0N. Sense amplifier drive line 21B is connected to the power supply node via P channel MOS transistor Qs3 that is rendered conductive in response to control signal S0P.

  Dummy word lines DWL1 and DWL2 are arranged in parallel with word lines WL1 and WL2. Further, dummy cells 28 are arranged at the intersections of the dummy word lines DWL1, DWL2 and the bit lines BL0, / BL0, respectively. The dummy cell 28 cancels noise generated in the bit lines BL0 and / BL0 when the word lines WL1 and WL2 rise.

  Sense amplifier 20 includes N channel MOS transistors Qn1 and Qn2 connected in series between bit line pairs, and P channel MOS transistors Qp1 and Qp2 connected in series between bit line pairs. The gate electrodes of transistors Qn1 and Qp1 are both connected to bit lines / BL0 and / BL1, and the gate electrodes of transistors Qn2 and Qp2 are both connected to bit lines BL0 and BL1. The source electrodes of transistors Qn1 and Qn2 are both connected to sense amplifier drive line 21A, and the source electrodes of transistors Qp1 and Qp2 are both connected to sense amplifier drive line 21B.

  Each memory cell 27 includes an N-channel MOS transistor Qm that functions as a transfer gate, and a capacitor Cm that stores data. Transistor Qm has its gate electrode connected to corresponding word line WL1 or WL2, while its source / drain electrode is connected to corresponding bit line BL0 or / BL0. One electrode of capacitor Cm is connected to the other source / drain electrode of transistor Qm, and the other electrode is supplied with cell plate potential Vcp.

  Each dummy cell 28 includes an N-channel MOS transistor Qd and a capacitor Cd in substantially the same manner as the memory cell 27. Transistor Qd has its gate electrode connected to corresponding dummy word line DWL1 or DWL2, while its source / drain electrode is connected to corresponding bit line BL0 or / BL0. One electrode of the capacitor Cd is connected to the other source / drain electrode, and the cell electrode potential Vcp is applied to the other electrode.

  Bit line select circuit 26B includes two N-channel MOS transistors Qb that are rendered conductive in response to bit line select signal BLI0. Bit line select circuit 26B includes two N-channel MOS transistors Qb that are rendered conductive in response to bit line select signal BLI1.

  The bit line precharge circuit 23 includes an N channel MOS transistor Qe connected between the bit line pair and two N channel MOS transistors Qpc connected in series between the bit line pair. The gate electrodes of these transistors Qe and Qpc are both connected to the equalize line 24. Both source electrodes of the transistor Qpc are connected to the precharge line 25.

  Column selection circuit 29 is connected between bit lines BL0 and BL1 and input / output line IO, and is turned on in response to column selection signal CSL. N channel MOS transistor Qio, and bit lines / BL0 and / BL1 N channel MOS transistor Qio connected between input / output line / IO and rendered conductive in response to column select signal CSL is provided.

  The drive-dedicated precharge circuit 22 includes an N-channel MOS transistor Qse connected between the drive lines 21A and 21B and two N-channel MOS transistors Qsp connected in series between the drive lines 21A and 21B. The gate electrodes of these transistors Qse and Qsp are connected to the equalize line 24. Both source electrodes of the transistor Qsp are connected to the precharge line 25.

  Next, the operation of FIG. 1 will be described with reference to the timing chart shown in FIG. As shown in FIG. 3A, address signals A0-A11 are strobed in response to the fall of external row address strobe signal / RAS. When bit line pair BL0, / BL0 is selected according to the address signal, bit line selection signal BLI0 rises as shown in FIG. The bit line selection signal BLI1 is maintained at L (logic low). Therefore, bit line pair BL0, / BL0 is connected to sense amplifier 20.

As shown in FIG. 3F, since the bit line equalize signal BLEQ is at the H (logic high) level, the transistors Qpc of the bit line precharge circuit 23 are both in a conductive state. Therefore, precharge potential _VBL is applied to bit line pair BL0, / BL0. Further, since the transistor Qe of the bit line precharge circuit 23 is also conductive, the potentials of the bit line pair BL0, / BL0 are equal to each other. Here, since half the potential Vcc / 2 of the power supply potential as a precharge potential V _BL is applied, bit line pair BL0, / BL0 potential intermediate the potential of the H and L level as shown in FIG. 3 (j) It becomes.

  Since the H level equalize signal BLEQ is also applied to the gate electrodes of the transistors Qse and Qsp of the drive-dedicated precharge circuit 22, the sense amplifier drive lines 21A and 21B have the power supply potential as well as the bit line pair BL0 and / BL0. Precharged to half potential Vcc / 2.

Subsequently, when the word line WL1 rises as shown in FIG. 3B, the transistor Qd of the corresponding memory cell 27 becomes conductive, whereby the charge of the capacitor Cm is read to the bit line BL0. If L-level data in the memory cell 27 is stored, the potential of the bit line BL0, as shown in FIG. 3 (j) is slightly lower than the precharge potential V _BL. As a result, a potential difference is generated between the bit line pair BL0, / BL0.

  Subsequently, when the control signal S0F rises as shown in FIG. 3G, the transistor Qs1 becomes conductive, whereby the charge on the sense amplifier drive line 21A flows out to the ground node via the transistor Qs1. Therefore, the potential SAN of the sense amplifier drive line 21A starts to decrease toward the ground potential Vss.

  Subsequently, when the control signal S0N rises as shown in FIG. 3 (h), the transistor Qs2 becomes conductive, whereby the charge on the sense amplifier drive line 21A flows out to the ground node via the transistor Qs2. For this reason, the potential SAN of the sense amplifier drive line 21A further decreases toward the ground potential Vss.

  Subsequently, as shown in FIG. 3 (i), when the control signal S0P falls, the transistor Qs3 becomes conductive, whereby electric charge is supplied from the power supply node to the sense amplifier drive line 21B via the transistor Qs3. Therefore, the potential SAB of the sense amplifier drive line 21B gradually increases toward the power supply potential Vcc.

  As described above, the sense amplifier drive signal SAN gradually decreases toward the ground potential Vss, and the sense amplifier drive signal SAP gradually increases toward the power supply potential Vcc. Therefore, as shown in FIG. The sense amplifier 20 lowers the potential of the bit line BL0 to L level and raises the potential of the bit line / BL0 to H level. Therefore, the sense amplifier 20 latches complementary data corresponding to the data in the memory cell 27.

  Subsequently, when the column selection signal CSL rises, both transistors Qio of the column selection circuit 29 are turned on. Thereby, the potential of bit line BL0 is applied to input / output line IO via transistor Qio, and the potential of bit line / BL0 is applied to input / output line / IO via transistor Qio. Potentials appearing on the input / output lines IO and / IO are finally amplified by the output buffer 18 and further output as output data.

  Although the case where the bit line pair is precharged to Vcc / 2 has been described here, the bit line pair may be precharged to Vcc. In this case, the capacitance of the capacitor Cd in the dummy cell 28 needs to be different from that of the capacitor Cm in the memory cell 27. For example, the capacitance of the capacitor Cd may be halved with respect to the capacitor Cm.

  FIG. 4 is a timing chart when the bit line pair is precharged to Vcc. When the bit line equalize signal BLEQ is at the H level as shown in FIG. 4F, the bit line pair is precharged to the H level, that is, the power supply potential Vcc as shown in FIG. By raising DWL2 at the same time that the word line WL1 rises, a potential difference is generated in the bit line pair.

  When power supply levels are hierarchized, the internal power supply potential is generated by stepping down the external power supply potential, and the internal ground potential is generated by boosting the external ground potential. In this case, the sense amplifier drive signal SAN is gradually discharged from the precharge level toward the internal ground potential higher than the external ground potential, and the sense amplifier drive signal SAP is gradually decreased toward the internal power supply potential lower than the external power supply potential. To increase. Therefore, sense amplifier 20 raises the potential of one sense amplifier to the internal power supply potential and lowers the potential of the other bit line to the internal power supply potential.

  In sense amplifier 20 of the first embodiment, a constant ground potential Vss is applied to the body regions of N-channel MOS transistors Qn1 and Qn2, whereby the body region is electrically fixed. A constant power supply potential Vcc is applied to the body regions of P-channel MOS transistors Qp1 and Qp2, and the body regions are thereby electrically fixed.

  Therefore, kink does not occur in these transistors Qn1, Qn2, Qp1, and Qp2, and stable Id-Vd characteristics are obtained. Therefore, the sense amplifier 20 performs a stable analog operation.

  Further, since the body regions of these transistors Qn1, Qn2, Qp1, and Qp2 are fixed, the leakage current between the source and the drain is reduced. Therefore, the charges on the bit lines BL0, / BL0, BL1, / BL1 do not leak through these transistors Qn1, Qn2, Qp1, Qp2. Therefore, the potential difference generated between the bit line pair when data is read from memory cell 27 can be maintained sufficiently large.

  In memory cell 27 of the first embodiment, a constant ground potential Vss is applied to the body region of the N-channel MOS transistor, whereby the body region is electrically fixed. Therefore, the subthreshold characteristic is improved, and the leakage current approaches the physical limit value. Therefore, the electric charge leaking from the capacitor Cm through the transistor Qm is governed by the leakage at the PN junction. Further, in a transistor formed on a thin film SOI, at least a PN junction surface parallel to the SOI substrate does not exist. In addition, since the leakage current in the PN junction is proportional to the surface area of the PN junction, the data retention time becomes long. In dummy memory cell 28 as well as memory cell 27, a constant ground potential Vss is applied to the body region of N-channel MOS transistor Qd, whereby the body region is electrically fixed.

  A constant ground potential Vss is applied to the body regions of the N channel MOS transistors Qe and Qpc of the bit line precharge circuit 23 of the first embodiment, whereby the body region is electrically fixed. Therefore, the charge on the bit line does not leak through these transistors Qe and Qpc. Therefore, the read potential difference generated between the bit line pairs does not become small, and the potential difference is surely amplified by the sense amplifier.

  In the drive-dedicated precharge circuit 22 as well, like the bit line precharge circuit 23, a constant ground potential Vss is applied to the body regions of the transistors Qse and Qsp, thereby electrically fixing the body region. ing. A constant ground potential Vss is applied to the body regions of N channel MOS transistors Qs1 and Qs2, thereby electrically fixing the body region. A power supply potential Vcc is applied to the body region of P channel MOS transistor Qs3, whereby the body region is electrically fixed.

  In bit line selection circuits 26A and 26B of the first embodiment, a constant ground potential Vss is applied to the body region of N channel MOS transistor Qb, thereby electrically fixing the body region. Therefore, the charge on the bit line does not leak through these transistors Qb, so that the read potential difference is kept sufficiently large.

  In column selecting circuit 29 of the first embodiment, a constant ground potential Vss is applied to the body region of N channel MOS transistor Qio, and the body region is electrically fixed. Accordingly, the charge on the bit line does not leak through these transistors Qio, so that the read potential difference is kept sufficiently large. Therefore, accurate data is read to input / output lines IO and / IO through column selection circuit 29.

  FIG. 5 is a plan view showing a partial configuration of the sense amplifier 20 and the entire configuration of the precharge circuit 23 shown in FIG. 6 is a cross-sectional view of the sense amplifier 20 shown in FIG. 5 taken along line 6-6. In FIG. 5, only an N channel sense amplifier constituted by N channel MOS transistors Qn1 and Qn2 is shown.

  5 and 6, n + type source region 1 of transistor Qn1 is common with the source region of transistor Qn2. This source region 1 is connected via a contact hole CH to a sense amplifier drive line 21A to which a sense amplifier drive signal SAN is applied.

  The n + type drain region 2 of the transistor Qn1 is connected to the bit line BL1 through the contact hole CH. N + type drain region 2 of transistor Qn2 is connected to bit line / BL1 through contact hole CH. Gate electrode 4 of transistor Qn1 is connected to bit line / BL1 through contact hole CH. Gate electrode 4 of transistor Qn2 is connected to bit line BL1 through contact hole CH.

  A p + -type contact region 31 is formed in the p-type body region 3 of the transistor Qn1. The contact region 31 is connected to the body fixing line 30C through an intermediate layer 32 such as a polypad. A ground potential Vss is supplied to the body fixing line 30C. Therefore, a constant ground potential Vss is applied to the body region 3. A contact region 31 is also formed in the body region 3 of the transistor Qn2. Body region 3 of transistor Qn2 is connected to body fixing line 30B via contact region 31 and the intermediate layer. The ground potential Vss is also supplied to the body fixing line 30B. Therefore, the ground potential Vss is also applied to the body region 3 of the transistor Qn2.

  Referring to FIG. 6, first interlayer insulating film 33 is formed on gate electrode 4. A contact hole CH is opened at a predetermined position of the interlayer insulating film 33. An intermediate layer 32 is formed on the contact hole CH. On the first interlayer insulating film 33 and the intermediate layer 32, a second interlayer insulating film 34 is formed. A contact hole CH is opened at a predetermined position of the second interlayer insulating film 34. Bit lines BL and / BL are formed on the second interlayer insulating film 34.

  A third interlayer insulating film 35 is formed on second interlayer insulating film 34 and bit lines BL and / BL. A contact hole CH is opened at a predetermined position of the third interlayer insulating film 35. This contact hole CH is opened above the intermediate layer 32. Body fixing lines 30B and 30C are formed on third interlayer insulating film 35. The body fixing line 30C is formed on the contact hole CH and is in contact with the intermediate layer 32. Further, a fourth interlayer insulating film 36 is formed on the third interlayer insulating film 35 and the body fixing lines 30B and 30C.

  The transistor Qn1 of the sense amplifier 20 is formed on the SOI substrate 6. In this SOI substrate, since the buried oxide layer 8 is shallow, the SOI active layer 9 is thin. Therefore, the bottom surface of LOCOS oxide film 5 reaches buried oxide layer 8, and source region 1 and drain region 2 of transistor Qn1 also reach buried oxide layer 8. Therefore, body region 3 of transistor Qn1 is completely separated from the periphery by LOCOS oxide film 5 and buried oxide layer 8, but body fixing line 30C is connected to body region 3, thereby ground potential Vss. Is given.

  On the other hand, in the precharge circuit 23, the equalize line 24 constitutes the gate electrodes of all the transistors Qe and Qpc. Therefore, the p-type body regions 3 of these transistors Qe and Qpc are common to each other. A p + -type contact region 31 is formed in the body region 3. Contact region 31 is connected to body fixing line 30A through contact hole CH. A ground potential Vss is applied to the body fixing line 30A. Therefore, ground potential Vss is applied to body region 4 of transistors Qe and Qpc.

  The driving precharge circuit 22 is configured in substantially the same manner as the bit line precharge circuit 23.

  FIG. 7 is a plan view showing a general configuration of the transistors Qm, Qd, Qb, and Qio of the memory cell 27, the dummy cell 28, the bit line selection circuits 26A and 26B, and the column selection circuit 29. Referring to FIG. 7, ap + -type contact region 31 is formed in p-type body region 3 of these transistors. A ground potential Vss is applied to the contact region 31. Thereby, the body region 3 is electrically fixed.

  As described above, according to the first embodiment, since the DRAM is formed on the SOI substrate, even if α particles rush into the silicon substrate 7 to generate charges in the silicon substrate 7, the silicon substrate 7 7 is electrically isolated by the SOI active layer 9 and the buried oxide layer 8, so that the generated charges do not flow into the source region 1, the drain region 2 and the body region 3. Moreover, since the source region 1, the drain region 2 and the body region 3 are very narrow, charges due to α particles are hardly generated in these regions 1, 2 and 3. Therefore, so-called soft errors hardly occur.

  Further, since the bottom surface of the source / drain region of the transistor Qm constituting the memory cell 27 also reaches the buried oxide layer 8, the PN junction surface exists only perpendicular to the SOI substrate 6 and exists in parallel. do not do. Further, the leakage current in the PN junction is proportional to the surface area of the PN junction. Therefore, the charge leaking from the capacitor Cm via the source / drain region is reduced according to the surface area, thereby increasing the data retention time. In addition, since the junction capacitance of the source / drain region is reduced, the read potential difference generated between the bit line pairs is increased, and the current consumption is also reduced.

  In addition, since the body region of the transistor connected to the bit line is fixed, the charge of the bit line does not leak through the transistor, so the read potential difference generated between the bit line pair is kept sufficiently large. It is. Further, since the body region of the transistor of the sense amplifier 20 is also fixed, almost no kink occurs in these transistors. Therefore, this sense amplifier 20 stably amplifies the read potential difference.

[Example 2]
FIG. 8 is a plan view showing a partial configuration of sense amplifier 20 and the entire configuration of precharge circuit 23 in the DRAM according to the second embodiment of the present invention. Referring to FIG. 8, in the second embodiment, unlike FIG. 5, both body regions 3 protrude in the same direction, and contact regions 31 are formed in the protruding portions. Both contact regions 31 are connected to one body fixing line 30C through contact holes CH, respectively. Both gate electrodes 4 protrude in the same direction, and the protruding portions are connected to the bit lines BL1 and / BL1 through the contact holes CH, respectively.

  In the second embodiment, since the body fixing line 30C for fixing the body region 3 of the transistors Qn1 and Qn2 is shared, the layout area is smaller than that in the first embodiment.

[Example 3]
FIG. 9 is a plan view showing a partial configuration of the sense amplifier 20 and the entire configuration of the precharge circuit 23 in the DRAM according to the third embodiment of the present invention. Referring to FIG. 9, the precharge circuit 23 is obtained by rotating the precharge circuit of the first embodiment 180 degrees. Body region 3 of transistors Qe and Qpc in precharge circuit 23 is connected to body fixing line 30B through contact region 31 and contact hole CH. Body region 3 of transistor Qn2 in sense amplifier 20 is also connected to body fixing line 30B through contact region 31 and contact hole CH.

  In the third embodiment, body fixing line 30B for fixing body region 3 of transistor Qn2 in sense amplifier 20 is a body fixing line for fixing body region 3 of transistors Qe and Qpc in precharge circuit 23. Since it is common, the layout area is smaller than that of the first embodiment.

[Example 4]
FIG. 10 is a circuit diagram showing a partial configuration of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 4 of the present invention. Referring to FIG. 10, in this fourth embodiment, unlike the first embodiment, negative potential V _BB is applied to the body region of transistor Qm in memory cell 27. Negative potential V _BB is also applied to the body region of transistor Qd in dummy cell 28. Therefore, the N channel MOS transistor in the fourth embodiment has two kinds of threshold voltages.

  According to the fourth embodiment, since only the threshold voltages of the transistors Qm and Qd in the memory cell 27 and the dummy cell 28 are large, the subthreshold current hardly flows in the transistors Qm and Qd. Therefore, in a non-selected memory cell, the dynamic data retention characteristic of the bit line amplitude by the sensing operation is further improved. Therefore, the data retention time of the memory cell becomes long.

[Example 5]
FIG. 11 is a circuit diagram showing a partial configuration of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 5 of the present invention. Referring to FIG. 11, in this embodiment 5, all of the N-channel MOS transistor Qm, Qd, Qb, Qpc, Qe, Qn1, Qn2, the body region of Qio, it is given a negative potential V _BB. As in the fifth embodiment, negative potential V _BB may be applied to the body regions of all N channel MOS transistors.

[Example 6]
FIG. 12 is a circuit diagram showing a partial configuration of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 6 of the present invention. Referring to FIG. 12, in the sixth embodiment, unlike FIG. 1, the body regions of four transistors Qn1, Qn2, Qp1, Qp2 in sense amplifier 20 are connected to their own source electrodes. That is, the body regions of transistors Qn1 and Qn2 are connected to sense amplifier drive line 21A. The body regions of transistors Qp1 and Qp2 are connected to sense amplifier drive line 21B. Therefore, the body region of the transistor Qn1 and Qn2 are variable potential is applied to decrease gradually toward the ground potential Vss from the precharge potential V _BL. A body region of the transistor Qp1 and Qp2 are variable potential is applied to rise toward the precharge potential V _BL to the power supply potential Vcc. Therefore, in these transistors Qn1, Qn2, Qp1, and Qp2, since the same voltage is always applied to the PN junction between the body region and the source region, the so-called substrate effect does not occur at all. Therefore, the sensitivity of the sense amplifier 20 is higher than that in the first embodiment. Moreover, even when a low power supply voltage is supplied, the sense amplifier 20 operates at high speed.

  When the DRAM is formed on a normal silicon substrate, the sense amplifier is completely separated from the substrate and other wells in order to synchronize the substrate potential of the transistor in the sense amplifier with the source potential as shown in FIG. Must. Therefore, a triple well structure is usually adopted. In the write operation, the well must be fixed at a constant potential in order to reduce the leakage current due to the subthreshold. As a result, the electric charge in the junction capacitance of the well is charged and discharged, and the current consumption increases. Furthermore, since a triple well structure or the like is adopted, a region for fixing the well potential is required. This increases the layout area.

  On the other hand, in Example 6, since the bottom surface of the body region is in contact with the buried oxide layer, the junction capacitance is very small. Further, since the body region is fixed, the leakage current due to the subthreshold does not increase. Furthermore, since it is not necessary to form a well or the like, the layout area is sufficiently small.

  FIG. 13 is a plan view showing a partial configuration of the sense amplifier 20 and the entire configuration of the precharge circuit 23 shown in FIG. Referring to FIG. 13, in the sixth embodiment, unlike FIG. 5, p + -type common region 38 is formed in a part of source region 1. Therefore, body region 3 of transistor Qn 1 is connected to source region 1 through common region 38. The body region 3 of the transistor Qn2 is connected to the source region 1 through the common region 38. Since sense amplifier drive signal SAN is applied to source region 1 through contact hole CH, body region 3 is electrically connected while a forward voltage is applied to the PN junction between common region 38 and source region 1. Fixed to. That is, the potential of the body region 3 is always higher than the potential of the source region 1 by the barrier potential of the PN junction. According to the sixth embodiment, since it is not necessary to provide the body fixing lines 30B and 30C as in the first embodiment, the layout area is smaller than that in the first embodiment.

[Example 7]
FIG. 14 is a plan view showing structures of a sense amplifier and a precharge circuit in a DRAM according to the seventh embodiment of the present invention. Referring to FIG. 14, in the seventh embodiment, ap + -type common region 38 having substantially the same size as source region 1 is formed between body regions 3. Source region 1 is connected to sense amplifier drive line 21A via contact hole CH, and common region 38 is also connected to sense amplifier drive line 21A via contact hole CH. Therefore, body region 3 of transistor Qn1 is connected to sense amplifier drive line 21A through common region 38 and contact hole CH. Body region 3 of transistor Qn2 is connected to sense amplifier drive line 21A through common region 38 and contact hole CH. Therefore, since the potentials of the common region 38 and the source region 1 are always the same, the body region 3 is always electrically fixed.

[Example 8]
FIG. 15 is a plan view showing structures of a sense amplifier and a precharge circuit in a DRAM according to the eighth embodiment of the present invention. Referring to FIG. 15, in this eighth embodiment, unlike FIG. 14, P + type common regions 38 are formed on both sides of source region 1. Two contact holes CH are formed over the source region 1 and the common region 38, respectively. Therefore, body region 3 of Qn1 is connected to sense amplifier drive line 21A via two common regions 38 and two contact holes CH, and body region 3 of transistor Qn2 is also connected to two common regions 38 and two contact holes CH. To the sense amplifier drive line 21A. According to the eighth embodiment, since the small common region 38 is formed on both sides of the source region 1, the execution channel length of the transistors Qn1 and Qn2 becomes long. Moreover, since the two common regions 38 are provided, the body region 3 is reliably fixed even in the transistors Qn1 and Qn2 having a long execution channel length. Therefore, even at a position far from the common region 38, the potential of the body region 3 quickly follows the potential SAN of the sense amplifier drive line 21A, so that this sense amplifier operates more stably than the seventh embodiment of FIG. To do.

[Example 9]
FIG. 16 is a circuit diagram showing a partial configuration of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 9 of the present invention. Referring to FIG. 16, in the ninth embodiment, unlike FIG. 12, the body regions of transistors Qb and Qio in bit line selection circuits 26A and 26B and column selection circuit 29 are in an electrically floating state. Even if these transistors Qb and Qio are brought into a floating state, a large amount of leakage current does not flow through them.

  According to the ninth embodiment, the body regions of some N-channel MOS transistors are electrically fixed, and the body regions of other N-channel MOS transistors are in a floating state. Even the number of body fixing lines is reduced. As a result, the area for the body fixing line is reduced, thereby reducing the layout area.

[Example 10]
FIG. 17 is a circuit diagram showing a partial configuration of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 10 of the present invention. Referring to FIG. 17, in the tenth embodiment, unlike FIG. 1, the body regions of all the P channel MOS transistors are in an electrically floating state. Specifically, the body regions of Qp1 and Qp2 in the sense amplifier 20 are in a floating state. Note that the body regions of all N-channel MOS transistors are electrically fixed.

  Since the breakdown voltage between the source and drain of a P channel MOS transistor is generally higher than that of an N channel MOS transistor, the body region of the N channel MOS transistor may be fixed. According to the tenth embodiment, since the body fixing region and the body fixing line for fixing the body region of the P-channel MOS transistor are not required, the layout area is smaller than that in the first embodiment.

[Example 11]
FIG. 18 is a circuit diagram showing structures of a memory cell array, sense amplifiers, and input / output circuits in a DRAM according to Embodiment 11 of the present invention. Referring to FIG. 18, in the eleventh embodiment, bit lines BL 0 and / BL 0 are arranged on both sides of sense amplifier 20. That is, a so-called open bit line structure is adopted.

  In the eleventh embodiment, similarly to the first embodiment, ground potential Vss is applied to the body regions of N channel MOS transistors Qn1 and Qn2 in sense amplifier 20, and power supply is applied to the body regions of P channel MOS transistors Qp1 and Qp2. A potential Vcc is applied. The ground potential Vss is applied to the body regions of the N channel MOS transistors Qe and Qpc in the bit line precharge circuit 23. The ground potential Vss is applied to the body regions of the N channel MOS transistors Qse and Qsp in the sense amplifier drive line precharge circuit 22. A ground potential Vss is applied to the body region of N channel MOS transistor Qio in the column selection circuit. The ground potential Vss is also applied to the body region of N channel MOS transistor Qm in memory cell 27. Further, ground potential Vss is also applied to the body region of N channel MOS transistor Qd in dummy cell 28.

  According to the eleventh embodiment, the same effect as in the first embodiment is obtained, and since the open bit line structure is adopted, the memory cells 27 can be arranged at all the intersections of the word lines and the bit lines.

[Example 12]
FIG. 19 is a circuit diagram showing structures of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 12 of the present invention. Referring to FIG. 19, in the twelfth embodiment, unlike FIG. 18, the body regions of four transistors Qn1, Qn2, Qp1, and Qp2 in sense amplifier 20 are connected to their own source electrodes. Therefore, sense amplifier drive signal SAN is applied to the body regions of N channel MOS transistors Qn1 and Qn2. Sense amplifier drive signal SAP is applied to the body regions of P channel MOS transistors Qp1 and Qp2.

  According to the twelfth embodiment, the same effect as that of the sixth embodiment of FIG. 12 is obtained and the open bit line structure is adopted. Therefore, the memory cells 27 can be arranged at all the intersections of the word lines and the bit lines. it can.

[Example 13]
FIG. 20 is a circuit diagram showing a partial configuration of a row decoder in a DRAM according to Embodiment 13 of the present invention. Referring to FIG. 20, the word line driving circuit in the row decoder includes eight N channel MOS transistors Qr1 to Qr8 at the final stage. Transistors Qr1 and Qr2 are connected in series, and the source electrode of transistor Qr1 is connected to word line WL0. Transistors Qr3 and Qr4 are connected in series, and the source electrode of transistor Qr3 is connected to word line WL1. Transistors Qr5 and Qr6 are connected in series, and the source electrode of transistor Qr5 is connected to word line WL2. Transistors Qr7 and Qr8 are connected in series, and the source electrode of transistor Qr7 is connected to word line WL3.

  This word line driving circuit is activated in response to signals Xj, Xk, and Xl obtained by predecoding the row address signal. When the word line driving circuit is activated and one of the boost signals RX0 to RX3 is applied to the drain electrode of the corresponding transistor, the corresponding one of the word lines WL0 to WL3 rises. Since boosted signals RX0-RX3 are boosted power supply potential Vcc, word lines WL0-WL3 rise to a potential higher than power supply potential Vcc. Therefore, a voltage higher than the power supply voltage is applied between the source and drain of the transistors Qr1 to Qr8.

  Further, when the boost signals RX0 to RX3 are applied when the word line driving circuit is not activated, the potentials of the body regions of the transistors Qr1, Qr3, Qr5, and Qr7 rise due to the coupling of parasitic capacitances, thereby The threshold drops. Therefore, the boosted potential leaks through the transistors Qr1, Qr3, Qr5, and Qr7, and the boosted potential becomes insufficient. When the leaked boosted potential is applied to the non-selected word line, data leaks from the non-selected memory cell.

  In the thirteenth embodiment, the ground potential Vss is applied to the body regions of the transistors Qr1 to Qr12, so that the body region is electrically fixed. Therefore, since the withstand voltage between the source and drain of these transistors Qr1 to Qr12 is increased, this word line driving circuit operates normally. Further, since the threshold value drop due to parasitic capacitance coupling is suppressed, the word line driving circuit operates stably.

[Example 14]
FIG. 21 is a circuit diagram showing a partial structure of a row decoder in a DRAM according to Embodiment 14 of the present invention. Referring to FIG. 21, in the fourteenth embodiment, unlike the thirteenth embodiment, the body regions of transistors Qr1-Qr12 are connected to their own source regions. Specifically, the body regions of transistors Qr1, Qr3, Qr5, and Qr7 are connected to word lines WL0 to WL3. The body regions of transistors Qr2, Qr4, Qr6, Qr8 are connected to the ground node. The body regions of the transistors Qr9 to Qr12 are connected to a node on the side where the potential does not rise by self-bootstrap.

  FIG. 22 is a plan view showing a general configuration of transistors Qr1-Qr12 in the word line driving circuit shown in FIG. Referring to FIG. 22, transistors Qr1-Qr12 each include an n + type source region 1, an n + type drain region 2, a p type body region 3, a gate electrode 4, and a p + type common region 38. . The common region 38 is formed adjacent to the source region 1 and the body region 3. Therefore, the body region 3 is connected to the source region 1 through the common region 38 and is electrically fixed thereby.

  In the fourteenth embodiment, since the body regions of the transistors Qr1, Qr3, Qr5, and Qr7 are connected to the word lines WL0 to WL3, the potential of the body region 3 follows the potential of the word lines WL0 to WL3. Therefore, no substrate effect occurs in transistors Qr1, Qr3, Qr5, and Qr7, and the potentials of word lines WL0 to WL3 rise quickly.

  Moreover, since the body region 3 of the transistors Qr1 to Qr12 is connected to its own source region 1, it is not necessary to provide a body fixing line. Therefore, the layout area of the fourteenth embodiment is smaller than that of the thirteenth embodiment shown in FIG.

[Example 15]
FIG. 23 is a circuit diagram showing a structure of a boost signal predecode circuit according to the fifteenth embodiment of the present invention. This boost signal predecode circuit is for supplying boost signals RX0 to RX3 to the word line driving circuit shown in FIGS.

  Referring to FIG. 23, this boost signal predecode circuit includes transistors Qr13-Qr15 and inverters I1 and I2. Transistors Qr13 and Qr14 are connected in series. A boost signal RX, which is an output of the boost voltage generation circuit, is applied to the drain electrode of the transistor Qr13. Row address signal X is applied to one source / drain electrode of transistor Qr15 through inverters I1 and I2. The output of inverter I1 is applied to the gate electrode of transistor Qr14.

  The boost signal predecode circuit is activated in response to the row address signal X. When the boost signal RX is applied while being activated, the gate potential of the transistor Qr13 rises by self-bootstrap. Qr13 becomes completely conductive. Therefore, the given boost signal RX is output to the outside as boost signals RX0 to RX3 via the transistor Qr13.

  As apparent from the above operation, a voltage higher than the power supply voltage is applied between the sources and drains of the transistors Qr13 to Qr15. Therefore, in the fifteenth embodiment, the ground potential Vss is applied to the body regions of the transistors Qr13 to Qr15, whereby the body region is electrically fixed. Therefore, the withstand voltage between the source and drain of these transistors Qr13 to Qr15 increases, so that this boost signal predecode circuit operates normally.

[Example 16]
FIG. 24 is a circuit diagram showing the structure of a boost signal predecode circuit in a DRAM according to Embodiment 16 of the present invention. Referring to FIG. 24, in the sixteenth embodiment, unlike FIG. 23, the body regions of transistors Qr13-Qr15 are connected to their own source regions.

  In the sixteenth embodiment, in particular, the body region of transistor Qr13 is connected to its own source region. Therefore, the potential of the body region of transistor Qr13 rises following the output boost signals RX0 to RX3. Therefore, no substrate effect occurs in transistor Qr13, so that boost signals RX0-RX3 rise quickly. In addition, since each body region is connected to its own source region, it is not necessary to provide a body fixing line, so the layout area of the sixteenth embodiment is smaller than that of the fifteenth embodiment of FIG.

[Example 17]
FIG. 25 is a plan view showing the structure of an N channel MOS capacitor in a DRAM according to Embodiment 17 of the present invention. The MOS capacitor is used in, for example, a word line drive circuit, a boost signal predecode circuit, a circuit that generates a voltage V _PP obtained by boosting a power supply voltage.

  Referring to FIG. 25, this MOS capacitor includes an n + -type source region 1, a p-type body region 3 surrounded by the source region 1, a gate electrode 4, and a p + -type common region 38. The common region 38 is inserted into a part of the source region 1. Therefore, the common region 38 is formed adjacent to the source region 1 and the body region 3. Therefore, body region 3 is connected to source region 1 through common region 38. As a result, body region 3 is electrically fixed, so that the MOS capacitor operates stably. In addition, since the body region 3 is connected to the source region 1 through the common region 38 inserted in a part of the source region 1, there is no need to provide a body fixing line or the like. Therefore, the layout area of the seventeenth embodiment is the same as the conventional one.

  In Example 17, only the common region 38 is inserted into a part of the source region 1, but one contact hole is formed on the junction between the source region 1 and the common region 38, Source region 1 and common region 38 may be connected to the body fixing line through the contact hole. In this way, the body region 3 can be electrically fixed even when the potential of the source region 1 is higher than the potential of the common region 38.

[Example 18]
FIG. 26 is a plan view showing the structure of the P channel MOS capacitor in the DRAM according to the eighteenth embodiment of the present invention. Referring to FIG. 26, this P-channel MOS capacitor includes a p + type source region 1, an n type body region 3 surrounded by the source region 1, a gate electrode 4, and an n + type common region 38. Prepare. In Example 18, the conductivity type of each region in Example 17 of FIG. 25 is reversed.

[Example 19]
FIG. 27 is a plan view showing the structure of an N channel MOS capacitor in a DRAM according to Embodiment 19 of the present invention. Referring to FIG. 27, this N channel MOS capacitor includes two n + type source regions 1, a p type body region 3 located between the source regions 1, a gate electrode 4, and a p + type contact region. 31. The two source regions 1 are connected to each other. The contact region 31 is inserted into a part of the body region 3 and is formed adjacent to only the body region 3.

  Contact region 31 is applied with the same potential as that applied to source region 1, whereby body region 3 is connected to source region 1 through contact region 31. Therefore, the N channel MOS capacitor operates stably because its body region 3 is electrically fixed.

In the nineteenth embodiment, the same potential as that applied to the source region 1 is applied to the contact region 31, but the ground potential Vss or the negative potential V _BB may be applied to the contact region 31.

[Example 20]
FIG. 28 is a plan view showing the structure of the P channel MOS capacitor in the DRAM according to the embodiment 20 of the present invention. Referring to FIG. 28, this P channel MOS capacitor includes two p + type source regions 1, an n type body region 3 located between the source regions 1, a gate electrode 4, and an n + type contact region. 31. A predetermined potential is applied to the contact region 31, whereby the body region 3 is electrically fixed. In Example 20, the conductivity type of each region in Example 19 of FIG. 27 is reversed.

[Example 21]
FIG. 29 is a circuit diagram showing a structure of a boosted power generation circuit in a DRAM according to the embodiment 21 of the present invention. Referring to FIG. 29, the boosted power generation circuit includes three MOS capacitors Cbs1 to Cbs3 and an N channel MOS transistor Qbs at the final stage. This boosted power generation circuit generates boosted potential V _PP higher than power supply potential Vcc in response to clock signal CK.

  In the transistor Qbs of this boosted power generation circuit, the potential of the drain electrode (output node) is always higher than the potential of the source electrode. Therefore, the body region of this transistor Qbs is connected to its own source region. As a result, the breakdown voltage between the source and drain of the transistor Qbs is increased. Moreover, since the body region is connected to the source region, there is no need to provide a body fixing line or the like. Therefore, the layout area of the twenty-first embodiment is almost the same as the conventional one.

[Example 22]
FIG. 30 is a circuit diagram showing structures of an output preamplifier and a write circuit in a DRAM according to Embodiment 22 of the present invention. Referring to FIG. 30, output preamplifier 40 is of a current mirror type and includes P channel MOS transistors Qp5 to Qp11 and N channel MOS transistors Qn5 to Qn12. Since the output preamplifier generally amplifies the potentials of the input / output lines IO and / IO in an analog manner, it is susceptible to kink. Therefore, the body regions of P channel MOS transistors Qp5 to Qp11 are connected to their own source regions. The body regions of N channel MOS transistors Qn5 to Qn12 are connected to their own source regions.

  According to the twenty-second embodiment, since the body regions of the transistors Qp5 to Qp11 and Qn5 to Qn12 are electrically fixed, no kink occurs in these transistors. Therefore, output preamplifier 40 can stably amplify the potentials of input / output lines IO and / IO.

  On the other hand, write circuit 41 includes four N-channel MOS transistors Qn13 to Qn16. Since the ground potential Vss is applied to the body regions of the transistors Qn13 to Qn16, these body regions are electrically fixed. Therefore, a large amount of leakage current does not flow between the sources and drains of the transistors Qn13 to Qn16.

[Example 23]
FIG. 31 is a circuit diagram showing structures of an input / output line precharge circuit and an input / output line equalize circuit in a DRAM according to Embodiment 23 of the present invention. Referring to FIG. 31, input / output line precharge circuit 42 includes P channel MOS transistors Qp21 and Qp22 and N channel MOS transistors Qn21 and Qn22. P channel MOS transistor Qp21 and N channel MOS transistor Qn21 form a transfer gate. P channel MOS transistor Qp22 and N channel MOS transistor Qn22 also form a transfer gate. Input / output line precharge circuit 42 precharges input / output lines IO and / IO to a predetermined potential in response to precharge signal YN.

  On the other hand, the input / output line equalize circuit includes a P channel MOS transistor Qp20 and an N channel MOS transistor Qn20. Transistors Qp20 and Qn20 form a transfer gate. This input / output line equalize circuit equalizes the potentials of input / output lines IO and / IO in response to input / output line equalize signals IOEQ and / IOEQ.

  In the twenty-third embodiment, power supply potential Vcc is applied to the body regions of P channel MOS transistors Qp20-Qp22. Ground potential Vss is applied to the body regions of N channel MOS transistors Qn20-Qn22. As a result, the body regions of the transistors Qp20 to Qp22, Qn20 to Qn22 are electrically fixed. Therefore, a large amount of leakage current does not flow between the source and drain of these transistors. Therefore, accurate data is transmitted via input / output lines IO and / IO.

[Example 24]
FIG. 32 is a circuit diagram showing a partial structure of a row address buffer in a DRAM according to Embodiment 24 of the present invention. Referring to FIG. 32, this row address buffer is of a dynamic latch type and includes P channel MOS transistors Qp25-Qp28 and N channel MOS transistors Qn25-Qn30. This address buffer has an external address signal ext. In response to An, internal row address signals RAn and / RAn are generated. This address buffer has an external address signal ext. An is compared with the reference signal VREF, whereby the external address signal ext. It is determined whether An is at H level or L level.

  In the twenty-fourth embodiment, the body regions of the transistors Qp25 to Qp28 are connected to the source electrode. Ground potential Vss is applied to the body regions of transistors Qn25, Qn26, Qn29, and Qn30. This dynamic latch type row address buffer latches the address signal in response to the fall of the control signal / RADBE. Therefore, in the activated state, no reverse voltage is applied to the PN junction between the body region and the source region, so that the body regions of the transistors Qn27 and Qn28 can be connected to their own source electrodes. is there.

  Therefore, since the body regions of transistors Qp25-Qp28 and Qn25-Qn30 are electrically fixed, this row address buffer stably performs analog operation. In addition, since transistors Qp27 and Qp28 are not subjected to the substrate effect, this row address buffer is connected to external address signal ext. Whether An is at an H level or an L level can be determined stably and at high speed.

[Example 25]
FIG. 33 is a circuit diagram showing a partial structure of a column address buffer in a DRAM according to Embodiment 25 of the present invention. Referring to FIG. 33, this column address buffer includes P channel MOS transistors Qp31-Qp34 and N channel MOS transistors Qn31-Qn34. Transistors Qp31, Qp32, Qn31, and Qn32 constitute a NOR circuit. Transistors Qp33, Qp34, Qn33, Qn34 constitute a clocked inverter in the next stage. This column address buffer is connected to external address signal ext. In response to An, internal column address signals CAn and / CAn are generated.

  The body regions of all the transistors Qp31, Qp32, Qn31, Qn32 constituting this NOR circuit are connected to their own source regions. Therefore, ground potential Vss is applied to the body regions of N channel MOS transistors Qn31 and Qn32. On the other hand, the body regions of all the transistors Qp33, Qp34, Qn33, Qn34 constituting the inverter are in a floating state.

  In the twenty-fifth embodiment, the external address signal ext. It is accurately determined whether An is at the H level or the L level. In addition, since the body regions of transistors other than the first input stage transistors, for example, the transistors Qp33, Qp34, Qn33, Qn34 constituting the next stage clocked inverter, and other transistors constituting the logic gate are in a floating state. There is no need to provide a body fixing line. Therefore, an increase in layout area can be minimized.

[Example 26]
FIG. 34 is a circuit diagram showing a partial structure of a column address buffer in a DRAM according to Embodiment 26 of the present invention. Referring to FIG. 34, in this embodiment 26, the negative potential V _BB is applied to the body region of the N-channel MOS transistors Qn31 and Qn32 constitute a NOR circuit different from FIG 33. As mentioned above, the body region of the N-channel MOS transistors Qn31, Qn32, negative potential V _BB may be provided in place of the ground potential Vss.

[Example 27]
FIG. 35 is a circuit diagram showing a partial structure of a column address buffer in a DRAM according to Embodiment 27 of the present invention. In the twenty-seventh embodiment, unlike FIG. 33, the body regions of all transistors Qp33, Qp34, Qn33, Qn34 constituting the inverter are connected to their own source regions. According to the twenty-seventh embodiment, since the body regions of the transistors constituting the input first stage transistor and the next stage clocked inverter are electrically fixed, the layout area is slightly increased, but the body regions are not fixed. This column address buffer operates more stably than.

[Example 28]
FIG. 36 is a circuit diagram showing a partial structure of a column address buffer in a DRAM according to Embodiment 28 of the present invention. In the twenty-eighth embodiment, unlike FIG. 27, negative potential V _BB is applied to the body regions of N-channel MOS transistors Qn31 and Qn32. In this manner, the body region of the N-channel MOS transistors Qn31, Qn32, negative potential V _BB may be provided in place of the ground potential Vss.

[Example 29]
FIG. 37 is a circuit diagram showing a structure of a clock input buffer in the DRAM according to the embodiment 29 of the present invention. Referring to FIG. 37, the clock input buffer includes P channel MOS transistors Qp35 to Qp37, an N channel MOS transistor Qn35, and inverters I3 to I5. This clock input buffer is connected to an external row address strobe signal ext. In response to / RAS, internal row address strobe signals RAS and / RAS are generated.

  In the embodiment 29, the body regions of the transistors Qp35 to Qp37 and Qn35 at the first input stage are connected to their own source regions. Therefore, ground potential Vss is applied to the body region of N channel MOS transistor Qn35.

  Thus, since the body regions of transistors Qp35-Qp37 and Qn35 at the first input stage are electrically fixed, external row address strobe signal ext. Whether / RAS is at the H level or the L level is accurately determined. Moreover, since the body regions of transistors Qp35 to Qp37 and Qn35 are connected to their own source regions, there is no need to provide a body fixing line or the like. Therefore, the layout area of this clock input buffer is the same as the conventional one.

[Example 30]
FIG. 38 is a circuit diagram showing a structure of a clock input buffer in the DRAM according to Embodiment 30 of the present invention. In the thirtieth embodiment, unlike FIG. 37, negative potential V _BB is applied to the body region of input first stage N channel MOS transistor Qn35. In this manner, the body region of the N-channel MOS transistors Qn35, a negative potential V _BB may be provided in place of the ground potential Vss.

[Example 31]
FIG. 39 is a circuit diagram showing a structure of a clock input buffer in the DRAM according to Embodiment 31 of the present invention. Referring to FIG. 39, this clock input buffer includes P channel MOS transistors Qp35-Qp37, N channel MOS transistor Qn35, and inverters I3-I5, as in the embodiment 29 of FIG. Inverter I4 includes a P-channel MOS transistor Qp38 and an N-channel MOS transistor Qn38. Inverter I5 includes a P-channel MOS transistor Qp39 and an N-channel MOS transistor Qn39.

In Embodiment 31, unlike FIG. 37, the body regions of P-channel MOS transistors Qp38 and Qp39 constituting inverters I4 and I5 are connected to their own source regions. Negative potential V _BB is applied to the body regions of N channel MOS transistors Qn38 and Qn39 constituting inverters I4 and I5.

  In the thirty-first embodiment, since the body regions of the final stage transistors Qp38, Qp39, Qn38, and Qn39 are electrically fixed, the clocks of the internal row address strobe signals RAS, / RAS generated by this clock input buffer are used. The queue is reduced.

[Example 32]
40 is a circuit diagram showing a structure of a clock input buffer in a DRAM according to Embodiment 32 of the present invention. In the embodiment 32, unlike FIG. 39, the body regions of the final-stage N-channel MOS transistors Qn38, Qn39 are connected to their own source regions.

According to the thirty-second embodiment, since the body regions of N channel MOS transistors Qn38 and Qn39 are connected to their own source regions, it is not necessary to provide a body fixing line. Therefore, the increase in the layout area can be minimized. In this manner, the body region of the transistor Qn38, Qn39 of the final stage, the ground potential Vss may be provided in place of the negative potential V _BB.

[Example 33]
41 is a circuit diagram showing a structure of a sense amplifier driving circuit in a DRAM according to Embodiment 33 of the present invention. Referring to FIG. 41, this sense amplifier drive circuit includes a plurality of inverters connected in series and a plurality of MOS capacitors Csp1-Csp3, Csn1-Csn3. The sense amplifier driving circuit generates control signals S0F, S0N, / S0P for driving the sense amplifier 20 in response to the boost signal RX.

  FIG. 42 is a timing chart showing the operation of the sense amplifier driving circuit shown in FIG. Referring to FIG. 42, control signal S0F rises after a lapse of a fixed time from the rise of boost signal RX. Furthermore, the control signal S0N rises after a lapse of a certain time from the rise of the control signal S0F. Further, control signal / S0P falls after a lapse of a certain time from the rise of control signal S0N.

  In the sense amplifier driving circuit according to the thirty-third embodiment, since the body regions of all the MOS capacitors Csp1 to Csp3 and Csn1 to Csn3 are electrically fixed, the threshold values of the MOS capacitors Csp1 to Csp3 and Csn1 to Csn3 are Therefore, the time from the rise of the boost signal RX to the rise of the control signal S0F is not shortened, or the time from the rise of the control signal S0F to the rise of the control signal S0N is not shortened. Therefore, the operation margin of the sense amplifier 20 does not decrease.

In the thirty-third embodiment, power supply potential Vcc is applied to the body regions of P-channel MOS capacitors Csp1-Csp3. Ground potential Vss is applied to the body regions of N channel MOS capacitors Csn1 to Csn3. However, the body region of the N-channel MO capacitor Csn1～Csn3, negative potential V _BB may be provided in place of the ground potential Vss.

[Example 34]
FIG. 43 is a circuit diagram showing the structure of a CAT (Column Address Transition) circuit in a DRAM according to Embodiment 34 of the present invention. Referring to FIG. 43, this CAT circuit includes three inverters I20-I22, three NOR circuits NR1-NR3, two P-channel MOS capacitors Ctp1, Ctp2, and N-channel MOS capacitors Ctn1, Ctn2. . The CAT circuit generates a control signal CAT in response to the control signal CAD. Here, power supply potential Vcc is applied to the body regions of P-channel MOS capacitors Ctp1 and Ctp2. Ground potential Vss is applied to the body regions of N channel MOS capacitors Ctn1 and Ctn2.

  FIG. 44 is a timing chart showing the operation of the CAT circuit shown in FIG. Referring to the timing chart of FIG. 43, as soon as control signal CAD rises, the potential of output node A of NOR circuit NR1 falls. After a lapse of a certain time from the fall of the potential of the node A, the potential of the output node B of the NOR circuit NR3 rises. Subsequently, as soon as the control signal CAD falls, the potential of the node B falls. The node A potential rises after a lapse of a certain time from the fall of the node B potential.

  On the other hand, as soon as the potential of the node A falls, the control signal CAT rises. As soon as the potential of the node B rises, the control signal CAT falls. Further, as soon as the potential of the node B falls, the control signal CAT rises. As soon as the potential of the node A rises, the control signal CAT falls.

  Here, if the body regions of the MOS capacitors Ctp1, Ctp2, Ctn1, and Ctn2 are in a floating state, the threshold values of the capacitors become unstable due to potential fluctuations in the body region, and the capacitances of the capacitors are thereby reduced. May become unstable. Therefore, as shown in the timing chart of FIG. 44, the falling timing of the control CAT1 is delayed or the falling timing of the control signal CAT2 is advanced. In particular, in the case of the control signal CAT2 whose falling is delayed, the operation margin of the CAT circuit is reduced.

  Therefore, in the thirty-fourth embodiment, the body regions of the MOS capacitors Ctp1, Ctp2, Ctn1, and Ctn2 are electrically fixed. Therefore, a stable control signal CAT is always generated.

[Example 35]
FIG. 45 is a circuit diagram showing a structure of an NN buffer in a DRAM according to Embodiment 35 of the present invention. The NN buffer is used as a data output buffer of a DRAM.

  Referring to FIG. 45, this NN buffer includes N channel MOS transistors Qnn1 and Qnn2 connected in series. The body regions of N channel MOS transistors Qnn1 and Qnn2 are each connected to their own source regions. Therefore, the body region of N channel MOS transistor Qnn1 is connected to output node OUT.

  In this NN buffer, complementary signals Do and / Do are applied to the gate electrodes of transistors Qnn1 and Qnn2, respectively. When signal Do is at H level and signal / Do is at L level, transistor Qnn1 is turned on and transistor Qnn2 is turned off. Therefore, an H level signal is output.

  In the NN buffer according to the thirty-fifth embodiment, since the body regions of N channel MOS transistors Qnn1 and Qnn2 are electrically fixed, the threshold value does not become unstable, and the transistors Qnn1 and Qnn2 A large amount of leakage current does not flow between the source and drain. Therefore, no leak current flows out through the transistor Qnn1, or no leak current flows in from the outside through the transistor Qnn2.

  Further, in this NN buffer, the body areas of the transistors Qnn1 and Qnn2 are connected to their own source areas, so the layout area does not increase. In addition, since the body region of transistor Qnn1 is connected to the output node, the potential of the body region follows the potential of the output node. Therefore, the threshold value of transistor Qnn1 does not increase due to the substrate effect. Therefore, the output signal of this NN buffer quickly rises to the power supply potential Vcc.

[Example 36]
FIG. 46 is a circuit diagram showing a structure of an NN buffer in a DRAM according to Embodiment 36 of the present invention. In the embodiment 36, unlike FIG. 45, the ground potential Vss is applied to the body regions of the transistors Qnn1 and Qnn2. Thus, the ground potential Vss may be applied to the body regions of the transistors Qnn1 and Qnn2 instead of the source potential.

[Example 37]
47 is a circuit diagram showing a structure of a 2-input NAND circuit in a DRAM according to Embodiment 37 of the present invention. The NAND circuit is used in various parts of the DRAM in addition to a clock input buffer for generating the internal row address strobe signal / RAS.

  Referring to FIG. 47, this NAND circuit is of the CMOS type and has two input terminals. This NAND circuit includes P channel MOS transistors Qgp1 and Qgp2 connected in parallel between a power supply node and an output node 50, and an N channel MOS transistor Qgn1 connected in series between an output node 50 and a ground node 51. And Qgn2. Input signal IN1 is applied to the gate electrodes of transistors Qgp1 and Qgn1. Input signal IN2 is applied to the gate electrodes of transistors Qgp2 and Qgn2. The output signal OUT is supplied from the output node 50.

  In this NAND circuit, the body regions of P channel MOS transistors Qgp1 and Qgp2 are in a floating state, but the body regions of N channel MOS transistors Qgn1 and Qgn2 are connected to their own source regions. Therefore, these body regions are electrically fixed. As a result, the threshold value of transistor Qgn1 becomes stable and small, and this NAND circuit operates at high speed. Therefore, even when the power supply potential Vcc is low, this NAND circuit operates normally.

  FIG. 48 is a plan view showing a configuration of N channel MOS transistors Qgn1 and Qgn2 in the NAND circuit shown in FIG. Referring to FIG. 48, transistor Qgn1 includes an n + -type drain region 52, an n + -type source / drain region 53, a p-type body region 57, and a gate electrode 59. Transistor Qgn2 is formed of n + -type source / drain region 53, n + source region 54, p-type body region 58, and gate electrode 60 common to transistor Qgn1. Drain region 52 of transistor Qgn1 is connected to output node 50 made of aluminum via contact hole CH. Source region 54 of transistor Qgn2 is connected to ground node 51 made of aluminum through contact hole CH.

  A p + -type common region 55 is formed in a part of the source / drain region 53. A contact hole CH is formed on the junction between the source / drain region 53 and the common region 55 with an intermediate layer 61 made of aluminum interposed. Therefore, the body region 57 is connected to the source / drain region 53 through the common region 55 and is electrically fixed thereby.

  A p + -type common region 56 is formed in a part of the source region 54. A contact hole CH is formed on the junction between the source region 54 and the common region 56. Accordingly, the body region 58 is connected to the source region 54 via the common region 56 and is electrically fixed thereby.

[Example 38]
FIG. 49 is a plan view showing another configuration of N channel MOS transistors Qgn1 and Qgn2 in the NAND circuit shown in FIG. Referring to FIG. 49, in the thirty-eighth embodiment, an intermediate layer 62 made of polysilicon is formed on drain region 52, source / drain region 53 and source region 54, unlike FIG. Since the intermediate layer 62 functions as an etching stopper, even the SOI substrate is not etched when the contact hole CH is formed by etching.

[Example 39]
FIG. 50 is a plan view showing still another configuration of N channel MOS transistors Qgn1 and Qgn2 in the NAND circuit shown in FIG. Referring to FIG. 50, in this embodiment 39, unlike FIG. 48, a part of source / drain region 65 protrudes between gate electrodes 59 and 60. A p + -type common region 66 is formed adjacent to the protruding portion of the source / drain region 65. A contact hole CH is formed on the protruding portion of the source / drain region 65 and the junction of the common region 66 with an intermediate layer 67 made of aluminum interposed.

  In the embodiment 39, the body region 57 is connected to the source region 65 through the common region 66, and is electrically fixed thereby. Further, since no contact hole is formed between the gate electrodes 59 and 60, the distance between the gate electrodes 59 and 60 can be shortened.

[Example 40]
FIG. 51 is a plan view showing still another configuration of N channel MOS transistors Qgn1 and Qgn2 in the NAND circuit shown in FIG. Referring to FIG. 51, in this embodiment 40, unlike FIG. 50, an intermediate layer 68 made of polysilicon is formed on drain region 52, source / drain region 65, and source region 54, respectively. Therefore, when the contact hole CH is formed by etching, even the SOI substrate is not etched.

[Example 41]
FIG. 52 is a circuit diagram showing a structure of a 3-input NAND circuit in a DRAM according to Embodiment 41 of the present invention. Referring to FIG. 52, this 3-input NAND circuit is provided between P-channel MOS transistors Qgp5, Qgp4 and Qgp3 connected in parallel between a power supply node and output node 70, and between output node 70 and ground node 71. N-channel MOS transistors Qgn3, Qgn4 and Qgn5 connected in series. Input signal IN1 is applied to the gate electrodes of transistors Qgp3 and Qgn3. Input signal IN2 is applied to the gate electrodes of transistors Qgp4 and Qgn4. Input signal IN3 is applied to the gate electrodes of transistors Qgp5 and Qgn5. The output signal OUT is supplied from the output node 70.

  In this NAND circuit, the body regions of the transistors Qgp3 to Qgp5 are brought into a floating state, and the body regions of the transistors Qgn3 to Qgn5 are connected to the source region, thereby being electrically fixed. Therefore, the threshold values of transistors Qgn3 and Qgn4 become small, and this three-input NAND circuit operates at high speed. Further, since the body regions of transistors Qgp3 to Qgp5 are in a floating state, it is not necessary to provide a body fixing line or the like, so that the layout area does not increase so much.

  FIG. 53 is a plan view showing a configuration of N channel MOS transistors Qgn3 to Qgn5 in the three-input NAND circuit shown in FIG. Referring to FIG. 53, transistor Qgn3 includes an n + -type drain region 72, an n + -type source / drain region 73, a p-type body region 79, and a gate electrode 82. Transistor Qgn4 includes source / drain region 37 common to transistor Qgn3, n + source / drain 74, and p-type body region 80. Transistor Qgn5 includes source / drain region 74 common to transistor Qgn4, n + -type source region 75, p-type body region 81, and gate electrode 84.

  The drain region 72 of the transistor Qgn3 is connected to the output node 70 through two contact holes CH. A p + -type common region 76 is formed in a part of the source / drain region 73. Therefore, the body region 79 of the transistor Qgn3 is connected to the source / drain region 73 through the common region 76, and is electrically fixed thereby. A contact hole CH is formed on the junction between the source / drain region 73 and the common region 76 with an intermediate layer 85 made of aluminum interposed therebetween.

  A p + -type common region 77 is formed in a part of the source / drain region 74. Therefore, the body region 80 of the transistor Qgn4 is connected to the source region 74 through the common region 77, and is electrically fixed thereby. A contact hole CH is formed on the junction between the source / drain region 74 and the common region 77 with an intermediate layer 85 made of aluminum interposed. Source region 75 of transistor Qgn5 is connected to ground node 71 via two contact holes CH. A p + -type common region 78 is formed in a part of the source region 75. The body region of the transistor Qgn5 is connected to the source region 75 through the common region 78, and is electrically fixed thereby.

[Example 42]
54 is a plan view showing another configuration of N channel MOS transistors Qgn3 to Qgn5 in the three-input NAND circuit shown in FIG. Referring to FIG. 54, the embodiment 42 differs from FIG. 53 in that an intermediate layer 86 made of polysilicon is formed on drain region 72, source / drain regions 73 and 74, and source region 75, respectively. Therefore, when the contact hole CH is formed by etching, even the SOI substrate is not etched.

[Example 43]
FIG. 55 is a plan view showing another configuration of N channel MOS transistors Qgn3 to Qgn5 in the three-input NAND circuit shown in FIG. Referring to FIG. 55, in this embodiment 43, unlike FIG. 53, source / drain region 90 projects from between gate electrodes 82 and 83. The source / drain region 91 also protrudes from between the gate electrodes 83 and 84. A p + -type common region 92 is formed adjacent to the protruding portion of the source / drain region 90. Therefore, the body region 79 of the transistor Qgn3 is connected to the source / drain region 90 via the common region 92, and is electrically fixed thereby. A p + -type common region 93 is formed adjacent to the protruding portion of the source / drain region 91. Therefore, the body region 80 of the transistor Qgn4 is connected to the source / drain region 91 via the common region 93, and is electrically fixed thereby. Further, a p + -type common region 78 is formed in a part of the source region 75. Therefore, the body region 81 of the transistor Qgn5 is connected to the source region 75 via the common region 78, and is electrically fixed thereby.

  A contact hole CH is formed on the junction between the source / drain region 90 and the common region 92 with an intermediate layer 94 made of aluminum interposed therebetween. A contact hole CH is formed on the junction between the source / drain region 91 and the common region 93 with an intermediate layer 94 made of aluminum interposed therebetween.

  In the embodiment 43, since no contact hole is formed between the gate electrodes 82 and 83, the distance between the gate electrodes 82 and 83 can be shortened. Further, since no contact hole is formed between the gate electrodes 83 and 84, the distance between the gate electrodes 83 and 84 can be shortened.

[Example 44]
FIG. 56 is a plan view showing another configuration of N channel MOS transistors Qgn3 to Qgn5 in the 3-input NAND circuit shown in FIG. Referring to FIG. 56, in this embodiment 44, unlike FIG. 55, an intermediate layer 95 made of polysilicon is formed on drain region 72, source / drain regions 90, 91 and source region 75, respectively. Therefore, when the contact hole CH is formed by etching, even the SOI substrate is not etched.

[Example 45]
FIG. 57 is a circuit diagram showing a structure of a 3-input NAND circuit in a DRAM according to Embodiment 45 of the present invention. Referring to FIG. 57, unlike Embodiment 52, in Embodiment 45, the body region of transistor Qgn3 is connected to the common source / drain region of transistors Qgn4 and Qgn5. The body regions of transistors Qgn4 and Qgn5 are in a floating state. In such a NAND circuit, when the potential of the output node 70 changes to L level, the potential of the body region of the transistor Qgn3 is always the ground potential.

  As apparent from the forty-fifth embodiment, it is sufficient that the body region of the transistor Qgn3 directly connected to the output node 70 is at least electrically fixed. The body region of transistor Qgn3 may be connected to the source / drain electrodes common to transistors Qgn4 and Qgn5, for example, instead of the source region of the transistor Qgn3.

  Also in the forty-fifth embodiment, the potential applied to the body region of transistor Qgn3 is not constant and rises as the potential of output node 70 rises. Therefore, since the substrate effect does not occur in this transistor Qgn3, this 3-input NAND circuit operates at high speed.

[Example 46]
FIG. 58 is a circuit diagram showing a structure of a negative logic 2-input NAND circuit (positive logic 2-input NOR circuit) in the DRAM according to Embodiment 46 of the present invention. Referring to FIG. 58, this 2-input NAND circuit is connected in series between N-channel MOS transistors Qgn6 and Qgn7 connected in parallel between ground node 51 and output node 50, and between output node 50 and the power supply node. P channel MOS transistors Qgp6 and Qgp8 are provided. Input signal IN1 is applied to the gate electrodes of transistors Qgn7 and Qgp6. Input signal IN2 is applied to the gate electrodes of transistors Qgn6 and Qgp7. The output signal OUT is supplied from the output node 50.

  In this NAND circuit, the body regions of transistors Qgn6 and Qgn7 are in a floating state. The body regions of transistors Qgp6 and Qgp7 are each connected to its own drain region. Therefore, a drain potential that increases as the output signal OUT increases is applied to the body region of the transistor Qgp6. A constant ground potential Vss is applied to the drain region of the transistor Qgp7. Therefore, since the threshold value of transistor Qgp6 becomes small, this NAND circuit operates at high speed. Even when the power supply potential Vcc is low, this NAND circuit operates normally.

[Example 47]
FIG. 59 is a circuit diagram showing a structure of a 2-input NAND circuit in a DRAM according to Embodiment 47 of the present invention. Referring to FIG. 59, unlike FIG. 58, in this NAND circuit, power supply potential Vcc is applied to the body region of P channel MOS transistor Qgp6, and this body region is electrically fixed. In this embodiment 47, the substrate effect occurs in the transistor Qgp6. However, as in this embodiment 47, the power supply potential Vcc may be applied to the body region of the transistor Qgp6 instead of its own drain potential.

[Example 48]
FIG. 60 is a cross sectional view, taken along the bit line direction, of a planar type memory cell portion in a DRAM according to Embodiment 48 of the present invention. FIG. 61 is a cross-sectional view of the memory cell portion shown in FIG. 60 cut in the word line direction.

  As shown in FIGS. 60 and 61, a source / drain region 44, a LOCOS oxide film 5, a gate electrode 4, and a cell plate electrode 45 are formed on the SOI substrate 6. The gate electrode 4 and the cell plate electrode 45 are formed in the first interlayer insulating film 33. Here, the two source / drain regions 44, the body region 3 therebetween, and the gate electrode 4 constitute one N-channel MOS transistor. One source / drain region 44, body region 3, and cell plate electrode 45 constitute one N-channel MOS capacitor.

  A source / drain region 44 common to the two transistors is connected to the bit line BL via an intermediate layer 32 such as a polypad. On the first interlayer insulating film 33 and the intermediate layer 32, a second interlayer insulating film 34 is formed. A bit line BL is formed on the second interlayer insulating film 34, and the bit line BL is connected to the intermediate layer 32 through a contact hole. A third interlayer insulating film 35 is formed on the bit line BL, and a stake word line 46 made of aluminum is formed on the third interlayer insulating film 35. The stake word line 46 is connected to the word lines WL constituting the gate electrode 4 through contact holes at regular intervals. Thereby, when a driving voltage is supplied to the word line WL, a signal transmission delay generated in the word line WL is reduced.

  As shown in FIG. 61, a contact region 31 is formed in a part of the body region 3 of the transistor. Therefore, body region 3 is connected to body fixing line 30 via contact region 31 and intermediate layer 32, and is electrically fixed thereby. As described above, since the body region 3 of the transistor constituting the memory cell is electrically fixed, the threshold value of the transistor does not become unstable, and a large amount of leakage current flows between the source and drain. There is no. Therefore, the data holding time in this memory cell becomes long. Even if α particles are incident on the SOI substrate 6 and charges are generated in the silicon substrate 7, the charges do not enter the body region 3. This is because the body region 3 and the silicon substrate 7 are electrically separated by the buried oxide layer 8. In addition, since the body region 3 is extremely thin, charges are hardly generated by the α particles in the body region 3. Therefore, so-called soft errors hardly occur.

[Example 49]
FIG. 62 is a cross sectional view, taken along the bit line direction, of a memory cell portion in a DRAM according to Embodiment 49 of the present invention. FIG. 63 is a cross-sectional view of the memory cell portion shown in FIG. 62 cut in the word line direction. In the embodiment 49 shown in FIGS. 62 and 63, a field shield electrode 47 is formed on the SOI substrate 6 instead of the LOCOS oxide film, unlike FIGS. The field shield electrode 47 is formed in the first interlayer insulating film 33.

  A ground potential Vss or a negative potential is applied to the field shield electrode 47, whereby the portion of the SOI active layer 9 under the field shield electrode 47 is rendered non-conductive. Therefore, these transistors and capacitors are electrically isolated from adjacent elements. As is clear from the embodiment 49, elements such as transistors may be separated not by LOCOS but by other separation methods such as a field shield.

[Example 50]
FIG. 64 is a cross sectional view taken along the bit line direction of the memory cell portion in the DRAM according to the embodiment 50 of the present invention. FIG. 64 shows stacked memory cells separated by the LOCOS oxide film 5.

  Referring to FIG. 64, source / drain regions 44, LOCOS oxide film 5, and gate electrode 4 are formed on SOI substrate 6. Two source / drain regions 44, body region 3 located between them, and gate electrode 4 constitute one N-channel MOS transistor.

  A source / drain region 44 common to the two transistors is connected to the bit line BL via the intermediate layer 32. A storage node 48 and a cell plate electrode 45 are formed on the other source / drain region 44 of the transistor. The storage node 48 and the cell plate 45 constitute a capacitor electrode. The aforementioned N channel MOS transistor and this capacitor constitute a memory cell.

  A contact region (not shown) is formed in a part of the body region 3 of the transistor. Therefore, body region 3 is connected to a body fixing line (not shown) via the contact region, and is electrically fixed thereby.

[Example 51]
FIG. 65 is a cross sectional view taken along the bit line direction of the memory cell portion in the DRAM according to the embodiment 51 of the present invention. FIG. 65 shows stacked memory cells separated by a field shield.

Referring to FIG. 65, in this embodiment 51, unlike FIG. 64, field shield electrode 47 is formed on SOI substrate 6 instead of the LOCOS oxide film. A contact region (not shown) is formed in a part of the body region 3 of the transistor. Therefore, body region 3 is connected to a body fixing line (not shown) through the contact region. A ground potential Vss or V _BB is applied to the body fixing line. Thereby, the body region 3 of the transistor is electrically fixed.

[Example 52]
FIG. 66 is a layout diagram showing the overall structure of a DRAM according to Embodiment 52 of the present invention. Referring to FIG. 66, this DRAM includes four memory cell arrays 11, two row decoders 12, two column decoders 13, and a peripheral circuit 99. Each row decoder 12 is arranged between two memory cell arrays 11. Each column decoder 13 is arranged on one side of the two memory cell arrays 11.

In the embodiment 52, the elements in the memory cell array 11 are separated by LOCOS. A negative potential V _BB is applied to the body region of the N channel MOS transistor constituting each memory cell in the memory cell array, whereby the body region is electrically fixed.

  Row decoder 12 includes a plurality of P-channel MOS transistors and a plurality of N-channel MOS transistors. A power supply potential Vcc is applied to the body region of the P channel MOS transistor in the row decoder 12, whereby the body region is electrically fixed. A ground potential Vss is applied to the body region of the N channel MOS transistor in the row decoder 12, whereby the body region is electrically fixed.

  Column decoder 13 includes a plurality of N-channel MOS transistors. A ground potential Vss is applied to the body region of the N channel MOS transistor in the column decoder 13, whereby the body region is electrically fixed.

  Peripheral circuit 99 arranged between column decoders 13 includes a plurality of P channel MOS transistors. The power supply potential Vcc is applied to the body region of the P channel MOS transistor in the peripheral circuit 99, whereby the body region is electrically fixed. Other peripheral circuit 99 includes a plurality of N channel MOS transistors. Ground potential Vss is applied to the body region of the N-channel MOS transistor in peripheral circuit 99, whereby the body region is electrically fixed.

As described above, the body regions of the MOS transistors included in this DRAM are all electrically fixed. However, power supply potential Vcc is applied to the body region of the P channel MOS transistor. Negative potential _VBB is applied to the body region of the transistors in memory cell array 11 among the N channel MOS transistors, and ground potential Vss is applied to the body regions of the other N channel MOS transistors.

  Therefore, the threshold voltage of the N channel MOS transistor in memory cell array 11 is larger than the threshold voltage of the other N channel MOS transistors. For this reason, the leakage current flowing through the transistors constituting the memory cell is reduced, and the data retention time of the memory cell is increased.

[Example 53]
FIG. 67 is a layout diagram showing the overall structure of a DRAM according to Embodiment 53 of the present invention. Referring to FIG. 67, in the embodiment 53, unlike FIG. 66, the body regions of the N channel MOS transistors in memory cell array 11 are all in a floating state.

  In general, in the memory cell array 11, transistors are arranged more densely than the peripheral circuit 99 or the like. Therefore, even if body fixing lines are arranged in row decoder 12, column decoder 13 and peripheral circuit 99, the layout area hardly increases. In addition, since it is not necessary to arrange body fixing lines in the memory cell array 11, the layout area is the same as the conventional one.

[Example 54]
FIG. 68 is a layout diagram showing the overall structure of a DRAM according to Embodiment 54 of the present invention. Referring to FIG. 68, in this embodiment 54, unlike FIG. 66, elements in memory cell array 11 are separated by a field shield. Note that a negative potential V _BB is applied to the body region of the transistor in the memory cell array 11 as in FIG.

  As described above, if at least the elements in the memory cell array 11 are separated by the field shield, the body region of the transistor in the memory cell array 11 is electrically fixed without providing a body fixing line or the like in the memory cell array 11 in particular. can do. Therefore, the layout area of the DRAM according to the embodiment 54 is smaller than that in the embodiment 52. Although the layout area according to the embodiment 54 is almost the same as that of the embodiment 53, the body region of the transistors in the memory cell array 11 is electrically fixed. Leakage current does not flow. Therefore, the data retention time in the embodiment 54 is longer than that in the embodiment 53.

[Example 55]
FIG. 69 is a layout diagram showing the overall structure of a DRAM according to Embodiment 55 of the present invention. Referring to FIG. 69, in this embodiment 55, unlike FIG. 68, ground potential Vss is applied to the body region of the N channel MOS transistor in memory cell array 11, whereby the body region is electrically fixed. . Therefore, in this embodiment 55, the ground potential Vss is applied to the body regions of all N channel MOS transistors, and the power supply potential Vcc is applied to the body regions of all P channel MOS transistors. As described above, the ground potential Vss may be applied to the body region of the transistor in the memory cell array 11.

[Example 56]
FIG. 70 is a conceptual diagram showing a DRAM according to Embodiment 56 of the present invention. Referring to FIG. 70, this DRAM includes a plurality of N channel MOS transistors and a plurality of P channel MOS transistors. The ground potential Vss is applied to the body regions of some of the N channel MOS transistors, and the negative potential V _BB is applied to the body regions of the other N channel MOS transistors. The power supply potential Vcc is applied to the body regions of all the P channel MOS transistors.

Therefore, in the embodiment 56, the body regions of all the MOS transistors are electrically fixed. Further, the threshold voltage of the transistor having the body region to which the negative potential V _BB is applied becomes larger than the threshold voltage of the transistor having the body region to which the ground potential Vss is applied. Has different threshold voltages.

[Example 57]
FIG. 71 is a conceptual diagram showing a DRAM according to Embodiment 57 of the present invention. Referring to FIG. 71, the embodiment 57 differs from FIG. 70 in that the body regions of some of the N channel MOS transistors are in a floating state. Therefore, it is not necessary to provide a body fixing line or the like in the region of the N-channel MOS transistor having the floating body region, so that the layout area is smaller than that in the above-described embodiment 56.

[Example 58]
FIG. 72 is a conceptual diagram showing a DRAM according to Embodiment 58 of the present invention. Referring to FIG. 72, in the embodiment 58, unlike FIG. 70, the body regions of all the P channel MOS transistors are in a floating state. Therefore, in the embodiment 58, the body regions of all N channel MOS transistors are electrically fixed, and the body regions of all P channel MOS transistors are in a floating state. In general, the breakdown voltage between the source and drain of an N channel MOS transistor having a body region in a floating state is lower than that of a P channel MOS transistor. However, in this embodiment 58, the body region of the N channel MOS transistor is electrically fixed. Therefore, the withstand voltage between the source and the drain becomes as high as that of the P-channel MOS transistor. For this reason, the breakdown voltage between the source and drain of all the transistors is increased, and the body region of the P channel MOS transistor is not electrically fixed. Therefore, it is not necessary to provide a body fixing line or the like in the region of the P channel MOS transistor. Therefore, the layout area of the DRAM according to the embodiment 58 is smaller than that of the embodiment 56.

Although the ground potential Vss to the body region of the part in this embodiment 58 of the N-channel MOS transistor is given a negative potential V _BB may be provided in place of the potential Vss.

[Example 59]
FIG. 73 is a conceptual diagram showing a DRAM according to Embodiment 59 of the present invention. Referring to FIG. 73, in this embodiment 59, unlike FIG. 72, the body regions of some N channel MOS transistors are also in a floating state. Therefore, in this embodiment 59, the body regions of some N channel MOS transistors are fixed, and the body regions of all P channel MOS transistors are in a floating state. According to the embodiment 59, it is not necessary to arrange a body fixing line or the like in the region of a part of the N channel MOS transistors.

[Example 60]
FIG. 74 is a conceptual diagram showing a DRAM according to Embodiment 60 of the present invention. Referring to FIG. 74, in this embodiment 60, all P channel MOS transistors are isolated by LOCOS. Some N-channel MOS transistors are separated by LOCOS, and other N-channel MOS transistors are separated by field shield (FS). Negative potential _VBB is applied to the body region of the N channel MOS transistor separated by the field shield, and ground potential Vss is applied to the body region of the N channel MOS transistor separated by LOCOS. The power supply potential Vcc is applied to the body regions of all the P channel MOS transistors. The ground potential Vss may also be applied to the body region of the N-channel MOS transistor separated by the field shield.

[Example 61]
FIG. 75 is a conceptual diagram showing a DRAM according to Embodiment 61 of the present invention. Referring to FIG. 75, in this embodiment 61, some P channel MOS transistors are separated by a field shield, and other P channel MOS transistors are separated by LOCOS. All N channel MOS transistors are separated by LOCOS. The power supply potential Vcc is applied to the body regions of all the P channel MOS transistors. The body regions of some N channel MOS transistors are in a floating state, and the ground potential Vss is applied to the body regions of other N channel MOS transistors. Therefore, in this embodiment 61, the body regions of some N channel MOS transistors are electrically fixed, and the body regions of all P channel MOS transistors are electrically fixed.

[Example 62]
FIG. 76 is a conceptual diagram showing a DRAM according to Embodiment 62 of the present invention. Referring to FIG. 76, the DRAM includes a plurality of P channel MOS transistors and a plurality of N channel MOS transistors. Some P-channel MOS transistors have a threshold voltage Vthp1, and other P-channel MOS transistors have a threshold voltage Vthp2. All N channel MOS transistors have a threshold voltage Vthn. Therefore, these P channel MOS transistors have two kinds of threshold voltages. These N channel MOS transistors have one kind of threshold voltage. In this way, two types of threshold voltages may be given to the same conductive channel type MOS transistor.

  In order to give two types of threshold voltages to the transistors, two types of potentials may be applied to the body regions of the transistors. This is because the threshold voltage varies depending on the substrate effect when the potential applied to the body region is different.

  In addition, as shown in FIG. 77, the n-type body region of P channel MOS transistor 3 may be doped with impurities having different concentrations. As a result, regions having different impurity concentrations are formed in the vicinity of the surface of the body region 3, so that these two P-channel MOS transistors have different threshold voltages.

  Further, the gate electrodes 4 of these transistors may be formed of different materials. In this case, the threshold voltages of these transistors differ from each other in accordance with the work function specific to these materials.

  Alternatively, a part of the SOI active layer 9 may be etched to form a thin part and a thick part in the SOI active layer 9, and a transistor may be formed thereon. The transistor formed on the thin SOI active layer 9 is close to a so-called fully depleted transistor. In general, the threshold voltage of a fully depleted transistor is smaller than the threshold voltage of a partially depleted transistor. Therefore, the transistor formed on the thin SOI active layer 9 has a smaller threshold voltage than the transistor formed on the thick SOI active layer 9.

  Further, the threshold voltage of the transistor may be changed by changing the thickness of the gate insulating film or changing the material of the gate insulating film.

  In this embodiment 62, the P channel MOS transistor has two types of threshold voltages, but the N channel MOS transistor may have two types of threshold voltages. Further, the transistor may have three or more threshold voltages.

  As described above, if a large number of transistors in the DRAM formed on the SOI substrate have two or more threshold voltages, the DRAM operates more stably.

[Example 63]
FIG. 78 is a conceptual diagram showing a DRAM according to Embodiment 63 of the present invention. Referring to FIG. 78, in the embodiment 63, the body region of the transistor having a short gate length is electrically fixed, and the body region of the transistor having a short gate length is electrically floated. In general, a transistor having a long gate length has a higher source-drain breakdown voltage than a transistor having a short gate length. Therefore, when the body region of a transistor having a short gate length is fixed, the threshold voltage is approximately the same as that of a transistor having a body region in a floating state and having a long gate length. In addition, in this case, since it is not necessary to dispose a body fixing line or the like in the transistor region having a long gate length, the layout area is not so large.

[Example 64]
FIG. 79 is a cross sectional view showing the structure of the sense amplifier in the DRAM according to the embodiment 64 of the present invention. Referring to FIG. 79, in this embodiment 64, unlike FIG. 6, SOI active layer 9 is etched in a mesa shape, and LOCOS oxide film 5 of FIG. 6 is not formed.

  80 and 81 are cross-sectional views showing the structure of the memory cell in the DRAM shown in FIG. This memory cell has a planar structure. As shown in FIGS. 80 and 81, the SOI active layer 9 is etched in a mesa shape unlike FIGS.

Such a structure is manufactured through the following processes, for example.
After the source / drain region 44, the contact region 31 and the like are formed in the SOI active layer 9, all the portions other than the element active region of the SOI active layer 9 are etched, thereby making the element active region mesa. Next, a gate oxide film is formed so as to cover the mesa element active region. A gate electrode 4 is formed on the gate oxide film.

  In the case of the LOCOS isolation shown in FIG. 6, when the SOI active layer 9 is thermally oxidized to form the LOCOS oxide film 5, boron implanted into the P-type body region 3 is absorbed into the LOCOS oxide film 5. There is a problem. When boron in the body region 3 is absorbed into the LOCO oxide film 5, the impurity concentration in the edge portion 3a of the body region 3 is lowered, and thereby a parasitic MOS transistor having a low threshold value is formed in the edge portion 3a. . Therefore, a so-called hump phenomenon appears in the drain current-gate voltage characteristics of the transistor Qn1. As another cause of the appearance of such a hump phenomenon, it can be considered that a bird's beak peculiar to LOCOS isolation gives stress to the thin SOI active layer 9.

  On the other hand, in the case of the mesa separation shown in FIGS. 79 to 81, the impurity concentration of the edge portion in the body region 3 does not decrease. This is because the SOI active layer 9 is not thermally oxidized and the body region 3 is covered with the gate oxide film and the gate electrode 4. Further, since an oxide film, a nitride film or the like is deposited as the interlayer insulating film 33 by the CVD method or the like, no stress is generated at the edge portion of the body region 3. Therefore, no hump phenomenon appears in the drain current-gate voltage characteristics of this transistor. Therefore, this transistor operates more stably.

[Example 65]
FIG. 82 is a cross sectional view showing the structure of the memory cell in the DRAM according to the embodiment 65 of the present invention. Referring to FIG. 82, this memory cell has a stack structure. Further, unlike FIG. 64, the SOI active layer 9 is etched in a mesa shape. As is clear from Example 64 and Example 65 above, mesa separation may be employed instead of LOCOS separation.

[Example 66]
FIG. 83 is a conceptual diagram showing a part of a DRAM according to Embodiment 66 of the present invention. In the embodiment described above, the potential of the silicon substrate 7 is not particularly mentioned, but it is preferable that a predetermined substrate potential _VBB is supplied to the silicon substrate 7 as shown in FIG. This substrate potential V _BB is generated by the substrate potential generator 100.

In the SOI substrate 6, the silicon substrate 7 is separated from the SOI active layer 9 by the buried oxide layer 8, but the SOI active layer 9 is coupled to the silicon substrate 7 through a parasitic capacitance. Therefore, when the silicon substrate 7 is in an electrically floating state, the potential of the body region 3 tends to become unstable as the potential of the silicon substrate 7 changes. According to the embodiment 66, a predetermined substrate potential V _BB is supplied to the silicon substrate 7 and is electrically fixed thereby, so that the potential of the silicon substrate 7 does not fluctuate. Therefore, semiconductor elements such as transistors formed on the SOI substrate 6 operate stably.

[Example 67]
FIG. 84 is a conceptual diagram showing part of a DRAM according to Embodiment 67 of the present invention. As shown in FIG. 84, in the embodiment 67, unlike FIG. 83, the silicon substrate 7 is connected to the ground node 51. Accordingly, since the ground potential Vss is supplied to the silicon substrate 7, the silicon substrate 7 is electrically fixed. Therefore, as in the above-described embodiment 66, the semiconductor elements such as transistors formed on the SOI substrate 6 operate stably. As is apparent from the embodiment 67, the potential of the silicon substrate 7 is not particularly limited, for example, not only the substrate potential _VBB but also the ground potential Vss may be applied.

[Example 68]
FIG. 85 is a perspective view showing a specific configuration for supplying substrate potential _VBB to silicon substrate 7 as shown in FIG. Referring to FIG. 85, in Example 68, substrate potential generator 100 is formed on SOI substrate 6. A bonding pad 102 is formed on the SOI substrate 6, and a substrate potential V _BB is supplied from the substrate potential generator 100 to the bonding pad 102.

This SOI substrate 6 is placed on a die pad 106 laid in the package. The bonding pad 102 is connected to the die pad 106 via a wire 104. Since the back surface of the SOI substrate 6 is in contact with the die pad 106, the substrate potential V _BB generated by the substrate potential generator 100 is supplied to the silicon substrate 7 through the bonding pad 102, the wire 104 and the die pad 106. Thereby, the silicon substrate 7 is electrically fixed.

[Example 69]
FIG. 86 is a perspective view showing a specific configuration for supplying ground potential Vss to silicon substrate 7 as shown in FIG. The bonding pad 102 in FIG. 86 is for supplying the ground potential Vss to the circuit formed on the SOI substrate 6. The bonding pad 102 is connected to a lead frame 110 to which a ground potential Vss is supplied via a wire 104.

  Furthermore, in the embodiment 69, the die pad 106 is connected to the lead frame 110 through the wire 104. Therefore, the ground potential Vss is supplied to the silicon substrate 7 via the lead frame 110, the wire 104, and the die pad 106. Thereby, the silicon substrate 7 is electrically fixed.

[Example 70]
FIG. 87 is a perspective view showing another example for supplying the ground potential Vss to the silicon substrate 7. As shown in FIG. 87, in this embodiment 70, the SOI substrate 6 is placed on a substantially L-shaped die pad 112. A bonding pad 102 for supplying a ground potential Vss to a circuit on the SOI substrate 6 is connected to the die pad 112 via a wire 104. Therefore, the ground potential Vss is supplied to the bonding pad 102 via the die pad and the wire 104 and also supplied to the silicon substrate 7 via the die pad 112. Thereby, the silicon substrate 7 is electrically fixed.

[Example 71]
FIG. 88 is a cross-sectional view showing another example for supplying substrate potential _VBB to silicon substrate 7 as shown in FIG. As shown in FIG. 88, in this example 71, a contact groove 118 is formed in the SOI substrate 6. The groove 118 penetrates the buried oxide layer 8 and reaches the silicon substrate 7. A contact hole CH is formed on the groove 118, and a substrate fixing line 114 is further formed. The substrate fixing line 114 is connected to the silicon substrate 7 through the contact hole CH.

In this embodiment 71, the substrate potential V _BB generated by the substrate potential generator 100 is supplied to the substrate fixing line 114. Therefore, the substrate potential V _BB is supplied to the silicon substrate 7 via the substrate fixing line 114. Thereby, the silicon substrate 7 is electrically fixed.

[Example 72]
FIG. 89 is a cross-sectional view showing another example for supplying substrate potential _VBB or ground potential Vss to silicon substrate 7 as shown in FIG. 83 or FIG. As shown in FIG. 89, in the embodiment 72, unlike FIG. 88, the substrate fixing line 114 is connected to the bonding pad. The bonding pad 102 is formed on the SOI substrate 6 as shown in FIG. 86 or 87. This bonding pad 102 ground potential Vss or the substrate potential V _BB is supplied. Therefore, the potential Vss or V _BB of the bonding pad 102 is supplied to the silicon substrate 7 via the substrate fixing line 114. Thereby, the silicon substrate 7 is electrically fixed.

[Example 73]
90 is a circuit diagram showing a partial configuration of a memory cell, a sense amplifier and an input / output circuit in a DRAM according to Embodiment 73 of the present invention. Referring to FIG. 90, unlike FIG. 12, in Example 73, boosted sense ground potential generator 120 is provided, and boosted sense ground potential V _BSG generated by generator 120 is used as the source electrode of transistors Qs1 and Qs2. Is given to.

FIG. 91 is a timing chart showing the operation of this DRAM. In this timing chart, unlike FIG. 3, the potential of one bit line is lowered only to the boosted sense ground potential V _BSG as shown in FIG. 91 (j). This potential V _BSG is higher than the ground potential Vss by ΔV.

Although the gate potential of the transfer gate Qm in the non-selected memory cell is 0 V (L level), according to the embodiment 73, the source potential of the transfer gate Qm decreases only to the boosted sense ground potential V _BSG . Therefore, the source potential is higher than the gate potential by ΔV. Therefore, the transfer gate Qm is more strongly non-conductive than the above-described embodiment. In other words, the threshold value of the transfer gate Qm is substantially increased. Therefore, in the non-selected memory cell 27, the disturb sub-threshold leakage current is greatly suppressed.

  According to such a boosted sense ground method, the threshold can be substantially increased without doping impurities in the body region of the transfer gate Qm, so that carrier mobility is reduced by doping. Absent. In addition, since such a doping process is not required, the manufacturing process is simplified.

In the above described embodiment, although the body region of the N-channel MOS transistors are supplied with a ground potential Vss or a negative potential V _BB, without being limited to the potential, the following source potential of the N-channel MOS transistor Any potential may be applied as long as it is present. Further, the power supply potential Vcc is mainly applied to the body region of the P channel MOS transistor. Similarly, any potential may be applied as long as it is higher than the source potential of the P channel MOS transistor. The present invention is not limited to the above-described embodiments, and can be carried out in a mode in which various modifications, improvements, variations and the like are added.

1 is a circuit diagram showing a partial configuration of a memory cell array, a sense amplifier, and an input / output circuit in a DRAM according to Embodiment 1 of the present invention; It is a block diagram which shows the whole structure of DRAM. 2 is a timing chart showing an operation of the DRAM shown in FIG. 1. 6 is a timing chart showing another operation of the DRAM shown in FIG. 1. FIG. 2 is a plan view showing a configuration of a sense amplifier and a precharge circuit shown in FIG. 1. FIG. 6 is a cross-sectional view of the sense amplifier shown in FIG. 5 taken along line 6-6. FIG. 2 is a plan view showing a general configuration of a transistor in the bit line selection circuit, the column selection circuit, or the memory cell shown in FIG. It is a top view which shows the structure of the sense amplifier and precharge circuit in DRAM by Example 2 of this invention. It is a top view which shows the structure of the sense amplifier and precharge circuit in DRAM by Example 3 of this invention. FIG. 10 is a circuit diagram showing a partial configuration of a memory cell array, a sense amplifier, and an input / output circuit in a DRAM according to Embodiment 4 of the present invention. FIG. 10 is a circuit diagram showing a partial configuration of a memory cell array, a sense amplifier, and an input / output circuit in a DRAM according to Embodiment 5 of the present invention. FIG. 10 is a circuit diagram showing a partial configuration of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 6 of the present invention; FIG. 13 is a plan view showing configurations of a sense amplifier and a precharge circuit shown in FIG. 12. It is a top view which shows the structure of the sense amplifier and precharge circuit in DRAM by Example 7 of this invention. It is a top view which shows the structure of the sense amplifier and precharge circuit in DRAM by Example 8 of this invention. FIG. 20 is a circuit diagram showing a partial configuration of a memory cell array, sense amplifiers and input / output circuits in a DRAM according to Embodiment 9 of the present invention; It is a circuit diagram showing a partial configuration of a memory cell array, a sense amplifier, and an input / output circuit in a DRAM according to Embodiment 10 of the present invention. It is a circuit diagram showing a partial configuration of a memory cell array, a sense amplifier, and an input / output circuit in a DRAM according to Embodiment 11 of the present invention. It is a circuit diagram showing a partial configuration of a memory cell array, a sense amplifier, and an input / output circuit in a DRAM according to Embodiment 12 of the present invention. It is a circuit diagram which shows the structure of the word line drive circuit in DRAM by Example 13 of this invention. It is a circuit diagram which shows the structure of the word line drive circuit in DRAM by Example 14 of this invention. FIG. 22 is a plan view showing a configuration of an N-channel MOS transistor in the word line drive circuit shown in FIG. 21. FIG. 22 is a circuit diagram showing a configuration of a boost signal predecode circuit in a DRAM according to Embodiment 15 of the present invention. FIG. 22 is a circuit diagram showing a configuration of a boost signal predecode circuit in a DRAM according to Embodiment 16 of the present invention. It is a top view which shows the structure of the N channel MOS capacitor in DRAM by Example 17 of this invention. It is a top view which shows the structure of the P channel MOS capacitor in DRAM by Example 18 of this invention. It is a top view which shows the structure of the N channel MOS capacitor in DRAM by Example 19 of this invention. It is a top view which shows the structure of the P channel MOS capacitor in DRAM by Example 20 of this invention. FIG. 38 is a circuit diagram showing an overall configuration of a boosted power generation circuit in a DRAM according to Embodiment 21 of the present invention. FIG. 22 is a circuit diagram showing structures of an output preamplifier and a write circuit in a DRAM according to Embodiment 22 of the present invention. It is a circuit diagram which shows the structure of the input / output line precharge circuit and input / output line equalize circuit in DRAM by Example 23 of this invention. FIG. 22 is a circuit diagram showing a configuration of a row address buffer in a DRAM according to Embodiment 24 of the present invention. FIG. 27 is a circuit diagram showing a structure of a column address buffer in a DRAM according to Embodiment 25 of the present invention. It is a circuit diagram which shows the structure of the column address buffer in DRAM by Example 26 of this invention. FIG. 38 is a circuit diagram showing a structure of a column address buffer in a DRAM according to Embodiment 27 of the present invention. FIG. 38 is a circuit diagram showing a configuration of a column address buffer in a DRAM according to Embodiment 28 of the present invention. FIG. 38 is a circuit diagram showing a structure of a clock input buffer in a DRAM according to Embodiment 29 of the present invention. FIG. 38 is a circuit diagram showing a configuration of a clock input buffer in a DRAM according to Embodiment 30 of the present invention. FIG. 38 is a circuit diagram showing a configuration of a clock input buffer in a DRAM according to Embodiment 31 of the present invention. It is a circuit diagram which shows the structure of the clock input buffer in DRAM by Example 32 of this invention. It is a circuit diagram which shows the structure of the sense amplifier drive circuit in DRAM by Example 33 of this invention. 42 is a timing chart showing an operation of the sense amplifier driving circuit shown in FIG. 41. It is a circuit diagram which shows the structure of the CAT circuit in DRAM by Example 34 of this invention. 44 is a timing chart showing an operation of the CAT circuit shown in FIG. FIG. 38 is a circuit diagram showing a configuration of an NN buffer in a DRAM according to Embodiment 35 of the present invention. It is a circuit diagram which shows the structure of the NN buffer in DRAM by Example 36 of this invention. FIG. 43 is a circuit diagram showing a configuration of a NAND circuit in a DRAM according to Embodiment 37 of the present invention. FIG. 48 is a plan view showing a partial configuration of the NAND circuit shown in FIG. 47; It is a top view which shows a partial structure of the NAND circuit in DRAM by Example 38 of this invention. It is a top view which shows a partial structure of the NAND circuit in DRAM by Example 39 of this invention. It is a top view which shows a partial structure of the NAND circuit in DRAM by Example 40 of this invention. It is a top view which shows the structure of the NAND circuit in DRAM by Example 41 of this invention. 53 is a plan view showing a partial configuration of the NAND circuit shown in FIG. 52. FIG. It is a top view which shows a partial structure of the NAND circuit in DRAM by Example 42 of this invention. It is a top view which shows a partial structure of the NAND circuit in DRAM by Example 43 of this invention. It is a top view which shows a partial structure of the NAND circuit in DRAM by Example 44 of this invention. It is a circuit diagram which shows the structure of the NAND circuit in DRAM by Example 45 of this invention. It is a circuit diagram which shows the structure of the NAND circuit in DRAM by Example 46 of this invention. It is a circuit diagram which shows the structure of the NAND circuit in DRAM by Example 47 of this invention. It is sectional drawing which shows the structure of the memory cell in DRAM by Example 48 of this invention. FIG. 61 is a cross-sectional view of the memory cell shown in FIG. 60 taken along the word line direction. It is sectional drawing which shows the structure of the memory cell in DRAM by Example 49 of this invention. FIG. 63 is a cross-sectional view of the memory cell shown in FIG. 62 taken along the word line direction. It is sectional drawing which shows the structure of the memory cell in DRAM by Example 50 of this invention. It is sectional drawing which shows the structure of the memory cell in DRAM by Example 51 of this invention. FIG. 44 is a layout diagram showing an overall structure of a DRAM according to Embodiment 52 of the present invention. FIG. 44 is a layout diagram showing the overall structure of a DRAM according to Embodiment 53 of the present invention. FIG. 48 is a layout diagram showing the overall structure of a DRAM according to Embodiment 54 of the present invention. FIG. 55 is a layout diagram showing an overall structure of a DRAM according to Embodiment 55 of the present invention. It is a conceptual diagram which shows DRAM by Example 56 of this invention. It is a conceptual diagram which shows DRAM by Example 57 of this invention. It is a conceptual diagram which shows DRAM by Example 58 of this invention. It is a conceptual diagram which shows DRAM by Example 59 of this invention. It is a conceptual diagram which shows DRAM by Example 60 of this invention. It is a conceptual diagram which shows DRAM by Example 61 of this invention. It is a conceptual diagram which shows DRAM by Example 62 of this invention. FIG. 77 is a cross sectional view showing two P-channel MOS transistors in the DRAM shown in FIG. 76. It is a conceptual diagram which shows DRAM by Example 63 of this invention. It is sectional drawing which shows the sense amplifier in DRAM by Example 64 of this invention. FIG. 80 is a cross-sectional view showing a memory cell of the DRAM shown in FIG. 79. FIG. 81 is a cross-sectional view of the memory cell shown in FIG. 80 cut in the word line direction. It is sectional drawing which shows the structure of the memory cell in DRAM by Example 65 of this invention. It is a conceptual diagram which shows a partial structure of DRAM by Example 66 of this invention. It is sectional drawing which shows a partial structure of DRAM by Example 67 of this invention. It is a perspective view which shows the structure of DRAM by Example 68 of this invention. It is a perspective view which shows the structure of DRAM by Example 69 of this invention. It is a perspective view which shows the structure of DRAM by Example 70 of this invention. It is a conceptual diagram which shows a partial structure of DRAM by Example 71 of this invention. It is a conceptual diagram which shows a partial structure of DRAM by Example 72 of this invention. FIG. 48 is a circuit diagram showing a partial configuration of a memory cell, a sense amplifier, and an input / output circuit in a DRAM according to Embodiment 73 of the present invention. 91 is a timing chart showing an operation of the DRAM shown in FIG. 90. It is a top view which shows the structure of the conventional N channel MOS transistor formed on the SOI substrate. FIG. 93 is a cross-sectional view of the transistor shown in FIG. 92 taken along line 93-93. FIG. 93 is a cross-sectional view of the transistor shown in FIG. 92 taken along line 94-94.

Explanation of symbols

  1, 54, 75 Source region, 2, 52, 72 Drain region, 3, 57, 58, 79, 80, 81 Body region, 53, 65, 73, 74, 90, 91 Source / drain region, 4, 44, 59, 60, 82, 83, 84 Gate electrode, 5 LOCOS oxide film, 6 SOI substrate, 7 silicon substrate, 8 buried oxide layer, 9 SOI active layer, 10 DRAM, 11 memory cell array, 12 row decoder, 13 column decoder , 14 sense amplifier group, 15 input / output circuit, 16 address buffer, 17 input buffer, 18 output buffer, 19 clock generation circuit, 20 sense amplifier, 21A, 21B sense amplifier drive line, 23 precharge circuit, 24 bit line equalize line 25 bit line precharge line, 26A, 26B bit line selection circuit, 27 Memory cell, 28 dummy cell, 29 column selection circuit, 30, 30A, 30B, 30C body fixing line, 31 contact region, 32, 61, 62, 67, 68, 85, 86, 94, 95 intermediate layer, 38, 55, 56, 66, 76, 77, 78, 92, 93 Common area, 40 output preamplifier, 41 write circuit, 42 I / O line precharge circuit, 50, 70 output node, 51, 71 ground node, 100 substrate potential generator .

Claims (6)

A plurality of word lines arranged along the row direction;
A plurality of bit line pairs arranged along the column direction;
Provided corresponding to one of intersections of the plurality of word lines and the plurality of bit line pairs, each connected between storage means for storing data and one bit line of the storage means and the corresponding bit line pair A plurality of memory cells including a first MOS transistor formed;
Row selection means for selecting one of the plurality of word lines;
Column selecting means including a plurality of second MOS transistors and selecting one of the plurality of bit line pairs;
A plurality of precharge means provided corresponding to the plurality of bit line pairs, each including a third MOS transistor, and precharging the corresponding bit line pair to a predetermined potential;
A semiconductor memory device comprising a plurality of sense amplifiers provided corresponding to the plurality of bit line pairs, each including a fourth MOS transistor and amplifying a potential difference between the corresponding bit line pairs. ,
The plurality of word lines, the plurality of bit line pairs, the plurality of memory cells, the row selection unit, the column selection unit, the plurality of precharge units, and the plurality of sense amplifier units. Formed on the SOI substrate,
Each of the plurality of first to fourth MOS transistors has a source region, a drain region, and a body region located between the source region and the drain region,
Of the plurality of first to fourth MOS transistors, a body region of a MOS transistor having a source region or a drain region connected to any one of the plurality of bit line pairs is electrically fixed. A semiconductor memory device.   2. The semiconductor memory device according to claim 1, wherein the MOS transistor having the fixed body region is the first MOS transistor.   2. The semiconductor memory device according to claim 1, wherein the MOS transistor having the fixed body region is the second MOS transistor.   2. The semiconductor memory device according to claim 1, wherein the MOS transistor having the fixed body region is the third MOS transistor.   2. The semiconductor memory device according to claim 1, wherein the MOS transistor having the fixed body region is the fourth MOS transistor. Multiple bit line pairs;
A plurality of sense amplifier means each provided corresponding to two bit line pairs of the plurality of bit line pairs, and amplifying a potential difference between one bit line pair of the corresponding two bit line pairs;
A plurality of MOS transistor pairs provided corresponding to the plurality of bit line pairs, each connected between a corresponding bit line pair and a corresponding sense amplifier means;
The two bit line pairs are semiconductor memory devices arranged on both sides of corresponding sense amplifier means,
The plurality of bit line pairs, the plurality of sense amplifier means, and the plurality of MOS transistor pairs are formed on an SOI substrate,
A semiconductor memory device, wherein a body region located between a source region and a drain region of at least one MOS transistor of the plurality of MOS transistor pairs is electrically fixed.

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