JPS6212598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active booster circuit used in a semiconductor memory device.

Integrated circuit technology has made remarkable progress in recent years, and large-capacity LSIs (Large-Scale Integrated Circuits) have been developed, particularly in the field of storage devices. Many new technological developments have made this possible. Specifically, examples of dynamic memory devices include one-transistor/one-capacitor memory cells, dynamic ratioless amplifiers using flip-flops, and memory cells with a two-layer polysilicon structure. Using this dynamic ratioless amplifier, for example, 64K bits of RAM can be
An active booster circuit was newly introduced in the production of (random access memory). That is, the use of a dynamic ratioless amplifier has the advantage of reducing power consumption, but has the disadvantage that the logic "1" level of sensed information is reduced. If this reduced level is rewritten into the memory cell, a malfunction may occur the next time the memory is accessed. For this reason, an active booster circuit was provided to restore the dropped logic "1" level to its original level, guarantee a high potential for the rewrite level, and boost only the digit line on the "1" level side. It is.

FIG. 1 shows a conventional example of a set of cells and a sense system of a MOS dynamic RAM using such an active booster circuit. In the figure, both ends of a dynamic ratioless sense amplifier 1 using a flip-flop are connected to digit lines A and B connected to each memory cell group 2 and 3. are provided with active booster circuits 4 and 5, respectively. The above digit line A,
B is a MOS operated by precharge signal φp
Transistors Q ₁ and Q ₂ reduce the potential Vc of the power supply Vcc
It is precharged as shown in FIG. 2e.
At this time, nodes (intersection points) C and D in active booster circuits 4 and 5 are both MOS transistors Q ₃ ,
It is precharged to the potential of Ac-Vt through Q ₄ (Figure 2 f). Here, Vt is the above transistor
This is the threshold voltage of Q ₃ and Q ₄ .

Next, data is read out from memory cell groups 2 and 3 to digit lines A and B, and sense amplifier 1
When the MOS transistors Q ₇ to _{Q 10} are operated by the sense amplifier drive signal φSA and the clock signal φO, one of the two digit lines A and B becomes “” by the data from the memory cell groups 2 and 3. 1” level, and the other becomes “0” level. Now, assume that digit line A is at the "1" level and digit line B is at the "0" level. Then, the potential of the digit line B becomes 0V as shown in FIG. 2e, and the potential of the node D is also discharged to the potential of 0V as shown in FIG. 2f. On the other hand, the potential of the digit line A is slightly discharged during sensing, as shown in FIG. 2f, and becomes slightly lower than the Vc potential. Here, when the boost clock signal φ shown in FIG. 2d goes to the "1" level, the transistor _Q3 is in the cut-off state, so the node C is connected to the capacitor.
It is bootstrapped by the capacitive coupling of _C1 , and its potential gradually becomes higher than the potential Vc, as shown in FIG. 2f. On the other hand, node D is held at 0V since said transistor _Q4 is conducting (FIG. 2f). In this way, the MOS transistor _Q6 is turned off and the MOS transistor _Q5 is turned on for triode operation, thereby restoring the slightly lowered potential of the digit line A to the power supply potential Vc (FIG. 2e). Thereafter, the levels of the digit lines A and B are read out through an I/O (input/output) gate controlled by the output of a column decoder (not shown).

However, if the potential of the digit line A drops considerably after sensing as shown in FIG. 2g, that is, if it drops by more than an amount corresponding to the threshold voltage Vt of the transistor _Q3 , the transistor _Q3 will no longer be in the cut-off state. Therefore, even if the capacitor _C1 is used for bootstrapping, all the charges will escape to the digit line A through the transistor _Q3 . Therefore, the node C remains at a potential lower than the power supply voltage Vc as shown in Fig. 2h, and the transistor
_Q5 will be cut off and the potential level of digit line A will not be restored as shown in FIG. 2g. Actually, digit line A
decreases by approximately 1.5V when the power supply potential Vc = 5V due to coupling with the integrated circuit board, noise, etc. In such situations, active boost circuits 4, 5 are often of no practical use.
Therefore, when such active booster circuits 4 and 5 are used, the digit lines A,
A malfunction occurs when rewriting the data read to B, causing a system error.

The present invention was made in view of the above circumstances, and
An object of the present invention is to provide an active booster circuit that can perform an effective boosting operation by configuring the active booster circuit used in a dynamic RAM with MOS transistors having different threshold voltages.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Figure 3 shows N-channel MOS dynamics.
A part of the memory peripheral circuit in which this circuit is applied to RAM, that is, one row of cells out of many rows, a sense system, and multiple memory cells connected to digit lines A and B and one dummy cell. This shows a state in which memory cell groups 2 and 3 having memory cells 2 and 3 are connected.
The dotted lines in the figure indicate that they are also connected to memory cells and sense systems in other rows. The active booster circuits 11 and 12 of the present invention also have digit lines A and B connecting the memory cells 2 and 3 and the dynamic ratioless sense amplifier 10 that senses the read information from the memory cells 2 and 3, as described above. It is connected to the. Connected to these digit lines A and B are one ends of input/output transistors Q ₂₁ and Q ₂₂ that are controlled by an output signal from a column decoder (not shown), and these transistors Q ₂₁ and Q ₂₂
Signal input or output (I/O,
/O signal) is performed. Sense amplifier 1 above
0 is constructed using a flip-flop made up of two MOS transistors Q ₇ and Q ₈ , and this flip-flop is operated by a sense amplifier drive signal φSA. Both ends of this flip-flop are connected to the digit lines A and B via gate transistors Q ₉ and Q ₁₀ which are put into a triode operating state by a clock signal φo input to the gates.

Further, the active booster circuits 11 and 12 are operated by a precharge signal φp input to their gates,
MOS transistor for precharging to precharge digit lines A and B to a predetermined level
The transistors have transistors Q ₁₁ and Q ₁₂ whose sources are connected to the digital lines A and B, respectively, and whose drains are connected to the power supply Vcc via a MOS transistor Q ₁₃ operated by a clock signal _φ1 . The transistors Q ₁₁ to _{Q 13} described above are constituted by ordinary enhancement mode MOS transistors, and the threshold voltage thereof is expressed as V _TO . The active booster circuits 11 and 12 have their drains connected to the power supply Vcc, their sources connected to the digit lines A and B, and their gates connected to the boost clock signal φ via bootstrap capacitors C ₁ and C ₂ . The low threshold voltage V _T1 (where V _TO
≧V _T1 >0) MOS transistors Q ₁₄ and Q ₁₅ ,
A high threshold voltage whose drain is connected to the clock signal φ input terminal via the capacitors C ₁ and C ₂ , whose source is connected to the digit lines A and B, and whose gate is connected to the power supply Vcc via the transistor Q ₁₃ . It has MOS transistors Q ₁₆ and Q ₁₇ with a voltage of V _T2 (where V _T2 >V _TO ). Here, a node C represents a contact point between the transistor Q ₁₆ and the capacitor C ₁ , a node D represents a contact point between the transistor Q ₁₇ and the capacitor C ₂ , and a node E represents a connection point between the transistor Q ₁₃ and the transistors Q ₁₁ and Q ₁₂ . Note that the clock signals φ, φ ₁ , φ ₀ , precharge signal φp and sense amplifier drive signal φSA are derived from a clock generator (not shown) provided within this memory chip. In addition, the active booster circuit 1 of this embodiment
1 and 12, the threshold voltage V _T1 of the transistors Q ₁₄ and Q ₁₅ is 0.3V, the threshold voltage V _T2 of the transistors Q ₁₆ and Q ₁₇ is 1.0 V, and the threshold voltage V _T0 of the other transistors Q ₁₁ to Q ₁₃ is 0.7. It is set as V. Furthermore, the potential Vc of the power supply Vcc is set to 5V.

Next, the operation of the above circuit will be explained with reference to the time chart of FIG. memory cell group 2,
When performing a read/write operation for digit number 3, it is first necessary to precharge digit lines A and B to a predetermined level as described above. In the precharge cycle, the clock generator pulls the precharge signal φp to a potential of about 7V higher than the power supply Vcc, and this signal φp causes the transistors Q ₁₁ ,
_Q12 becomes conductive and digit lines A and B are precharged. At this time, the clock signal _φ1 is also the signal φp.
Similarly, since the potential is raised to about 7V, transistor _Q13 operates as a triode, and node E
becomes the power supply potential Vcc, so the digit lines A and B are precharged to the power supply potential Vc. In addition, the clock signal _φ0 is also boosted and approximately
The potential is 7V, and the transistors Q ₉ and Q ₁₀ are in a triode operating state. In this precharge cycle, nodes C and D connect digit lines A,
Transistors Q ₁₆ and Q ₁₇ turn on from the B side
Pre-charged through. The potential is about 4 V, which is 1.0 V lower than the power supply voltage of 5 V by the threshold potential of these transistors Q ₁₆ and Q ₁₇ . In this way, capacitors C ₁ and C ₂ are precharged to about 4V. At this time, transistors Q ₁₄ and Q ₁₅
is in the cut-off state, and the signal φSA is also set to the precharge level.

Next, when an active cycle is entered by a chip enable signal or the like, data and reference signals are read out from one of the selected memory cells 2 and 3 and the dummy cell to the digit lines A and B, and the sense amplifier 10 operates. . That is, first, the clock signal _φ1 changes from the boosted level of approximately 7V to the power supply potential Vc (5V).
As a result, the transistor _Q13 is temporarily cut off. Next, the precharge signal φp drops to 0V, and the transistors Q ₁₁ and Q ₁₂
is off, so node E and digit lines A and B
be separated from. At this time, the potential of node E is
Due to the coupling between the gate and drain capacitance of transistors Q ₁₁ and Q ₁₂ , the voltage drops from the power supply Vcc level, and stops (clamped) when it drops by the threshold voltage of transistor Q ₁₃ . Therefore, the potential of node E changes from the power supply potential of 5V to
The threshold voltage of _Q13 (0.7V) has decreased to about 4.3V. Next, the readout line of one of memory cells 2 and 3 and the dummy cell (not shown) becomes about 7V,
The stored data and reference signal are output to digit lines A and B. These information signals are transmitted to both terminals of the flip-flop 6 of the sense amplifier 10 through transistors Q ₉ and Q ₁₀ which are in an on state. Immediately thereafter, the sense amplifier drive signal φSA becomes 0V while drawing a slow curve, so the sense amplifier 10 senses and amplifies the minute signals of information appearing on the digit lines A and B. In this way, the digit lines A and B become the high potential "1" level or the low potential (0V) "0" level. As described above, this "1" level drops from the precharge level (5V) to about 3.5V.

Now, as a result of the sensing operation described above, if digit line B goes to the "0" level and digit line A goes to
Suppose that each reaches the "1" level. Then, transistor _Q17 turns on, and node D is discharged to 0V. This drop in node D to 0V causes transistor _Q15 to remain off. Node E further decreases due to the coupling of transistor _Q17 due to the discharge of node D, etc. Since the level of the clock signal _φ1 is the power supply potential of 5V, the potential of the node E is fixed at a potential of 4.3V, which is lowered by the threshold voltage of the transistor _Q13 (0.7V). Even in this situation, the transistor
_Q16 is in a cut-off state with its drain at 4V, gate at 4.3V, and source at 3.5V. Therefore, the charge at node C will not leak to digit line A through transistor _Q16 .

Next, when the boost clock signal φ goes to the "1" level, the node C is bootstrapped by the capacitor _C1 . Therefore, if the "1" level of boosted clock signal φ is 5V, the potential of node C will be about 7V. This turns transistor _Q14 on, and as mentioned above, approximately
The potential level of digit line A, which is at 3.5V, is restored to the power level of approximately 5V. In this case, the threshold voltage of this transistor Q ₁₄ (Q ₁₅ in the active booster circuit 12) is that of a normal transistor.
Since it is lower than that of Q ₁₁ and Q ₁₂ , the conductance of transistors Q ₁₄ and Q ₁₅ can be increased, and the potential of digit lines A and B can be raised to the power supply potential of 5V more quickly and reliably. . The information appearing on the digit lines A and B is read out via the transistors Q ₂₁ and Q ₂₂ , while the 5V potential of the digit lines A and B is rewritten as information in the memory cells 2 and 3. Ru.

According to the active booster circuit described above, since it is configured with transistors having mutually different threshold voltages, it is possible to reliably restore the rewrite potential to the memory cells 2 and 3 to the power supply potential faster than in the past. I can do it. Particularly in the case of a dynamic ratioless sense amplifier, the height of the "1" level changes depending on the magnitude of the signals from the memory cells 2 and 3, and the smaller the signal, the lower the potential level of the "1". Therefore, if the active booster circuit of the present invention is used, the sense amplifier can take a lower "1" level potential, so it can stably sense even a smaller signal than before. Therefore, the sense circuit becomes highly sensitive, which increases the reliability of the product, helps improve the operating margin, and improves the yield. Furthermore, since even smaller signals can be sensed stably, the memory cell can be made smaller accordingly, and the chip size can be reduced, contributing to lower product costs and improved yields.

Furthermore, since the potential rewritten to the memory cells 2 and 3 is reliably the power supply voltage, the logic amplitude level of "0" and "1" in the memory cells 2 and 3 becomes the same as the power supply voltage. This facilitates the design of reference potentials using dummy cells, contributing to improved product reliability. Furthermore, since the digit line on the logic "1" side is connected to the power supply Vcc via the transistors Q ₁₄ and Q ₁₅ , the digit line does not become floating even after the sensing operation in the active cycle is completed. It becomes resistant to fluctuations in substrate potential (back bias) and various types of noise, significantly improving product reliability.

An important feature of the present invention is to adjust and optimize the threshold voltages of the individual transistors constituting the active booster circuit. This threshold voltage is generally adjusted by changing the impurity concentration of the silicon substrate under the gate oxide film by ion implantation. In this case, the manufacturing process requires IC masks for the different threshold voltages of MOS transistors in one chip. For this reason, as the number of vapor depositions increases, the number of ion implantations also increases, resulting in an inconvenience that the manufacturing cost increases. Therefore, in the present invention, the MOS transistor of the active booster circuit is
The above-mentioned disadvantages are solved by introducing the two-dimensional effect of MOS transistors. That is, the low threshold voltage transistors Q ₁₄ , Q ₁₅ of this circuit
Short channel MOS transistors are used for , and narrow channel MOS transistors are used for high threshold voltage transistors Q ₁₆ and Q ₁₇ .
For example, the threshold voltage of a normal MOS transistor is
In order to obtain 0.7V, the channel length is, for example, 3μ, and the channel width is, for example, 10μ or more. So the threshold voltage of the transistor
Q ₁₄ and Q ₁₅ have threshold voltages of about 0.3 to 0.4 V when the channel length is 2 μ. In addition, the high threshold voltage transistors Q ₁₆ and Q ₁₇ have a channel width of 3μ.
, the threshold voltage will be around 1.0 to 1.2V. By utilizing such a two-dimensional effect, ion implantation into the channel can be performed only once, which is effective in simplifying the manufacturing process and reducing manufacturing costs.

Note that the present invention is not limited to the above-mentioned embodiments, but can also be applied to high-speed static RAM signal lines and CPU bus lines.

As explained above, according to the present invention, by configuring an active circuit used in a dynamic RAM or the like with MOS transistors having different threshold voltages, an active booster circuit that effectively boosts voltage and improves reliability can be created. Can be provided.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram of a memory peripheral circuit using a conventional active booster circuit, Figure 2 is a time chart for explaining the operation of the circuit in Figure 1, and Figure 3 is a circuit diagram of a memory peripheral circuit using a conventional active booster circuit. FIG. 4 is a circuit configuration diagram of the memory peripheral circuit used, and is a time chart for explaining the operation of the circuit of FIG. 3. 10...Dynamic ratioless sense amplifier, 2, 3...Memory cell, 11, 12...Active booster circuit, _Q11 to _Q13 ...Ordinary MOS transistor,
Q ₁₄ , Q ₁₅ ...Low threshold voltage MOS transistor, Q ₁₆ ,
_Q17 ...High threshold voltage MOS transistor, A, B...digit line, C, D, E...node, _C1 , _C2 ...capacitor, φ...boost clock signal, φp...precharge signal, _φ0 , _φ1 ...clock signal.

Claims (1)

[Claims] 1. A first enhancement-type transistor with a threshold voltage of V _T1 whose first terminal is connected to a predetermined signal line and whose second terminal is connected to a power supply; and a second terminal connected to the gate of this transistor. a second enhancement-type transistor having a threshold voltage V _T2 connected to the transistor and having a first terminal connected to the signal line; and one end connected to the gate of the first transistor and the second terminal of the second transistor. and a bootstrap capacitor to which a boost clock signal is input at the other end, and the threshold voltage V _T1 of the first transistor is the threshold voltage V T1 of the second transistor.
An active booster circuit characterized in that the voltage is lower than _T2 (V _T2 >V _T1 ). 2 The channel length of the first transistor is:
2. The active booster circuit according to claim 1, wherein the channel length is shorter than the channel length of the second transistor. 3. The active signal line according to claim 1, wherein the signal line is a digit line between a plurality of memory cells and one dummy cell in a MOS dynamic RAM and a dynamic ratioless sense amplifier. Boost circuit. 4 along with the gate of the second transistor.
The threshold voltage at which the terminal is connected to the power supply, the first terminal is connected to the signal line, and the precharge signal φp is input to the gate is V _T0 (however, V _T2 >V _T0 ≧V _T1 >0)
a third enhancement type transistor;
The first terminal and the second terminal are inserted and connected between the connection point of the second terminal of the third transistor and the gate of the second transistor and the power supply, and the threshold voltage is V _T0 and a clock is applied to the gate. A signal is input to the signal line and the second transistor of the second transistor.
An enhancement-type fourth terminal that sets the connection point to a potential lower than the power supply potential after the precharging of the terminal is completed.
2. The active booster circuit according to claim 1, further comprising a transistor.