JPS6031249A - Substrate for hybrid integrated circuit - Google Patents

Substrate for hybrid integrated circuit

Info

Publication number
JPS6031249A
JPS6031249A JP58140356A JP14035683A JPS6031249A JP S6031249 A JPS6031249 A JP S6031249A JP 58140356 A JP58140356 A JP 58140356A JP 14035683 A JP14035683 A JP 14035683A JP S6031249 A JPS6031249 A JP S6031249A
Authority
JP
Japan
Prior art keywords
substrate
recognition
mark
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58140356A
Other languages
Japanese (ja)
Inventor
Kenji Higashiyama
健二 東山
Yasuhiro Kishi
岸 安洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58140356A priority Critical patent/JPS6031249A/en
Publication of JPS6031249A publication Critical patent/JPS6031249A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Abstract

PURPOSE:To accurately and rapidly recognize a pattern by forming a special shape on a substrate, and using it as for recognizing the pattern. CONSTITUTION:A high resistance paste having, for example, 100kOMEGA or larger is printed and dried in a square of 1.5-2.0mm. on a portion 4, on which the circuit of a white ceramic substrate 1 is not formed, and conductive paste 6 of triangular shape is then printed and dried on the center. When a wire bonding is performed, four positions of a recognition mark formed after fixing on the substrate are pattern-recognized, and wire-bonded. Thus, since the resistor 5 has very high contrast due to gold or silver triangular mark 6, a recognition mistake can be eliminated. Since the accuracy of printing the recognition mark is high due to the same screen as the bonding pad, and the position of the substrate can be recognized by the accuracy within + or -10mum.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、混成集積回路用基板に関し、特にその製造を
自動化する場合の基板上の位置を自動的に検出するだめ
の認識用マークに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a hybrid integrated circuit board, and more particularly to a recognition mark for automatically detecting the position on the board when automating the manufacturing thereof. .

従来例の構成とその問題点 一般に、ICf、ブ等の部品を基板上に直接貼りつけ、
金あるいは、アルミニウム線で結線する場合、基板側の
ボンディグノくラドは、非常に/j・さく高密度になっ
ているため、完全な自動ワイヤーボンディングにおいて
は、基板上の基準面(2辺)あるいは、基準穴をもうけ
、その面あるいは穴を基準にボンディングしている。ま
た、特別な場合は、基板上の回路の一部を使用し、それ
を、ノ々ターン認識し行なっている。例えば、第11ス
に示しだ如く基板1上に形成された導体回路2の御名l
S3を使用し、それをノリーン認識し実施し一部いる。
Conventional configuration and its problems In general, parts such as ICf and BU are directly pasted on the board,
When connecting with gold or aluminum wire, the bonding wire on the board side is extremely dense, so in fully automated wire bonding, the reference plane (two sides) or , a reference hole is created and bonding is performed using that surface or hole as a reference. Also, in special cases, a part of the circuit on the board is used and it is recognized in many turns. For example, as shown in the 11th step, the name of the conductor circuit 2 formed on the substrate 1 is
Some people use S3, recognize it, and implement it.

傭ギの土圧で2汁 其惟面あ乙いは、基準穴トホンディ
ングパッド部では、±150μm程度あるいは、それ以
上の誤差が発生するし、基板固定がメカ的になるため誤
差が生じる。この2つの誤差を累積すると、±200μ
m以上にもなり、ポンディングパッドから、はずれる場
合も生じていた。
On the other hand, an error of about ±150 μm or more will occur in the reference hole and landing pad part, and errors will occur because the board is fixed mechanically. Cumulatively, these two errors are ±200μ
m or more, and there were cases where it came off from the bonding pad.

また後者の場合、一般的な厚膜混成集積回路の場合、白
色セラミック基板を用い、Acr/pd導体を用いて回
路形成するが、第1図に示した部分でパターン認識した
場合、位置精度は出ているが、導体2と基板1の色調に
大差がないため認識出来ない場合がしばしば発生してい
た。
In the latter case, in the case of a typical thick film hybrid integrated circuit, a white ceramic substrate is used and the circuit is formed using Acr/PD conductors, but when the pattern is recognized in the part shown in Figure 1, the position accuracy is However, since there is not much difference in color tone between the conductor 2 and the substrate 1, it often occurs that the color cannot be recognized.

発明の目的 本発明はこのような従来の欠点を除去するものであυ、
正確かつ迅速にパターン認識出来る混成集積回路用基板
を提供するものである。
OBJECT OF THE INVENTION The present invention obviates such conventional drawbacks.
The present invention provides a hybrid integrated circuit board that allows accurate and rapid pattern recognition.

発明の構成 本発明の基板は、基板の1ケ所以上の部分に基板の色調
とコントラストの太きい、かつ周辺に類似したパターン
のない特別な形状(三角形、丸形。
Structure of the Invention The substrate of the present invention has a special shape (triangular, round, etc.) that has a thick contrast with the color tone of the substrate in one or more parts of the substrate and has no similar pattern around the periphery.

四角形etc )を形成し、それをパターン認識に使用
するものであり、その位置精度、誤認識のない回路基板
を提供するものである。
This method forms rectangles (etc.) and uses them for pattern recognition, and provides a circuit board with positional accuracy and no erroneous recognition.

実施例の説明 以下本発明の1実施例を図面を参照に説明する。Description of examples An embodiment of the present invention will be described below with reference to the drawings.

ICチップを基板上のバンドにワイヤーボンドする場合
について説明する。第2図に示した如く、白色セラミッ
ク基板1の回路形成されてない部分(特に対角線上の離
れた所が望ましい)4に100にΩ以上の高抵抗ペース
ト(Ru02系)を第3図の5の様に1.5〜2.0m
m角に印刷、乾燥後その中心部に三角形をした導体ペー
スト6(金ペーストあるいはA(1/1:ldペースト
など)を印刷乾燥する。
A case where an IC chip is wire-bonded to a band on a substrate will be explained. As shown in FIG. 2, a high resistance paste (Ru02 series) of 100Ω or more is applied to a portion 4 of the white ceramic substrate 1 where no circuit is formed (particularly a diagonally distant location is desirable). 1.5~2.0m like
After printing on m squares and drying, a triangular conductor paste 6 (gold paste or A (1/1: ld paste, etc.)) is printed and dried in the center.

この三角マーク6は、基板上のワイヤボンディング用バ
ンド形成用導体と同一材木1、同一スクリーンで形成す
ることが最も望捷しい。
It is most desirable to form this triangular mark 6 using the same material 1 and the same screen as the wire bonding band forming conductor on the board.

次に使用したペーストの最適条件(86o〜960°C
1時間)で焼成する。この本発明の基板を用い、ワイヤ
ボンドする場合は、基板固定後、形成した認識マークの
4ケ所をパターン認識し、ワイヤーボンドする。この方
法に従えば、抵抗体6が黒色、三角マーク6が金あるい
は銀色のため非常にコントラストがあり、認識ミスが皆
無になるだけでなく、ポンディングパッド部と同一スク
リーンで認識マークを印刷するため精度が良く、±10
μm以内の精度で基板の位置認識が出来、高精度なワイ
ヤボンドが出来る。
Next, the optimum conditions for the paste used (86o~960°C
Bake for 1 hour). When wire bonding is performed using the substrate of the present invention, after fixing the substrate, pattern recognition is performed on the four recognition marks formed, and wire bonding is performed. If this method is followed, the resistor 6 is black and the triangular mark 6 is gold or silver, so there is a great contrast, and not only is there no recognition error, but the recognition mark is printed on the same screen as the bonding pad. Therefore, the accuracy is good, ±10
It is possible to recognize the position of the board with an accuracy of within μm, making it possible to perform high-precision wire bonding.

以上の実施例においては、非常に高精度な、位置認識用
マークの形成法を述べたが、認識精度が±10011m
でも使用出来る場合には、前記実施例で示した抵抗体6
を省略することが出来る。
In the above embodiment, a method of forming a mark for position recognition with very high accuracy was described, but the recognition accuracy was ±10011 m.
However, if it can be used, the resistor 6 shown in the above embodiment
can be omitted.

すなわち、第2図に示した白色セラミック基板1の4の
位置に抵抗体ベース) (RuO2系)を用いて直接三
角マークを印刷、焼成して認識用マークとして使用出来
る。この方法においては、ワイヤボンド用バンドと認識
マークとが異なったスクリーンで印刷されるため、スク
リーンの位置合せ誤差が生じるため前の実施例に較べ若
干精度は低下する。しかし生産コストは安くなる特徴が
ある。
That is, a triangular mark can be directly printed on position 4 of the white ceramic substrate 1 shown in FIG. 2 using a resistor base (RuO2 based) and fired, and used as a recognition mark. In this method, since the wire bond band and the identification mark are printed on different screens, the accuracy is slightly lower than in the previous embodiment due to screen alignment errors. However, the production cost is low.

以上の2つの実施例においては、白色セラミック基板を
用いる場合についで説明したが、有色基板(例えば、黒
色基板)を用いる場合には、次の構成で精度よく基板の
位置認識が出来る。
In the above two embodiments, the case where a white ceramic substrate is used has been explained, but when a colored substrate (for example, a black substrate) is used, the position of the substrate can be recognized with high accuracy with the following configuration.

すなわち、第2図に示した基板1の4の部分にワイヤボ
ンディング用パッドと同一スクリーン上に認識用三角マ
ークを形成しそれを用いて導体を印刷、乾燥、焼成する
。本実施例に従えば、製造コス)upなしに±1oμm
以内の精度でパターン認識出来るマークを基板」二に形
成することが出来る。
That is, a triangular mark for recognition is formed on the same screen as the wire bonding pad at a portion 4 of the substrate 1 shown in FIG. 2, and the conductor is printed, dried, and fired using the triangular mark. According to this embodiment, ±1oμm can be obtained without increasing manufacturing cost.
It is possible to form marks on a substrate that can be recognized as a pattern with accuracy within

以上の3つの実施例においては、認識マークを回路形成
用の導体、抵抗ペーストを用いる構成について述べたが
、それ以外に基板とコントラストの大きい有色顔料を印
刷、硬化してなる認識マークも出来る。すなわち、白色
基板には黒色や青色などのエポキシ樹脂を用いて認識マ
ークを形成し硬化した後、使用する。本方式に従えばい
かなる色の認識マークをも形成する事が出来、かつ、低
温で硬化出来る。寸だ、マーク認識方法も白、黒のパタ
ーン認識以外に、カラーカメラによる色認識が出来、認
識率の向上に大きな効果を生じる。
In the above three embodiments, the configuration in which the recognition mark is made of a circuit-forming conductor or resistive paste has been described, but other than that, a recognition mark can also be made by printing and curing a colored pigment that has a high contrast with the substrate. That is, a recognition mark is formed on a white substrate using a black or blue epoxy resin, and the epoxy resin is cured before use. According to this method, recognition marks of any color can be formed and can be cured at low temperatures. In addition to white and black pattern recognition, the mark recognition method uses a color camera to recognize colors, which has a significant effect on improving the recognition rate.

発明の効果 以上のように本発明によれば従来法で発生していた、ワ
イヤボンディングのセカンドの位置ズレに起因する不良
はなくなり混成集積回路自体の信頼性も犬1〕に向上す
ることが出来る。また、回路導体の1部を認識用に使用
していた従来法における認識ミス、も完全に解決するこ
とが出来る。なお、実施例については、ワイヤボンディ
ング用ニついて説明したが、それ以外の部品実装用に摘
要出来ることは勿論のこと、セラミック基板以外の基板
に摘要出来ること社、言うまでもない。壕だ認識マーク
についても本実施例で述べた以外の形状も使用出来るこ
とは、説明するにおよばない。
Effects of the Invention As described above, according to the present invention, the defects caused by the positional deviation of the second wire bonding, which occurred in the conventional method, are eliminated, and the reliability of the hybrid integrated circuit itself can be improved to 1). . Furthermore, the recognition errors caused by the conventional method in which a part of the circuit conductor is used for recognition can be completely resolved. Although the embodiments have been described for wire bonding, it goes without saying that the present invention can be applied to other types of component mounting as well as to substrates other than ceramic substrates. It is unnecessary to explain that shapes other than those described in this embodiment can also be used for the trench recognition mark.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の混成集積回路用基板の1部を示す平面
図、第2図は本発明の混成集積回路用基板の一実施例を
示す平面図、第3図aは同要部拡大平面図、bは同安部
断面図を示した。 1・・・・・・セラミック基板、2・・・・・・回路導
体、3・・・・・・認識部分、4・・・・・・認識マー
ク形成部分、6・・・・・・認識用抵抗体、6・・・・
・・認識用マーク。
Fig. 1 is a plan view showing a part of a conventional hybrid integrated circuit board, Fig. 2 is a plan view showing an embodiment of the hybrid integrated circuit board of the present invention, and Fig. 3a is an enlarged view of the same main part. Plan view, b shows a sectional view of the same part. 1...Ceramic substrate, 2...Circuit conductor, 3...Recognition part, 4...Recognition mark forming part, 6...Recognition Resistor for use, 6...
・Recognition mark.

Claims (1)

【特許請求の範囲】[Claims] (1)基板の1ケ所以上の部分に、その基板の色調と異
なる色あるいは、コントラストの大きい所定の形状をし
たマークを配置した混成集積回路用基板0 (功 白色セラミック基板上の一部に抵抗ペーストを印
刷し、その中心部に所定の形状に導体ペーストを印刷、
焼成してマークとすることを特徴とする特許請求の範囲
第1項記載の混成集積回路用基板0 (′jI 有色基板上の回路形成部と関係のない部分に
所定の図形の導体ペーストを印刷、焼成してマークとす
ることf:特徴とした特許請求の範囲第1項記載の混成
集積回路用基板。 (4白色セラミック基板の回路形成されてない部分に、
抵抗ペーストを用いて所定の形状のバター−7シー&−
汁 + −−hI−−J−7> I−f−#I:9Mr
 I−1嘉ル#ヲ[丑李求の範囲第1項記載の混成集積
回路用基板。
(1) A hybrid integrated circuit board 0 in which a mark in one or more parts of the board is marked in a color different from that of the board, or in a predetermined shape with a large contrast. Print the paste and print the conductive paste in a predetermined shape in the center,
Substrate 0 for a hybrid integrated circuit according to claim 1, characterized in that the mark is formed by firing ('jI) Printing a conductor paste of a predetermined shape on a portion of the colored substrate not related to the circuit formation portion , firing to form a mark f: A board for a hybrid integrated circuit according to claim 1 characterized in (4) In the part of the white ceramic board where no circuit is formed,
Butter-7 sea &- in the specified shape using resistance paste
Juice + --hI--J-7>I-f-#I: 9Mr
I-1 The substrate for a hybrid integrated circuit according to item 1 of the scope of the invention.
JP58140356A 1983-07-29 1983-07-29 Substrate for hybrid integrated circuit Pending JPS6031249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58140356A JPS6031249A (en) 1983-07-29 1983-07-29 Substrate for hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58140356A JPS6031249A (en) 1983-07-29 1983-07-29 Substrate for hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6031249A true JPS6031249A (en) 1985-02-18

Family

ID=15266917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58140356A Pending JPS6031249A (en) 1983-07-29 1983-07-29 Substrate for hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6031249A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715435A (en) * 1980-06-30 1982-01-26 Nec Home Electronics Ltd Substrate for semiconductor device
JPS5785240A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd Semiconductor device
JPS5759447B2 (en) * 1974-12-25 1982-12-15 Hitachi Ltd

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759447B2 (en) * 1974-12-25 1982-12-15 Hitachi Ltd
JPS5715435A (en) * 1980-06-30 1982-01-26 Nec Home Electronics Ltd Substrate for semiconductor device
JPS5785240A (en) * 1980-11-17 1982-05-27 Fujitsu Ltd Semiconductor device

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