JPS6029418B2 - Memory - How to use it - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of using memory in an electronic exchange, such as a central control unit.

Conventionally, storage devices (hereinafter referred to as memories) used in central control units such as electronic exchanges include read-only storage circuits and temporary storage circuits. At this time, when used as a storage area of a read-only memory circuit and a temporary memory circuit, the storage area of the read-only memory circuit and the storage area of the temporary memory circuit are limited by the memory capacity of the integrated circuit used for each, and are limited by the address. Separated. This has a size of 250 bytes, 1 kilobyte, 2 kilobytes, etc. Therefore, the boundaries of the memory castle below this are not established. Another disadvantage of this machine was that a part of the storage area of the read-only memory circuit could not be used as a temporary memory circuit. An object of the present invention is to provide dual read-only storage circuits and temporary storage circuits having storage areas at the same address, and to write a read-only storage circuit at the address (hereinafter referred to as an address) of the storage area desired to be used as the temporary storage circuit. The purpose of this invention is to provide a memory usage method that allows any address to be used as a temporary memory circuit by setting the contents of the circuit (hereinafter referred to as data) to a certain value. Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating a first embodiment of the present invention.

In FIG. 1, the read-only memory circuit ROM and the temporary memory circuit RAM are already at the same address (in this case, SOO
From O Tochimitsuji to SO Misaki F address. Here S is 16
Indicates a base number. ) is set. Furthermore, addresses SOOOO to S of the read-only memory circuit ROM are
O07F contains valid data, and address SO08
It is assumed that 0 has already been written from 0 to SO Misaki F. Under this condition, the central processing unit CPU reads SO08 of the read-only memory circuit ROM and the temporary memory circuit RAM.
The following describes the case where the contents of address 0 are read. First, address information from the central processing unit CPU passes through the address bus and specifies the respective read-only storage circuit ROM or temporary storage circuit RAM.

Here, the upper 8 bits of the address information are converted to the terminal CSO or CSI as a chip select signal. Further, the lower 8 bits of the address information are input as they are to the read-only memory circuit ROM or the temporary memory circuit RAM. In the case of the present invention, since the same address is set for the read-only storage circuit and the temporary storage circuit, signals arrive at the terminals CSO and CSI at the same time. In addition, terminals AOO to A07 of the read-only memory circuit ROM and temporary memory circuit RAM
At the same time, the lower 8 bits of the address information are input to the address information.
Further, the read-only memory circuit ROM outputs data at the address specified by the terminal CSI and the terminals AOO-A07 to the output terminals DOO-07. Here, SO080
Since the address data is 0, DOO to D07 are all 0. This information is provided by gates BO to B7.
It is ANDed with the memory read/write signal. As a result, the output terminal DOO of gates BO to B7
All information from ' to D07' becomes 1. Similarly, the temporary storage circuit RAM outputs data at the address specified by the terminal CSO and the terminals AOO to A07 to the terminals DAO to DA.
7, and the AND with the memory read/write signal is negated by gates AO to A7. As a result, this information is transferred to the output terminals DAO'-D of gates AO-A7.
It is output to A7. Further, these pieces of information are logically ORed by wired OR circuits CO to C7. By performing a wired OR, ie, logical product, of these pieces of information, the data in the read-only memory circuit ROM ultimately serves to open the gate to the data in the temporary memory circuit RAM. That is, the data in the read-only memory circuit ROM can be invalidated and only the data in the temporary memory circuit RAM can be effectively read. Also, for writing data, the same device can be used as a temporary memory circuit RAM.
In this way, the data in the read-only memory circuit ROM is set to 0.
R from SO080 address set as 0 to SO Misaki F address
Can be used as AM, S from SOOOO address
Address O07F can be used as a ROM. As described above, by setting the contents of any address in the read-only memory circuit ROM to 0, that part can be used as a temporary memory circuit.

Further, in the first embodiment of the present invention, gates AO to A7 and B
Although NAND gate circuits are used for gates O to B7, it is also possible to use AND gate circuits for gates AO to A7 and BO to B7 as a second embodiment. In the case of this second embodiment, by setting the address data of the read-only memory circuit ROM to 1, it can be partially used as a temporary memory circuit in the same machine. As explained above, by setting the storage area used as a read-only memory circuit as described above, the present invention enables the temporary memory circuit to be used even when the storage capacity of the read-only memory circuit and the temporary memory circuit is below. It has the advantage of being able to set the storage area.

Further, it is also possible to use only an arbitrary portion of the storage area of the read-only storage circuit as a temporary storage circuit.
This is a very effective method, especially when modifying a program. Note that in the case of the first embodiment of the present invention, it is necessary to connect an inverter to the output terminals DO to D7, but in the case of the second embodiment, this is not necessary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a first embodiment of the present invention. RAM: Temporary memory circuit; ROM: Read-only memory circuit. younger brother l figure

Claims (1)

[Claims] 1. A read-only storage circuit and a temporary storage circuit having storage areas at the same address are provided, and the read-only storage circuit and the temporary storage circuit set the contents of the read-only storage circuit at an address where the storage area overlaps to a specific value. The storage area at that address is partially used as a temporary storage circuit by obtaining the logical product information of the information obtained from the read-only storage circuit and the information obtained from the temporary storage circuit. Memory usage.