JPS6225347A - Memory control system - Google Patents

Abstract

PURPOSE:To assign the areas of a ROM and a RAM as well which are below the storage capacity of an IC as a RAM by setting the storage contents of specific addresses in the storage area of the ROM to a specific value and using the specific addresses as the RAM only at the time of the specific value. CONSTITUTION:The same addresses are assigned to the ROM 2 and RAM 1. Address information from a CPU specifies the ROM 2 or RAM 1. When the contents of the ROM in specific addressed are set to 00H and data outputs D00-D07 are all 0, an OR circuit D6 outputs 0, which is ANDed with a memory read/write signal by an AND circuit F1 to output 0. Outputs of NAND gates B0-B7 are therefore all 0. The output 0 of the OR circuit D6. on the other hand, is set to 1 by a NO circuit E, the AND circuit F01 outputs 1, and NAND circuits A0-A7 output the NOT of the data DA0-DA7, so that the output of the RAM 1 appears at outputs of exclusive OR circuits C0-C7.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory control system, and particularly to an electronic switching system (
This invention relates to a method for controlling the use of memory devices such as central control units.

Prior Art Conventionally, storage circuits (hereinafter referred to as memories) used in central control units such as electronic exchanges include read-only storage circuits and temporary storage circuits, and the storage areas of each are determined at the time of circuit design. The area cannot be changed later.

In the conventional memory usage method described above, the read-only storage circuit and the temporary storage circuit are limited by the storage capacity of the integrated circuit used and are separated by addresses. These elements are 1 kilobyte.

2 kilobytes...16 kilobytes, and the Higashi Sekido is gradually increasing. On the other hand, pJ allocation of storage areas at the time of circuit design depends on the size of these elements, making it impossible to make other detailed allocations.

Another disadvantage is that a part of the storage area of the read-only storage circuit cannot be used as a temporary storage circuit.

OBJECTS OF THE INVENTION An object of the present invention is to provide a memory control system that allows even areas below the storage capacity of an IC for read-only storage circuits and temporary storage circuits to be allocated as temporary storage circuits.

Another object of the present invention is to provide a memory control method that can use any part of the area of a read-only storage circuit as a temporary storage circuit.

Composition of the Invention A memory control method according to the present invention is a control method for a memory circuit having a read-only storage circuit and a temporary storage circuit, wherein the storage areas of the read-only storage circuit and the temporary storage circuit are located at the same address. , the storage contents of a predetermined location in the storage area of the read-only storage circuit are set to a specific value, the predetermined location is used as a temporary storage circuit only when the specific value is set, and the storage contents of a predetermined location in the storage area of the read-only storage circuit are used as a temporary storage circuit; The device is characterized in that it can be used as a read-only storage circuit when .

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

The figure is a circuit diagram of a memory circuit of the present invention. In the figure, the read-only memory circuit ROM2 and the temporary memory circuit RAM1 are allocated to the same address.

First, address information from the CPU (not shown) passes through an address bus to specify ROM2 or RAM1. Here, the upper 8 bits of the address bus are converted to the chip select terminal C8O or C81 as a chip select signal. Also, the lower 8 bits are stored in ROM or RA as they are.
It is input to each address terminal AOO to AO7 of M.

In the case of this embodiment, since ROM and RAM are assigned to the same address, chip select terminals C8O and C31
A signal is simultaneously input to and. Further, the lower 8 bits of the address information are simultaneously input to the address terminals AOO-AO7 of the ROM and RAM.

Further, the ROM2 stores data at addresses designated by terminal C81 and signals from terminals AOO to AO7.

Output to O~007.

Here, the contents of the ROM at a specific address are OOH (H is 1
(indicates a hexadecimal number). The OR circuits DO-D7 generate the logical sum of the data outputs DOO-DO7, and the data 0
When 00-DO7 are all O, OR circuit [)6 outputs 0, and this output and memory read/write (MEM R
/W) signal is generated in AND circuit F1, and O is outputted. Nant gates BO to B7 will be closed by this output. Therefore, each gate BO~B
7's outputs 000' to DO7' are all O.

At this time, RAM1 also has chip select terminal C8O.
and address terminals AOO to AO7, and outputs the data at the address specified by each signal to the data terminals DAO to DA7.

On the other hand, the output O of the OR circuit D6 is set to 1 by the NOT circuit E, and this output and the memory read/write signal are ANDed by the AND circuit FO and 1 is output. Nant gates AO to AI are opened by this signal, and each output DA
The negative of each data DAO to DA7 is output to O' to DA7'.

CO to CI are exclusive OR circuits, and ROM
2 and RAMI are ORed.

Now, since the data DOO' to DO7' are all 0, the outputs DAO to DA7 of the RAM 1 are output to the outputs DO to DI of the exclusive OR circuits CO to CI.

Conversely, when the contents of the ROM2 at a certain address are other than O, the output of the OR circuit D6 becomes 1, and the output of the AND circuit F1 becomes 1, opening the gate BO-37. At this time, the output of the AND circuit FO is O, and the gate A
O to A7 are closed. Therefore, the contents of ROM2 DOO~
DO7 is output to DO-D7.

In this way, by setting the contents of an arbitrary address in ROM2 to 0, the contents of RAM1 can be made valid, and at other times, the contents of ROM2 can be made valid. Furthermore, it is obvious to those skilled in the art that the same effect can be obtained by replacing the OR circuits DO to D6 with AND circuits and setting the contents of the ROM2 to FFI- ((000 to ()07S total 71)).

Effects of the Invention As explained above, according to the present invention, by setting the storage area used as a read-only memory circuit as described above, the IC memory of the read-only memory circuit and the temporary memory circuit can be improved. It has the advantage of being able to be allocated as a temporary memory circuit even in an area that is less than 100m tall. It is also possible to use only an arbitrary part of the area of the read-only memory circuit as a temporary memory circuit.

[Brief explanation of the drawing]

The figure is a circuit diagram of an embodiment of the present invention. Explanation of symbols of main parts 1...Temporary memory circuit

Claims (1)

[Claims] A control method for a memory circuit having a read-only memory circuit and a temporary memory circuit, wherein the same address is assigned to the storage areas of the read-only memory circuit and the temporary memory circuit, and the storage area of the read-only memory circuit is The memory content of a predetermined location within the area is set to a specific value, and the predetermined location is used as a temporary storage circuit only when the specific value is present, and used as a read-only memory circuit when the value is not the specific value. A memory control method characterized by: