JPS6029031A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To make a A/D converter more high-accurate and to simplify constitution of the A/D converter by adding a subtraction circuit to the A/D converter. CONSTITUTION:Plural subtraction circuits 11, 12-1m are provided to a basic i-bit A/D converter 22 and analog voltages V1, V2-Vm are inputted to the input terminals of respective subtraction circuits 11, 12-1m, thereby subtracting the reference voltage VR. When subtraction cannot be performed by respective subtraction circuit 11, 12-1m, the most significant n bit OBn-OB1 of digital conversion output of input analog voltage V1 are outputted from a decoder. In addition, output Vm+1 of the last subtraction circuit 1n is added to a converter 22. Reference voltage VR is added to the converter 22, and the voltage VR is converted as full scale voltage to 1-bit digital data, thereby outputting from an output buffer 24. Thus, the A/D converter is made more accurate and the A/D converter 22 is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an analog-to-digital (AD) converter in which an AD converter is provided with an additional circuit to improve accuracy.

Prior Art and Problems In recent years, systems using microcomputers have been actively developed, and with this, the importance of AD converters has increased, leading to the emergence of low-cost, single-power, high-speed, and high-precision AD converters. is desired. AD converters include successive approximation type and multiple integral type. For the successive approximation type, the input voltage V
First, compare it with half of the full scale voltage FS, Fs/2, and check whether it is higher (older or lower (L)). The operation of comparing H and L is repeated to sequentially determine the lower bits from the upper bits of the digital conversion output.

These comparison voltages FS/2.3FS/4.・・・・・・
is created by a DA converter, and this DA converter creates an analog output voltage with a resistance ladder circuit, so the resolution of the successive approximation type AD converter is ultimately determined by the accuracy of the resistance ladder inside the XC (that of the DA converter above). At present, resistance ladders that are inexpensive and suitable for mass production are 8 bits at most.

The multiple integration type charges a capacitor with an analog input voltage, discharges it at a constant current, and obtains a digital value by counting the discharge time, so improving accuracy requires improving the linearity of the constant current circuit. This results in a cost increase. The successive approximation type can also achieve high resolution by trimming the resistor ladder with high precision, but this also increases cost.

In this way, aiming for high accuracy in both the successive approximation type and the multiple integral type leads to lower yields and higher costs.

By the way, when input analog voltage ■ is 1/H, i bit A
By keeping it within the full scale voltage of the D converter and converting it to an i-bit digital value, the resolution can be increased by N times. For example, if N = 2, the resolution will be doubled, and if N = 4, the resolution will be 4
If it is doubled, and it is i-8, such an AD converter can be obtained or manufactured normally, so ＼
A high-precision AD converter, such as a 10-bit one, can be obtained using an AD converter.

Purpose of the Invention The present invention focuses on this point, and attempts to obtain an inexpensive and highly accurate AD converter by using an ordinary AD converter as a base and adding an additional circuit for processing input voltage to this. It is something to do.

Structure of the Invention The analog-to-digital converter of the present invention has an i-bit basic A
The reference voltage supplied to the D converter is subtracted from the analog voltage applied to the input terminal, and the difference is output. If the difference is negative, the analog voltage is output as is, and if the difference is O or positive, the difference is output. A subtraction circuit that produces a carry output of "1" and a carry output of "0" when the difference is negative is connected to the 2-1 narrow side row, and the input analog voltage to be converted is connected to the input terminal of this series-connected subtraction circuit group. In addition, the i-bit basic AD converter is connected to the output terminal, and a decoder is further provided that receives the carry output and outputs the upper n bits of the digital conversion output,
The present invention is characterized in that n+i digital conversion outputs are obtained from these decoders and the basic AD converter, which will now be described with reference to embodiments.

Embodiment of the invention FIG. 1 shows an embodiment of the invention, 11.12.・・・・・・
...1m is m subtraction circuits, and analog voltages Vl, V2, . . . are applied to the input terminals.・・・・・・Subtract the reference voltage vR from Vm, the difference V2=Vl-VR, V3=V
2-VR=V l-2VR, --・Vm+ 1=Vm-
VR=Vl Output mVR. Note that if the difference is negative, it becomes a through state and outputs the input voltage as is. When the difference is O or positive, and therefore it can be subtracted, the carry output C101, . . . C/Om is set to 1, and when it cannot be subtracted, the carry output is set to O. The carry output is input to the decoder 20, which decoders the upper n bits of the digital conversion output of the input analog voltage Vl.

Output Bn~OBI. The output Vm++ of the last one of the subtraction circuits is the analog input voltage Ai of the AD converter 22.
It becomes n. The AD converter 22 is an 8-bit ADC in this example, which can be manufactured or obtained easily and inexpensively, and receives a reference voltage vR and sets it as a full-scale voltage, and converts it to Vm.
Analog input voltage A where 10+ = A 3n< VR
It receives ln and converts it into i-bit digital data. , 24 is an output buffer that receives the i-bit data and outputs it in serial or parallel format. A device that receives the conversion output, such as a CPU (central processing unit), takes in the bits OBn to OBI and OUT.

The operation will be explained with reference to Fig. 2 (al is the case where the input analog voltage v+ is in the range of 4VB < V + < 3vR, and in this case, three subtractions are possible (subtraction circuits 11, 12 .13), and the third subtraction result Va=Vm++ is input to the AD converter 22,
Converted to 8-bit digital. The carries output from the subtraction circuits 11 to 1m are 11100...0, and in response to this, the decoder 20 sets the outputs OBn to OB1 to 0.
．． 0-...011. That is, 0B1=OB2=
1. OB3-0Bn=0. In this case, the full-scale voltage can be considered to be 4VR, and input 1 is the reference voltage 2VR (if the full-scale voltage is FS, this is FS
/2) is Hl and 3VR (-3E/4
) is also H, so it is a correct result that the upper two bits (OB2, 0BI) of the digital conversion output are both 1. The bit-to-digital conversion of Vm+1=Ain by the ADC 22 is known.

Figure 2 (bl is the human analog voltage ■1 is 2vR × V〈v
An example of the case where R is within the range will be shown. In this case, subtraction is possible only once, so the carry output is 10...
It is 0. Upon receiving this, the decoder 20 sets 0B1=1. O
Output B2-0Bn=0. The full-scale voltage in this case can be considered to be 2VR, and since the determination result at half VR is H, it is correct that the upper bit OBI of the digital conversion output is 1. These m subtraction circuits 1
1 to 1m are the full scale multiplied by m, and the carry of m1Il from these constitutes the upper n bits of the digital conversion output. Since m subtraction circuits represent m+1 cases including cases where all subtraction circuits cannot perform subtraction, m+1=
2'', therefore, if it is desired to add n bits to the higher order bits, it is efficient to provide 2n-1 subtraction circuits.

For example, if n-1, m=1°; if n=2, m=3. If n=3, m=7.・It is better to set it to ``Old''. Now, as an example, a table showing the correspondence between the carry output and the output of the decoder 20 when there are seven subtraction circuits.

1000000 001 iiioooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo so much

1110000 011 1111000 100 1111100 101 1111110 110 1111111 111 FIG. 3 shows an embodiment of the present invention in which three subtraction circuits are provided and the upper two bits are added to improve the accuracy by four times.

In Figure 3, 11.12.13 is the subtraction circuit of 3111i1,
20 is a decoder, and 22 is a basic AD converter, which in this example is an 8-bit successive approximation type. 26 is a serial interface, which corresponds to the output buffer 24 in FIG. 1, but here outputs 8-bit digital outputs BO to B7 in a serial format. Six types of analog voltages Io~■5 are input to this circuit,
Multiplexer 30 outputs a 3-bit channel selection signal A o
" A 2 selects one of them and sends it to the sample and hold circuit 28. 32 is a capacitor for sample and hold, 34 is a power supply that outputs the reference voltage vR, ST is a conversion start signal, and CLK is a conversion clock.

To explain the operation with reference to FIG. 4, the channel selection signal AoxA2 selects a certain channel (T).

~I5) is selected, and when the conversion start signal ST rises, the basic ADC 22 starts conversion and sequentially outputs the digital output OUT from MSB to LSB at the fall of each clock. Upper 2 bits B9. Since B8 is the decoded value of the subtraction carry, it is output almost simultaneously when the analog input is input, and therefore the conversion ends when the LSB is output. Therefore, next time the channel selection signals An to A2 are switched,
Select the next channel and enter its digital conversion.

Figure 5 shows an integral type AD converter, where Ain is its analog input, vR is the reference voltage, and ST is the start of conversion (start of charging).
The signal sp is a conversion end signal.

Figure 6 is a diagram explaining the operation. When the charging start signal ST is input, a capacitor (not shown) is charged with the analog input voltage Ain, and when the conversion start signal (second ST) is input after charging is completed, the capacitor starts discharging. Then, when the discharge ends, the conversion end signal S
, P is output. Since the digital value of the analog input Ain corresponds to the discharge period TI from the conversion start ST to the conversion end sp, the digital value is obtained by counting this with a microcomputer or the like. In reality, a similar discharge period TR with respect to the reference voltage vR is used, A in = VR - T + /TR
shall be. If the discharge periods TI and TR are short, the measurement accuracy will not improve, so it is necessary to make them longer (the conversion speed will be slower), and if the discharge is not performed linearly, the proportional relationship cannot be maintained and errors will occur. It is necessary to use a high quality linear discharge circuit. Although the integral type AD has such drawbacks, the present invention improves resolution by adding upper bits.
It can also be applied to C. Examples are shown in FIGS. 7 and 9.

FIG. 7 corresponds to FIG. 1, and the same parts are given the same reference numerals. There are no special limitations except that the AD converter 22 is of an integral type.

Since this type of AD converter has a conversion output of 5P-3T as described above, this width B is read by a microcomputer (not shown), and a conversion output is generated together with the upper bits OBn to OBI.

FIG. 9 is a diagram corresponding to FIG. 3, in which the upper two bits 89B8 are added to the output of the 8-bit basic AD converter (integral type) 22 to obtain a 10-bit digital output. 11-13
are three subtraction circuits used to add the upper two bits, and 20 is a decoder for the carry. The same or corresponding parts as in FIG. 3 are given the same reference numerals. Figure 8 is 9
This is an explanatory diagram of the operation in the figure and corresponds to FIG. 2. That is, Fig. 8 (a
) is an example in which the input analog voltage V; is 4vR〈■1〈3vR, and in Fig. 8(b), the vI is 2VR<V + <
Here is an example in VR. As mentioned above, FS indicates full scale and is referred to as FS-4VR. The full scale of an AD converter is often 5■, which means analog human power V+ (this is Io in Figure 9, etc.).

■1. . . . ) is also designed to have a maximum of 5■, so to apply the present invention, VR = FS / 4 =
It is preferable to create 5/4=1.25 (V) and supply this to the AD converter and subtraction circuit. That is, the AD converter is operated at low voltage.

FIG. 10 shows subtraction circuits 11, 12. The configuration of... is shown. These all have the same configuration. 40.42°44
．． 46 is an operational amplifier, 48 is an impark, 50.52 is an analog switch, R is a resistor, T+ and T2 are input terminals to which input voltage Vi and reference voltage vR are applied, T3 and T4 are outputs that produce a carry output and a difference output. It is a terminal. The operational amplifiers 40 and 42 are for impedance conversion and have a gain of 1, and output the input voltage as is. amplifier 44
operates as a comparator, and produces an H (high) level output if V i > VR, and outputs an L level if V' i <' VR
(low) level outputs and these are the carry outputs “
1”.

becomes “0”. The amplifier 46 receives Vi and VR and outputs the difference between them. That is, in this amplifier, the following formula holds true, and the output Vo becomes ViVR.

(V o VR)R/(R+R)+VR=ViR/(R
+R), °, V n =V i VR The analog gate 50.52 is in a through state when the gate (G) input is H, and is in a high impedance (HZ) state when it is L. Therefore, when the output of the comparator 44 is H, the gate 50
is open, the gate 52 is closed, and the output V of the operational amplifier 46 is
o appears through gate 50 to output terminal T4. When the output of the comparator 44 is L, the gate 50 is closed;
2 is opened, and the input voltage Vi appears from the buffer 40 at the output terminal T4.

As described in detail, according to the present invention, it is possible to improve the accuracy of an ordinary AD converter by adding a subtraction circuit, and it is possible to provide an inexpensive, high-precision AD converter with a high yield. It is valid.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a diagram explaining the operation of Figure 1, Figure 3 is a block diagram showing a specific example of Figure 1, Figure 4 is a diagram explaining the operation of Figure 3, and Figure 5 is a block diagram showing an integral type AD converter. 6 is an explanatory diagram of the operation, FIG. 7 is a block diagram showing the first embodiment of the present invention, FIG. 8 is an explanatory diagram of the operation, and FIG. 9 is a block diagram showing a specific example of FIG. 7. , FIG. 10 is a block diagram showing the configuration of the subtraction circuit. In the drawing, 22 is an i-bit basic AD converter, VR is a reference voltage, Vl, V2 . . . . are analog voltages applied to the input terminals, 11, 12 . ... is a subtraction circuit, 2
0 is the upper n bits of decoders OBn to OBI. Applicant: Minoru Aoyagi, Patent Attorney, Fujitsu Ten Limited

Claims (1)

[Claims] (The reference voltage supplied to the 11i-bit basic AD converter is
It subtracts it from the analog voltage applied to the input terminal and outputs the difference. If the difference is negative, it outputs the analog pressure as is, and if the difference is 0 or positive, it outputs the carry output."1
'', a subtraction circuit that produces a carry output of ``0'' when the difference is negative is connected to the 2''-1 control column, the input analog voltage to be converted is applied to the input terminal of this series-connected subtraction circuit group, and the output terminal The i-bit basic AD converter is connected to the i-bit basic AD converter, and a decoder is provided which receives the carry output and outputs the upper n bits of the digital conversion output. An analog-to-digital conversion device characterized in that (2) The analog-to-digital conversion device according to claim 1, wherein the i-bit basic AD converter is a successive approximation type AD converter. (3) The analog-to-digital conversion device according to claim 1, wherein the i-bit basic AD converter is an integral type AD converter.